-- generated by newgenasym Fri Apr 02 12:54:26 2010

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \25aa256_8p_skt\ is
    port (    
	CS_N:      IN     STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	HOLD_N:    IN     STD_LOGIC;    
	SCK:       IN     STD_LOGIC;    
	SI:        IN     STD_LOGIC;    
	SO:        OUT    STD_LOGIC;    
	VCC:       IN     STD_LOGIC;    
	WP_N:      IN     STD_LOGIC);
end \25aa256_8p_skt\;
