-- generated by newgenasym Wed Oct 11 20:10:22 2006

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity FET_DIRECT_2S is
    port (    
	D1:        INOUT  STD_LOGIC;    
	D2:        INOUT  STD_LOGIC;    
	D3:        INOUT  STD_LOGIC;    
	D4:        INOUT  STD_LOGIC;    
	G:         INOUT  STD_LOGIC;    
	S1:        INOUT  STD_LOGIC;    
	S2:        INOUT  STD_LOGIC);
end FET_DIRECT_2S;
