%#################################################################
Title:        Cref Error Report
Design:       stargo
Date:         Jul 11 16:29:09 2013
%#################################################################



Warnings in Page : @stargo_lib.stargo(sch_1):Page18
Signal     CK420_X1_25 at (C 6) is labeled only once in the design.
Signal      CK420_IREF at (B 3) is labeled only once in the design.
Signal TEST_MODE_CK420 at (B 5) is labeled only once in the design.
Signal     CK420_X2_25 at (C 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page21
Signal   CLK_PWRGD_N_R at (D 6) is labeled only once in the design.
Signal    CLK_OSC100_N at (A 3) is labeled only once in the design.
Signal     CLK_PWRGD_R at (C 4) is labeled only once in the design.
Signal       OSC100_EN at (B 4) is labeled only once in the design.
Signal       CLK_PWRGD at (D 7) is labeled only once in the design.
Signal    CLK_OSC100_P at (B 3) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page22
Signal CK1900_OE_N<12..5> at (C 6) is labeled only once in the design.
Signal     DB1900_IREF at (D 2) is labeled only once in the design.
Signal   CK1900_BYPM_N at (C 5) is labeled only once in the design.
Signal   CK1900_A1_TRI at (B 5) is labeled only once in the design.
Signal DB1900_DFB_OUTN at (D 3) is labeled only once in the design.
Signal DB1900_DFB_OUTP at (D 3) is labeled only once in the design.
Signal DB1900_VDD_CORE at (D 6) is labeled only once in the design.
Signal     DB1900_VDDR at (D 6) is labeled only once in the design.
Signal     DB1900_VDDA at (D 6) is labeled only once in the design.
Signal  DB1900_DFB_INP at (D 4) is labeled only once in the design.
Signal  DB1900_DFB_INN at (D 4) is labeled only once in the design.
Signal   CK1900_100M_N at (B 5) is labeled only once in the design.
Signal   CK1900_A0_TRI at (A 5) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page25
Signal DMI_CPU_PCH_TX_DP_N_C<3..0> at (A 5) is labeled only once in the design.
Signal DMI_CPU_PCH_TX_DP_P_C<3..0> at (B 5) is labeled only once in the design.
Signal CPU_PCIE_R_ICOMP at (B 8) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page28
Signal        GDXICOMP at (B 5) is labeled only once in the design.
Signal CPU_DDR_RCOMP<0> at (C 6) is labeled only once in the design.
Signal CPU_DDR_RCOMP<2> at (C 6) is labeled only once in the design.
Signal CPU_DDR_RCOMP<1> at (C 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page29
Signal      CPU_PECI_R at (C 5) is labeled only once in the design.
Signal CPU_VID_ALERT_N_R1 at (B 6) is labeled only once in the design.
Signal   CPU_PROCHOT_N at (C 5) is labeled only once in the design.
Signal CPU_DDR_RESET_N at (D 5) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page31
Signal     VCCFUSE_CPU at (B 5) is labeled only once in the design.
Signal     VR_VTT_RGND at (B 7) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page35
Signal   CPU_JP_CFG<2> at (D 6) is labeled only once in the design.
Signal   CPU_JP_CFG<3> at (B 6) is labeled only once in the design.
Signal   CPU_JP_CFG<6> at (A 6) is labeled only once in the design.
Signal   CPU_JP_CFG<5> at (B 6) is labeled only once in the design.
Signal  CPU__JP_CFG<7> at (D 2) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page36
Signal DDR3_CHB_VREF_OPFB at (A 5) is labeled only once in the design.
Signal DDR3_CHA_VREF_DCP_A at (D 3) is labeled only once in the design.
Signal DDR3_CHA_VREF_OPFB at (C 5) is labeled only once in the design.
Signal DDR3_CHB_VREF_DCP at (B 5) is labeled only once in the design.
Signal VREF_SMBDAT_D27 at (A 7) is labeled only once in the design.
Signal VREF_SMBCLK_C27 at (B 7) is labeled only once in the design.
Signal DDR3_CHB_VREF_DCP_B at (B 3) is labeled only once in the design.
Signal VREF_SMBDAT_D28 at (C 7) is labeled only once in the design.
Signal VREF_SMBCLK_C28 at (D 7) is labeled only once in the design.
Signal DDR3_CHA_VREF_DCP at (D 5) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page37
Signal  CPU_DDR_VREF_R at (D 3) is labeled only once in the design.
Signal P1V5_DDR3_VREF_DIV_B at (B 4) is labeled only once in the design.
Signal CPU_DDR3_VREF_OPFB at (C 5) is labeled only once in the design.
Signal    CPU_VREF_DCP at (C 3) is labeled only once in the design.
Signal CPU_DDR3_VREF_DCP at (C 5) is labeled only once in the design.
Signal P1V5_DDR3_VREF_DIV_A at (B 8) is labeled only once in the design.
Signal VREF_SMBCLK_C47 at (C 7) is labeled only once in the design.
Signal VREF_SMBDAT_D47 at (C 7) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page38
Signal    DDRA_0_SA<2> at (A 6) is labeled only once in the design.
Signal    DDRA_0_SA<1> at (A 6) is labeled only once in the design.
Signal    DDRA_0_SA<0> at (A 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page39
Signal    DDRA_1_SA<0> at (A 6) is labeled only once in the design.
Signal    DDRA_1_SA<1> at (A 6) is labeled only once in the design.
Signal    DDRA_1_SA<2> at (A 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page40
Signal    DDRB_0_SA<1> at (A 5) is labeled only once in the design.
Signal    DDRB_0_SA<0> at (A 5) is labeled only once in the design.
Signal    DDRB_0_SA<2> at (A 5) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page41
Signal      DDRB_1_<1> at (A 5) is labeled only once in the design.
Signal      DDRB_1_<2> at (B 5) is labeled only once in the design.
Signal      DDRB_1_<0> at (A 5) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page46
Signal RST_PCIE_EXP1_N at (D 3) is labeled only once in the design.
Signal  PCIE_2_PRSNT_N at (D 3) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page47
Signal CPU_EXP1_TX_DP_N_C<3..0> at (C 5) is labeled only once in the design.
Signal CPU_EXP1_TX_DP_P_C<3..0> at (D 5) is labeled only once in the design.
Signal RST_PCIE_EXP2_N at (C 3) is labeled only once in the design.
Signal  PCIE_1_PRSNT_N at (C 3) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page48
Signal RST_PCIE_EXP3_N at (C 3) is labeled only once in the design.
Signal  PCIE_3_PRSNT_N at (C 3) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page49
Signal  PCIE_4_PRSNT_N at (C 3) is labeled only once in the design.
Signal RST_PCIE_EXP4_N at (C 3) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page50
Signal RST_PCIE_EXP5_N at (C 3) is labeled only once in the design.
Signal  PCIE_5_PRSNT_N at (C 3) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page51
Signal  PCIE_6_PRSNT_N at (C 4) is labeled only once in the design.
Signal RST_PCIE_EXP6_N at (C 4) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page53
Signal  PCH_PEA_ICOMPI at (B 6) is labeled only once in the design.
Signal PCH_PEA_IREF_1P8 at (A 3) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page54
Signal DMI_CPU_PCH_RX_DP_N_C<3..0> at (B 5) is labeled only once in the design.
Signal DMI_CPU_PCH_RX_DP_P_C<3..0> at (B 5) is labeled only once in the design.
Signal PCH_EXP3_TX_DP_N_C<0> at (C 4) is labeled only once in the design.
Signal PCH_EXP6_TX_DP_P_C<3> at (D 4) is labeled only once in the design.
Signal PCH_EXP4_TX_DP_N_C<1> at (C 4) is labeled only once in the design.
Signal    PCH_DMI_VREF at (B 5) is labeled only once in the design.
Signal PCH_EXP6_TX_DP_N_C<3> at (C 4) is labeled only once in the design.
Signal PCH_EXP5_TX_DP_N_C<2> at (C 4) is labeled only once in the design.
Signal   PCH_DMI_COMPI at (A 8) is labeled only once in the design.
Signal PCH_EXP5_TX_DP_P_C<2> at (D 4) is labeled only once in the design.
Signal PCH_EXP4_TX_DP_P_C<1> at (D 4) is labeled only once in the design.
Signal PCH_EXP3_TX_DP_P_C<0> at (D 4) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page55
Signal PCH_GBE_RX_DP_P<3..0> at (D 6) is labeled only once in the design.
Signal PCH_GBE_RX_DP_N<3..0> at (D 6) is labeled only once in the design.
Signal GBE_AUX_PWR_OK_R at (C 6) is labeled only once in the design.
Signal    PCH_PE_RST_N at (B 6) is labeled only once in the design.
Signal  PCH_GBE_IRCOMP at (A 4) is labeled only once in the design.
Signal PCH_GBE_IREF_1P8 at (A 2) is labeled only once in the design.
Signal GBE_MAIN_PWR_OK_R at (C 6) is labeled only once in the design.
Signal   PCH_EP_CRU_EN at (B 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page56
Signal   PCH_USB_RBIAS at (C 3) is labeled only once in the design.
Signal PCH_SPI_CS0_N_R at (B 6) is labeled only once in the design.
Signal PCH_SATA_IREF_1P8 at (D 8) is labeled only once in the design.
Signal PCH_SATA_ICOMPO at (C 6) is labeled only once in the design.
Signal PCH_SPI_CS1_N_R at (B 6) is labeled only once in the design.
Signal   PCH_SPI_CLK_R at (B 6) is labeled only once in the design.
Signal  PCH_SPI_MOSI_R at (B 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page57
Signal PCH_PWROK_BUF1_PCH_R at (C 6) is labeled only once in the design.
Signal  PCH_THRMTRIP_N at (C 4) is labeled only once in the design.
Signal TP_PCH_RTCEXTPAD at (C 6) is labeled only once in the design.
Signal       PCH_RTCX2 at (C 6) is labeled only once in the design.
Signal       PCH_RTCX1 at (C 6) is labeled only once in the design.
Signal     PCH_MEPWROK at (D 6) is labeled only once in the design.
Signal    CLK_PCH_UART at (C 4) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page58
Signal   PLLBYPASS_CRU at (B 6) is labeled only once in the design.
Signal      TS1_IREF_N at (B 4) is labeled only once in the design.
Signal      TS0_IREF_N at (C 4) is labeled only once in the design.
Signal  OBSVCCA1P1_CRU at (B 6) is labeled only once in the design.
Signal    PCH1_JTAG_EN at (A 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page59
Signal      PCH_GP37_R at (B 6) is labeled only once in the design.
Signal        PCH_GP45 at (C 2) is labeled only once in the design.
Signal        PCH_GP26 at (B 6) is labeled only once in the design.
Signal      PCH_RSVD38 at (B 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page60
Signal VCC_CRU_1P0_PCH at (B 7) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page61
Signal   VCCA_1P8_STBY at (B 6) is labeled only once in the design.
Signal VCC_SUS_USB_3P3 at (B 2) is labeled only once in the design.
Signal   VCCA_1P8_FLT1 at (C 6) is labeled only once in the design.
Signal   VCCA_1P8_FLT2 at (C 6) is labeled only once in the design.
Signal      VCC1P8_TSX at (A 6) is labeled only once in the design.
Signal      VCC1P5_TSX at (A 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page65
Signal  GBE_LED3_STRAP at (A 2) is labeled only once in the design.
Signal  GBE_LED2_STRAP at (A 2) is labeled only once in the design.
Signal  GBE_LED0_STRAP at (A 2) is labeled only once in the design.
Signal GBE_SMB_LED_DLY at (A 7) is labeled only once in the design.
Signal  GBE_SMB_LED_EN at (A 4) is labeled only once in the design.
Signal  GBE_LED1_STRAP at (A 2) is labeled only once in the design.
Signal      PCH_GP33_R at (C 3) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page66
Signal        PROT_RTC at (B 6) is labeled only once in the design.
Signal PCH_CONFIG_JP_PU at (B 4) is labeled only once in the design.
Signal        CLR_CMOS at (A 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page67
Signal CPU_RESET_BUFF_N at (D 7) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page68
Signal  EEPROM_GBE_SCK at (C 6) is labeled only once in the design.
Signal      GB_SW_BE_N at (C 6) is labeled only once in the design.
Signal         EE_HD_N at (A 5) is labeled only once in the design.
Signal EEPROM_GBE_WP_N at (A 5) is labeled only once in the design.
Signal EEPROM_GBE_CS_N at (C 6) is labeled only once in the design.
Signal   EEPROM_GBE_DI at (C 6) is labeled only once in the design.
Signal PHY_CARD_DETECT_SW_BX at (B 5) is labeled only once in the design.
Signal   EEPROM_GBE_DO at (C 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page69
Signal  CONN_GBE_INT_N at (D 4) is labeled only once in the design.
Signal  CONN_MODULE_ID at (C 4) is labeled only once in the design.
Signal CONN_GBE_RESET_N at (C 4) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page70
Signal  CONN_GBE_GPIO2 at (C 6) is labeled only once in the design.
Signal  CONN_GBE_GPIO3 at (C 4) is labeled only once in the design.
Signal CONN_GBE_GPIO1_SUS at (C 4) is labeled only once in the design.
Signal CONN_GBE_GPIO0_SUS at (C 6) is labeled only once in the design.
Signal  CONN_GBE_GPIO4 at (B 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page71
Signal GBE_JTAG_TDO_HD at (A 4) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page72
Signal   USB0_REAR_PWR at (C 5) is labeled only once in the design.
Signal    USB0N_REAR_L at (C 3) is labeled only once in the design.
Signal    USB0P_REAR_L at (B 3) is labeled only once in the design.
Signal   USB3_REAR_PWR at (D 5) is labeled only once in the design.
Signal    USB3N_REAR_L at (D 3) is labeled only once in the design.
Signal    USB3P_REAR_L at (C 3) is labeled only once in the design.
Signal   USB1_REAR_PWR at (A 5) is labeled only once in the design.
Signal   USB2_REAR_PWR at (B 5) is labeled only once in the design.
Signal    USB2P_REAR_L at (B 3) is labeled only once in the design.
Signal    USB2N_REAR_L at (B 3) is labeled only once in the design.
Signal    USB1N_REAR_L at (A 3) is labeled only once in the design.
Signal    USB1P_REAR_L at (A 3) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page73
Signal  USB_P5_OC_N<3> at (C 5) is labeled only once in the design.
Signal  USB_P4_OC_N<2> at (C 5) is labeled only once in the design.
Signal   USB4N_FRONT_L at (B 3) is labeled only once in the design.
Signal  USB4_FRONT_PWR at (C 6) is labeled only once in the design.
Signal   USB5P_FRONT_L at (B 5) is labeled only once in the design.
Signal   USB5N_FRONT_L at (B 5) is labeled only once in the design.
Signal   USB4P_FRONT_L at (B 3) is labeled only once in the design.
Signal  USB5_FRONT_PWR at (C 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page74
Signal   SATA_C_RXN<0> at (C 6) is labeled only once in the design.
Signal   SATA_C_TXP<1> at (B 6) is labeled only once in the design.
Signal   SATA_C_TXN<1> at (B 6) is labeled only once in the design.
Signal   SATA_C_RXN<1> at (B 6) is labeled only once in the design.
Signal   SATA_C_RXP<1> at (B 6) is labeled only once in the design.
Signal   SATA_C_RXP<0> at (C 6) is labeled only once in the design.
Signal   SATA_C_TXN<0> at (C 6) is labeled only once in the design.
Signal   SATA_C_TXP<0> at (C 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page75
Signal SW_SRL_PORT_S1_S2 at (B 3) is labeled only once in the design.
Signal  SW_SRL_PORT_S0 at (B 3) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page77
Signal  SPI1_PROG_MISO at (B 3) is labeled only once in the design.
Signal  SPI1_PROG_WP_N at (B 4) is labeled only once in the design.
Signal  SPI0_PROG_MISO at (C 3) is labeled only once in the design.
Signal    SPI_SELECT_N at (A 6) is labeled only once in the design.
Signal SPI_PROG_HOLD_N at (B 4) is labeled only once in the design.
Signal   SPI_PROG_MOSI at (B 6) is labeled only once in the design.
Signal    SPI_PROG_CLK at (B 6) is labeled only once in the design.
Signal   SPI_PROG_MISO at (C 2) is labeled only once in the design.
Signal  SPI_PROG_CS1_N at (C 6) is labeled only once in the design.
Signal  SPI_PROG_CS0_N at (C 6) is labeled only once in the design.
Signal SPI_VCC3P3_PROG at (D 6) is labeled only once in the design.
Signal  SPI0_PROG_WP_N at (C 4) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page78
Signal ADT_TACH3_AUXFAN at (C 2) is labeled only once in the design.
Signal ADT_ADDRSELECT_N at (B 2) is labeled only once in the design.
Signal     THERM_GPIO1 at (C 4) is labeled only once in the design.
Signal     THERM_GPIO2 at (B 4) is labeled only once in the design.
Signal    ADT_ADDREN_N at (C 2) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page79
Signal ADT_TACH1_CPUFAN_P3 at (D 4) is labeled only once in the design.
Signal CPU_FAN_CTRL_P4 at (C 5) is labeled only once in the design.
Signal    TACH3_AUXFAN at (A 5) is labeled only once in the design.
Signal ADT_TACH2_PCHFAN_P3 at (B 5) is labeled only once in the design.
Signal ADT_PWM2_PCHFAN_R at (B 5) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page80
Signal      SIO_GPIO13 at (A 6) is labeled only once in the design.
Signal   CK_14M_SIO_R1 at (A 5) is labeled only once in the design.
Signal  PCH_SUSCLK_SIO at (A 6) is labeled only once in the design.
Signal    SIO_SLP_S4_N at (B 6) is labeled only once in the design.
Signal       SIO_SKC_N at (A 5) is labeled only once in the design.
Signal    SIO_SLP_S3_N at (B 6) is labeled only once in the design.
Signal         SIO_FNC at (C 6) is labeled only once in the design.
Signal PCH_SERIRQ_SIO_R at (B 7) is labeled only once in the design.
Signal          SIO_PE at (C 5) is labeled only once in the design.
Signal     SIO_LPCPD_N at (C 6) is labeled only once in the design.
Signal    SIO_PLTRST_N at (C 6) is labeled only once in the design.
Signal LPC_FRAME_SIO_N at (C 6) is labeled only once in the design.
Signal           VCORP at (D 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page82
Signal           V5_KB at (D 4) is labeled only once in the design.
Signal        V5_KB_RT at (D 5) is labeled only once in the design.
Signal      CON_KBDATA at (C 4) is labeled only once in the design.
Signal       CON_KBCLK at (C 4) is labeled only once in the design.
Signal      CON_MSDATA at (C 4) is labeled only once in the design.
Signal       CON_MSCLK at (C 4) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page83
Signal    FP_VCC_HDLED at (C 5) is labeled only once in the design.
Signal     FP_HD_LED_N at (C 6) is labeled only once in the design.
Signal    FP_LED_GRN_N at (C 4) is labeled only once in the design.
Signal    FP_LED_YLW_N at (C 4) is labeled only once in the design.
Signal          FP_PD2 at (C 4) is labeled only once in the design.
Signal   FP_LED_GRN_EN at (D 3) is labeled only once in the design.
Signal LED_Y_HDR_NPN_C at (A 5) is labeled only once in the design.
Signal LED_Y_HDR_DRV_NPN at (A 6) is labeled only once in the design.
Signal          FP_PD1 at (C 5) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page84
Signal         P80_TD0 at (A 7) is labeled only once in the design.
Signal         P80_TCK at (A 7) is labeled only once in the design.
Signal         P80_TDI at (A 7) is labeled only once in the design.
Signal         P80_TMS at (A 7) is labeled only once in the design.
Signal     PORT_OPTION at (C 4) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page86
Signal    EP_SMBCLK_SW at (A 3) is labeled only once in the design.
Signal    EP_SMBDAT_SW at (A 3) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page88
Signal        FRUID_A2 at (D 3) is labeled only once in the design.
Signal        FRUID_A1 at (D 3) is labeled only once in the design.
Signal        FRUID_WP at (D 4) is labeled only once in the design.
Signal        FRUID_A0 at (D 3) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page90
Signal 5STBY_CTRL_XSTR_P6 at (B 6) is labeled only once in the design.
Signal 5VSUS_CTRL_RSMRST_N at (C 3) is labeled only once in the design.
Signal     RSMRST_RC_N at (C 7) is labeled only once in the design.
Signal     RSMRST_N_P4 at (C 4) is labeled only once in the design.
Signal  RSMRST_SCHMITT at (C 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page91
Signal GBE_AUX_PWR_OK_N at (B 4) is labeled only once in the design.
Signal 1P0_1P05_AUX_PWRGD at (B 7) is labeled only once in the design.
Signal GBE_MAIN_PWR_OK_N at (A 3) is labeled only once in the design.
Signal GBE_MAIN_PWR_OK_DLY at (A 4) is labeled only once in the design.
Signal ATX_PWROK_3V3_BUF at (A 5) is labeled only once in the design.
Signal ATX_PWROK_3V3_BUF_R1 at (A 7) is labeled only once in the design.
Signal  AUX_PWR_OK_DLY at (B 5) is labeled only once in the design.
Signal AUX_PWR_OK_NGATE at (B 6) is labeled only once in the design.
Signal GBE_AUX_PWR_AVAIL_R at (D 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page92
Signal   EP_CRU_EN_DLY at (A 5) is labeled only once in the design.
Signal PCH_PWROK_BUF_EP at (A 6) is labeled only once in the design.
Signal  PWROK_3V_DELAY at (C 5) is labeled only once in the design.
Signal     PWROK_3V_P4 at (C 3) is labeled only once in the design.
Signal SLP_S3_PWROK_P6 at (B 5) is labeled only once in the design.
Signal SLP_S3_PWROK_P5 at (B 6) is labeled only once in the design.
Signal     EP_CRU_EN_N at (A 4) is labeled only once in the design.
Signal    ATX_PWROK_P5 at (C 7) is labeled only once in the design.
Signal     ATX_PWROK_N at (C 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page93
Signal     ALL_RST_BTN at (C 7) is labeled only once in the design.
Signal  VCCP_PWRGD_DLY at (A 6) is labeled only once in the design.
Signal VCCP_PWRGD_DLY_N at (A 5) is labeled only once in the design.
Signal       RST_BTN_N at (C 8) is labeled only once in the design.
Signal       PWR_BTN_N at (C 3) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page95
Signal    ATX_PS_ON_EN at (D 6) is labeled only once in the design.
Signal NORMAL_MAIN_OPR_SW_EN_R at (A 6) is labeled only once in the design.
Signal ATS_PS_ON_N_JMPR at (D 5) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page97
Signal    5VAUX_STBY_R at (A 5) is labeled only once in the design.
Signal   3V3AUX_STBY_R at (C 5) is labeled only once in the design.
Signal      5VAUX_STBY at (A 6) is labeled only once in the design.
Signal     3V3AUX_STBY at (C 6) is labeled only once in the design.
Signal      5VAUX_GATE at (A 4) is labeled only once in the design.
Signal     3V3AUX_GATE at (C 4) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page98
Signal      3P3STBY_FB at (B 6) is labeled only once in the design.
Signal     3P3STBY_V0S at (B 6) is labeled only once in the design.
Signal   3P3STBY_LGATE at (B 4) is labeled only once in the design.
Signal    3P3STBY_BOOT at (C 5) is labeled only once in the design.
Signal    3P3STBY_COMP at (C 7) is labeled only once in the design.
Signal 3P3STBY_COMP_RC at (B 7) is labeled only once in the design.
Signal   3P3STBY_FB_RC at (B 5) is labeled only once in the design.
Signal 3P3STBY_BOOT_RC at (C 4) is labeled only once in the design.
Signal   3P3STBY_PHASE at (C 5) is labeled only once in the design.
Signal   3P3STBY_UGATE at (C 5) is labeled only once in the design.
Signal   3P3STBY_PGOOD at (B 7) is labeled only once in the design.
Signal     3P3STBY_VCC at (C 7) is labeled only once in the design.
Signal VCC5_STBY_FILTER at (D 3) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page99
Signal  VCC1P0_STBY_FB at (A 5) is labeled only once in the design.
Signal  VCC1P8_STBY_FB at (C 5) is labeled only once in the design.
Signal  VCC1P8_STBY_EN at (C 6) is labeled only once in the design.
Signal VCC1P8_STBY_PWRGD at (D 5) is labeled only once in the design.
Signal VCC1P0_STBY_PWRGD at (B 4) is labeled only once in the design.
Signal  VCC1P0_STBY_EN at (A 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page100
Signal   VCC1P0_AUX_FB at (A 5) is labeled only once in the design.
Signal   VCC1P8_AUX_EN at (D 6) is labeled only once in the design.
Signal   VCC1P0_AUX_EN at (A 6) is labeled only once in the design.
Signal   VCC1P8_AUX_FB at (C 4) is labeled only once in the design.
Signal   VCC1P0_AUX_VR at (B 3) is labeled only once in the design.
Signal  VCC1P8_AUX_GND at (C 5) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page101
Signal   VCC1P8_CPU_FB at (C 5) is labeled only once in the design.
Signal   VCC1P8_PCH_FB at (A 5) is labeled only once in the design.
Signal   VCC1P8_CPU_EN at (C 6) is labeled only once in the design.
Signal   VCC1P8_PCH_EN at (A 6) is labeled only once in the design.
Signal VCC1P8_CPU_PWRGD at (D 4) is labeled only once in the design.
Signal VCC1P8_PCH_PWRGD at (B 4) is labeled only once in the design.
Signal   VCC1P8_CPU_VR at (D 4) is labeled only once in the design.
Signal   VCC1P8_PCH_VR at (B 4) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page102
Signal  VCC1P05_AUX_FB at (C 6) is labeled only once in the design.
Signal  VCC1P05_AUX_VR at (C 5) is labeled only once in the design.
Signal VCC1P05_FUSE_GATE at (B 3) is labeled only once in the design.
Signal VCC1P0_PCH_PWRGD_3V3 at (B 7) is labeled only once in the design.
Signal VCC1P05_FUSE_GATE_R at (B 5) is labeled only once in the design.
Signal  VCC1P05_AUX_EN at (C 7) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page104
Signal   VCC1P0_PCH_FB at (B 5) is labeled only once in the design.
Signal   VCC1P0_PCH_EN at (C 6) is labeled only once in the design.
Signal VCC1P0_PCH_SET0 at (B 6) is labeled only once in the design.
Signal VCC1P0_PCH_VID0 at (C 6) is labeled only once in the design.
Signal    VCC5_1P0_PCH at (C 6) is labeled only once in the design.
Signal VCC1P0_PCH_SREF at (C 6) is labeled only once in the design.
Signal   VCC1P0_PCH_VR at (C 2) is labeled only once in the design.
Signal VCC1P0_PCH_PHASE at (C 4) is labeled only once in the design.
Signal   VCC1P0_PCH_V0 at (B 4) is labeled only once in the design.
Signal VCC1P0_PCH_OCSET at (B 4) is labeled only once in the design.
Signal VCC1P0_PCH_FB_RC at (B 4) is labeled only once in the design.
Signal VCC1P0_PCH_LGATE at (C 4) is labeled only once in the design.
Signal VCC1P0_PCH_UGATE at (C 4) is labeled only once in the design.
Signal VCC1P0_PCH_BOOT_RC at (C 4) is labeled only once in the design.
Signal   VCC12_1P0_PCH at (D 3) is labeled only once in the design.
Signal VCC1P0_PCH_BOOT at (C 5) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page105
Signal   VTT_SA_CPU_FB at (B 4) is labeled only once in the design.
Signal   VTT_SA_CPU_EN at (C 6) is labeled only once in the design.
Signal     VCC5_VTT_SA at (C 6) is labeled only once in the design.
Signal   VTT_SA_CPU_VR at (C 2) is labeled only once in the design.
Signal VTT_SA_CPU_PHASE at (C 4) is labeled only once in the design.
Signal VTT_SA_CPU_OCSET at (B 3) is labeled only once in the design.
Signal   VTT_SA_CPU_VO at (B 4) is labeled only once in the design.
Signal    VTT_SA_FB_RC at (B 3) is labeled only once in the design.
Signal      SA_BOOT_RC at (C 4) is labeled only once in the design.
Signal     VTT_SA_BOOT at (C 4) is labeled only once in the design.
Signal    VCC12_VTT_SA at (D 3) is labeled only once in the design.
Signal VTT_SA_CPU_UGATE at (C 4) is labeled only once in the design.
Signal VTT_SA_CPU_LGATE at (C 4) is labeled only once in the design.
Signal VTT_SA_CPU_SREF at (C 7) is labeled only once in the design.
Signal VTT_SA_CPU_SET0 at (C 7) is labeled only once in the design.
Signal VTT_SA_CPU_VID0 at (C 7) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page106
Signal   VR_P5VAUX_DDR at (B 7) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page107
Signal  IMVP7_VID3_SEL at (A 6) is labeled only once in the design.
Signal PCH_GP25_VID5_EN at (C 7) is labeled only once in the design.
Signal PCH_GP25_VID3_EN at (A 7) is labeled only once in the design.
Signal  IMVP7_VID5_SEL at (C 6) is labeled only once in the design.
Signal  IMVP7_VID4_SEL at (B 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page108
Signal       VR_DDR_FB at (D 4) is labeled only once in the design.
Signal     VR_DDR_PVCC at (C 6) is labeled only once in the design.
Signal     VR_DDR_RSET at (C 6) is labeled only once in the design.
Signal ISENSE2_VR_DDR_P at (A 5) is labeled only once in the design.
Signal ISENSE1_VR_DDR_N at (A 5) is labeled only once in the design.
Signal ISENSE1_VR_DDR_P at (A 5) is labeled only once in the design.
Signal     VR_DDR_RGND at (A 5) is labeled only once in the design.
Signal       DDR_VR_EN at (B 6) is labeled only once in the design.
Signal   VR_DDR_VSENSE at (A 5) is labeled only once in the design.
Signal VR_DDR_VSENSE_R1 at (D 3) is labeled only once in the design.
Signal   VR_DDR_SCIR_2 at (A 2) is labeled only once in the design.
Signal   VR_DDR_SCIR_1 at (B 2) is labeled only once in the design.
Signal    VR_DDR_FB_RC at (D 3) is labeled only once in the design.
Signal    VR_DDR_BOOT1 at (C 4) is labeled only once in the design.
Signal VR_DDR_BOOT1_R1 at (C 3) is labeled only once in the design.
Signal VR_DDR_UGATE2_R1 at (B 3) is labeled only once in the design.
Signal VR_DDR_LGATE1_R1 at (B 3) is labeled only once in the design.
Signal VR_DDR_UGATE1_R1 at (C 3) is labeled only once in the design.
Signal     VR_DDR_COMP at (D 5) is labeled only once in the design.
Signal  VR_DDR_COMP_RC at (D 4) is labeled only once in the design.
Signal      DDR_VR_OUT at (B 5) is labeled only once in the design.
Signal       VR_DDR_FS at (B 7) is labeled only once in the design.
Signal ISENSE2_VR_DDR_N at (A 5) is labeled only once in the design.
Signal   VR_DDR_UGATE2 at (C 4) is labeled only once in the design.
Signal      VR_DDR_APA at (D 5) is labeled only once in the design.
Signal    VR_DDR_BOOT2 at (C 4) is labeled only once in the design.
Signal   VR_DDR_UGATE1 at (C 4) is labeled only once in the design.
Signal   VR_DDR_LGATE1 at (C 4) is labeled only once in the design.
Signal   VR_DDR_PHASE1 at (C 4) is labeled only once in the design.
Signal      VR_DDR_REF at (B 7) is labeled only once in the design.
Signal       VR_DDR_SS at (B 8) is labeled only once in the design.
Signal   VR_DDR_LGATE2 at (C 4) is labeled only once in the design.
Signal   VR_DDR_PHASE2 at (C 4) is labeled only once in the design.
Signal VR_DDR_BOOT2_R1 at (B 3) is labeled only once in the design.
Signal VR_DDR_LGATE2_R1 at (A 3) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page109
Signal  VTT_CPU_BST_UP at (D 5) is labeled only once in the design.
Signal   VTT_CPU_DL_LG at (C 4) is labeled only once in the design.
Signal VCC12_PS_VTT_CPU at (D 3) is labeled only once in the design.
Signal     VTT_CPU_SYN at (C 7) is labeled only once in the design.
Signal    VTT_CPU_COMP at (C 7) is labeled only once in the design.
Signal     VTT_CPU_VCC at (D 7) is labeled only once in the design.
Signal     VTT_CPU_SWN at (C 5) is labeled only once in the design.
Signal   VTT_CPU_DH_HG at (C 5) is labeled only once in the design.
Signal     VTT_CPU_VIN at (D 5) is labeled only once in the design.
Signal      VTT_CPU_DH at (C 5) is labeled only once in the design.
Signal      VTT_CPU_DL at (C 5) is labeled only once in the design.
Signal     VTT_CPU_CS+ at (C 5) is labeled only once in the design.
Signal      VTT_CPU_VR at (C 2) is labeled only once in the design.
Signal    VTT_CPU_VCCP at (D 7) is labeled only once in the design.
Signal      VTT_CPU_EN at (C 7) is labeled only once in the design.
Signal    VTT_CPU_IDRP at (C 7) is labeled only once in the design.
Signal VTT_CPU_VR_SENSE_R at (B 6) is labeled only once in the design.
Signal      VTT_CPU_FB at (C 7) is labeled only once in the design.
Signal VTT_CPU_COMP_RC at (B 8) is labeled only once in the design.
Signal   VTT_CPU_FB_RC at (B 7) is labeled only once in the design.
Signal     VTT_CPU_BST at (D 5) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page110
Signal         VCCP_FB at (A 5) is labeled only once in the design.
Signal       VCCP_IMON at (C 6) is labeled only once in the design.
Signal       VCCP_COMP at (A 6) is labeled only once in the design.
Signal      VCCP_BOOT2 at (C 4) is labeled only once in the design.
Signal      VCCP_BOOT1 at (C 4) is labeled only once in the design.
Signal      VCCP_PROG2 at (C 6) is labeled only once in the design.
Signal    VCCP_NTC_RT1 at (A 7) is labeled only once in the design.
Signal       VCCP_ISNG at (A 5) is labeled only once in the design.
Signal        CPU_NTCG at (B 5) is labeled only once in the design.
Signal    VCCP_VIN_12V at (C 6) is labeled only once in the design.
Signal     VCCP_VDD_5V at (D 6) is labeled only once in the design.
Signal      VCCP_PROG1 at (C 6) is labeled only once in the design.
Signal   VCCP_ISUMN_C1 at (B 4) is labeled only once in the design.
Signal         VCCP_VW at (B 6) is labeled only once in the design.
Signal        VCCP_NTC at (A 7) is labeled only once in the design.
Signal      VCCP_VR_EN at (C 6) is labeled only once in the design.
Signal VCCP_ISUMP_THRM1 at (B 2) is labeled only once in the design.
Signal      VCCP_FB_RC at (A 4) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page111
Signal VCC_CORE_CPU_VR1 at (B 3) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page112
Signal VCC_CORE_CPU_VR2 at (C 2) is labeled only once in the design.
Signal     VCCP_UGATE3 at (A 6) is labeled only once in the design.
Signal     VCCP_PHASE3 at (A 6) is labeled only once in the design.
Signal VCC_CORE_CPU_VR3 at (A 2) is labeled only once in the design.
Signal     VCCP_LGATE3 at (A 6) is labeled only once in the design.
Signal      VCCP_BOOT3 at (B 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page113
Signal VTT0P75_VDDQSNS at (C 5) is labeled only once in the design.
Signal    VTT0P75_S5_N at (B 5) is labeled only once in the design.
Signal      VTTREF_DDR at (C 3) is labeled only once in the design.
Signal    VTT0P75_S3_N at (B 5) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page115
Signal   PD_TPM_CLKRUN at (C 4) is labeled only once in the design.
Signal LPC_TPM_LPCPD_N at (C 7) is labeled only once in the design.
Signal SIO_LPC_DRQ_ANDG at (A 6) is labeled only once in the design.
Signal TPM_CONN_DRQ0_N_ANDG at (B 5) is labeled only once in the design.
Signal   TPM_DRQ0_N_AG at (B 6) is labeled only once in the design.
Signal    U1H2_PIN2_PU at (B 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page116
Signal    XDP0_SMB_DAT at (B 6) is labeled only once in the design.
Signal XDP0_PCH_PLTRST_N at (C 4) is labeled only once in the design.
Signal    XDP0_SMB_CLK at (B 6) is labeled only once in the design.
Signal XDP0_BP_PWRGD_RST_N at (C 6) is labeled only once in the design.
Signal PD_XDP0_PRESENT_N at (B 4) is labeled only once in the design.
Signal  XDP0_CPU_PWRGD at (C 6) is labeled only once in the design.
Signal PCH_SYS_PWROK_XPD0 at (B 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page117
Signal PCH1_XDP_TCK1_SW at (B 7) is labeled only once in the design.
Signal PD_XDP1_PRESENT_N at (B 4) is labeled only once in the design.
Signal XDP1_PCH_PLTRST_N at (C 4) is labeled only once in the design.
Signal XDP1_VCC1P05_P43 at (D 6) is labeled only once in the design.
Signal      XDP1_PWROK at (C 7) is labeled only once in the design.
Signal XDP1_BP_PWRGD_RST_N at (C 7) is labeled only once in the design.
Signal    XDP1_SMB_CLK at (C 6) is labeled only once in the design.
Signal    XDP1_SMB_DAT at (C 6) is labeled only once in the design.
Signal GBE_AUX_PWR_OK_XDP at (C 6) is labeled only once in the design.
Signal PCH0_XDP_TCK0_SW at (B 4) is labeled only once in the design.
Signal XDP1_VCC1P05_P44 at (D 4) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page119
Signal    CPU_PECI_SW1 at (A 5) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page121
Signal    SLP_S3_LED_N at (A 7) is labeled only once in the design.
Signal    SLP_S4_LED_N at (A 6) is labeled only once in the design.
Signal   SYS_PWROK_LED at (B 6) is labeled only once in the design.
Signal       PWROK_LED at (B 7) is labeled only once in the design.
Signal    SLP_S5_LED_N at (C 7) is labeled only once in the design.
Signal    RSMRST_LED_N at (C 6) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page122
Signal   PROCHOT_LED_N at (C 6) is labeled only once in the design.
Signal      WAKE_LED_N at (A 7) is labeled only once in the design.
Signal     PLTRST_ED_N at (C 7) is labeled only once in the design.

Warnings in Page : @stargo_lib.stargo(sch_1):Page123
Signal CPU_CATERR_LED_N at (C 1) is labeled only once in the design.
Signal CPU_RESET_LED_N at (C 3) is labeled only once in the design.
Signal    THRMTRIP_CLR at (A 4) is labeled only once in the design.
Signal PCH_RSMRST_THRMRST_N at (B 5) is labeled only once in the design.
Signal    THRMTRIP_CLK at (A 5) is labeled only once in the design.
Signal    THRMTRIP_LED at (A 3) is labeled only once in the design.
Signal CPU_THRMTRIP_TTL_STBY at (A 6) is labeled only once in the design.
