-- generated by newgenasym Tue Jan 05 18:45:36 2010

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \74cbt3383\ is
    port (    
	\1a1\:     INOUT  STD_LOGIC;    
	\1a2\:     INOUT  STD_LOGIC;    
	\1b1\:     INOUT  STD_LOGIC;    
	\1b2\:     INOUT  STD_LOGIC;    
	\2a1\:     INOUT  STD_LOGIC;    
	\2a2\:     INOUT  STD_LOGIC;    
	\2b1\:     INOUT  STD_LOGIC;    
	\2b2\:     INOUT  STD_LOGIC;    
	\3a1\:     INOUT  STD_LOGIC;    
	\3a2\:     INOUT  STD_LOGIC;    
	\3b1\:     INOUT  STD_LOGIC;    
	\3b2\:     INOUT  STD_LOGIC;    
	\4a1\:     INOUT  STD_LOGIC;    
	\4a2\:     INOUT  STD_LOGIC;    
	\4b1\:     INOUT  STD_LOGIC;    
	\4b2\:     INOUT  STD_LOGIC;    
	\5a1\:     INOUT  STD_LOGIC;    
	\5a2\:     INOUT  STD_LOGIC;    
	\5b1\:     INOUT  STD_LOGIC;    
	\5b2\:     INOUT  STD_LOGIC;    
	BE_N:      IN     STD_LOGIC;    
	BX:        IN     STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	VCC:       IN     STD_LOGIC);
end \74cbt3383\;
