-- generated by newgenasym Tue Oct 20 14:04:52 2009

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \74lvc125ad\ is
    generic (
        size:positive:= 1
            );
    port (    
	A:         IN     STD_LOGIC_VECTOR (size-1 DOWNTO 0);    
	OE_N:      IN     STD_LOGIC_VECTOR (size-1 DOWNTO 0);    
	Y:         OUT    STD_LOGIC_VECTOR (size-1 DOWNTO 0));
end \74lvc125ad\;
