-- generated by newgenasym Mon Feb 11 12:41:06 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity ISL6313 is
    port (    
	APA:       INOUT  STD_LOGIC;    
	BOOT1:     INOUT  STD_LOGIC;    
	BOOT2:     INOUT  STD_LOGIC;    
	COMP:      INOUT  STD_LOGIC;    
	DVC:       INOUT  STD_LOGIC;    
	EN:        IN     STD_LOGIC;    
	FB:        INOUT  STD_LOGIC;    
	FS:        INOUT  STD_LOGIC;    
	GND37_TH1: IN     STD_LOGIC;    
	IOUT:      INOUT  STD_LOGIC;    
	ISEN1_M:   INOUT  STD_LOGIC;    
	ISEN1_P:   INOUT  STD_LOGIC;    
	ISEN2_M:   INOUT  STD_LOGIC;    
	ISEN2_P:   INOUT  STD_LOGIC;    
	LGATE1:    INOUT  STD_LOGIC;    
	LGATE2:    INOUT  STD_LOGIC;    
	OFS:       INOUT  STD_LOGIC;    
	PGOOD:     OUT    STD_LOGIC;    
	PHASE1:    INOUT  STD_LOGIC;    
	PHASE2:    INOUT  STD_LOGIC;    
	PVCC:      IN     STD_LOGIC;    
	REF:       INOUT  STD_LOGIC;    
	RGND:      INOUT  STD_LOGIC;    
	RSET:      INOUT  STD_LOGIC;    
	SS:        INOUT  STD_LOGIC;    
	UGATE1:    INOUT  STD_LOGIC;    
	UGATE2:    INOUT  STD_LOGIC;    
	VCC:       IN     STD_LOGIC;    
	VID:       INOUT  STD_LOGIC_VECTOR (7 DOWNTO 0);    
	VSEN:      INOUT  STD_LOGIC);
end ISL6313;
