// generated by newgenasym  Tue Jul 21 09:35:58 2009


module wpcd376i (\5v_ddcscl_gpioe11 , \5v_ddcsda_gpioe10 , ack_n,
        afd_dstrb_n, bkfd_cut_n, busy_wait_n, cc_ddcscl_gpioe13,
        cc_ddcsda_gpioe12, cirled, clocki14, clocki32_gpio15,
        cpu_present_n, cts1_n, dcd1_n, densel, dir_n, dr0_n, drate0,
        dskchg_n_ejdct3_n, dsr1_n, dtr_n_bout1_xor_out_baddr_n,
        ejdct1_n, ejdct2_n, err_n_ejdct3_n, fnc, ga20, gpioe00,
        gpioe01, gpioe02, gpioe03, gpioe04, gpioe05, gpioe06,
        gpioe07, gpioe12_pcirst_out2_n, gpioe13, gpioe14, gpioe16,
        gpioe17, gpo11_vsbstrap1, gpo12_vddstrap1,
        gpo13_vddstrap2, grn_led, hd_led_n, hdsel_n, ide_rstdrv_n,
        index_n, irtx1, irtx2, irtx3_slin_astrb_n, irtx3_wgate_n,
        irtx4_init_n, irtx4_wdata_n, kbclk, kbdat, kbrst_n, lad0,
        lad1, lad2, lad3, latched_bf_cut, ldrq_n, lframe_n, mclk,
        mdat, mirrx, mtr0_n, nc_102, nc_123, pci_clk, pci_reset_n,
        pcirst_out_n, pd0, pd1, pd2, pd3, pd4, pd5, pd6, pd7,
        pe_ejdct4_n, primary_hd_n, ps_on_n, pwrgd_3v, pwrgd_ps,
        rdata_n_ejdct4_n, ref5v, ref5v_stby, ri1_n, rsmrst_n,
        rts1_n_tris_n, scsi_n, secondary_hd_n, ser_irq, sin1,
        siopme_n, slct, slp_s3_n, slp_s5_n, smb1_scl, smb1_sda,
        smb2_scl, smb2_sda, smi_n, sout1_test_n, srirrx,
        stb_write_n, step_n, trk0_n, vbat, vcorf, vdd3_31, vdd3_49,
        vdd3_6, vdd3_60, vsb3_107, vsb3_76, vsb3_93, vsb5, vss_110,
        vss_29, vss_46, vss_58, vss_78, vss_8, vss_96, wp_n, ylw_led);
    inout \5v_ddcscl_gpioe11 ;
    inout \5v_ddcsda_gpioe10 ;
    input ack_n;
    output afd_dstrb_n;
    output bkfd_cut_n;
    input busy_wait_n;
    inout cc_ddcscl_gpioe13;
    inout cc_ddcsda_gpioe12;
    inout cirled;
    input clocki14;
    inout clocki32_gpio15;
    input cpu_present_n;
    input cts1_n;
    input dcd1_n;
    output densel;
    output dir_n;
    output dr0_n;
    output drate0;
    input dskchg_n_ejdct3_n;
    input dsr1_n;
    inout dtr_n_bout1_xor_out_baddr_n;
    inout ejdct1_n;
    inout ejdct2_n;
    input err_n_ejdct3_n;
    inout fnc;
    inout ga20;
    inout gpioe00;
    inout gpioe01;
    inout gpioe02;
    inout gpioe03;
    inout gpioe04;
    inout gpioe05;
    inout gpioe06;
    inout gpioe07;
    inout gpioe12_pcirst_out2_n;
    inout gpioe13;
    inout gpioe14;
    inout gpioe16;
    inout gpioe17;
    inout gpo11_vsbstrap1;
    inout gpo12_vddstrap1;
    inout gpo13_vddstrap2;
    output grn_led;
    output hd_led_n;
    output hdsel_n;
    output ide_rstdrv_n;
    input index_n;
    inout irtx1;
    inout irtx2;
    output irtx3_slin_astrb_n;
    output irtx3_wgate_n;
    output irtx4_init_n;
    output irtx4_wdata_n;
    inout kbclk;
    inout kbdat;
    inout kbrst_n;
    inout lad0;
    inout lad1;
    inout lad2;
    inout lad3;
    output latched_bf_cut;
    output ldrq_n;
    input lframe_n;
    inout mclk;
    inout mdat;
    inout mirrx;
    output mtr0_n;
    inout nc_102;
    inout nc_123;
    input pci_clk;
    input pci_reset_n;
    output pcirst_out_n;
    inout pd0;
    inout pd1;
    inout pd2;
    inout pd3;
    inout pd4;
    inout pd5;
    inout pd6;
    inout pd7;
    input pe_ejdct4_n;
    input primary_hd_n;
    output ps_on_n;
    output pwrgd_3v;
    input pwrgd_ps;
    input rdata_n_ejdct4_n;
    inout ref5v;
    inout ref5v_stby;
    input ri1_n;
    output rsmrst_n;
    output rts1_n_tris_n;
    input scsi_n;
    input secondary_hd_n;
    inout ser_irq;
    input sin1;
    inout siopme_n;
    input slct;
    input slp_s3_n;
    input slp_s5_n;
    inout smb1_scl;
    inout smb1_sda;
    inout smb2_scl;
    inout smb2_sda;
    output smi_n;
    inout sout1_test_n;
    inout srirrx;
    output stb_write_n;
    output step_n;
    input trk0_n;
    input vbat;
    input vcorf;
    input vdd3_31;
    input vdd3_49;
    input vdd3_6;
    input vdd3_60;
    input vsb3_107;
    input vsb3_76;
    input vsb3_93;
    inout vsb5;
    input vss_110;
    input vss_29;
    input vss_46;
    input vss_58;
    input vss_78;
    input vss_8;
    input vss_96;
    input wp_n;
    output ylw_led;


    initial
        begin
        end

endmodule
