-- generated by newgenasym Thu May 22 15:46:56 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity CONN24_SSI is
    port (    
	\5vsb\:    INOUT  STD_LOGIC;    
	GND1:      INOUT  STD_LOGIC;    
	GND2:      INOUT  STD_LOGIC;    
	GND3:      INOUT  STD_LOGIC;    
	GND4:      INOUT  STD_LOGIC;    
	GND5:      INOUT  STD_LOGIC;    
	GND6:      INOUT  STD_LOGIC;    
	GND7:      INOUT  STD_LOGIC;    
	GND8:      INOUT  STD_LOGIC;    
	N12V_14:   INOUT  STD_LOGIC;    
	P12V2_10:  INOUT  STD_LOGIC;    
	P12V2_11:  INOUT  STD_LOGIC;    
	P3_3V_1:   INOUT  STD_LOGIC;    
	P3_3V_12:  INOUT  STD_LOGIC;    
	P3_3V_13:  INOUT  STD_LOGIC;    
	P3_3V_2:   INOUT  STD_LOGIC;    
	P5V_21:    INOUT  STD_LOGIC;    
	P5V_22:    INOUT  STD_LOGIC;    
	P5V_23:    INOUT  STD_LOGIC;    
	P5V_4:     INOUT  STD_LOGIC;    
	P5V_6:     INOUT  STD_LOGIC;    
	PS_ON:     INOUT  STD_LOGIC;    
	PWROK:     INOUT  STD_LOGIC;    
	RSVD:      INOUT  STD_LOGIC);
end CONN24_SSI;
