-- generated by newgenasym Wed Apr 19 09:36:15 2006

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \1x4hdr_shunt\ is
    port (    
	IO:        INOUT  STD_LOGIC_VECTOR (4 DOWNTO 1));
end \1x4hdr_shunt\;
