-- generated by newgenasym Thu Sep 20 08:06:19 2007

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity SI4511DY is
    port (    
	D1_7:      INOUT  STD_LOGIC;    
	D1_8:      INOUT  STD_LOGIC;    
	D2_5:      INOUT  STD_LOGIC;    
	D2_6:      INOUT  STD_LOGIC;    
	G1:        INOUT  STD_LOGIC;    
	G2:        INOUT  STD_LOGIC;    
	S1:        INOUT  STD_LOGIC;    
	S2:        INOUT  STD_LOGIC);
end SI4511DY;
