-- generated by newgenasym Tue Feb 29 15:43:17 2000

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \74ahc1g08\ is
    port (    
	A:         IN     STD_LOGIC;    
	B:         IN     STD_LOGIC;    
	Y:         OUT    STD_LOGIC);
end \74ahc1g08\;
