// generated by newgenasym  Wed May 02 18:47:25 2012


module \932sq420d  (\48m_2x_100m_133m_n , avdd14, avdd96, avdd_ns_sas,
        avdd_src, cpu0c, cpu0t, cpu1c, cpu1t, cpu2c, cpu2t, cpu3c,
        cpu3t, dot96c, dot96t, gnd14_1, gnd14_2, gnd48, gnd96,
        gndcpu, gndns_1, gndns_2, gndpci_1, gndpci_2, gndsrc_1,
        gndsrc_2, gndxtal, iref, ns_sas0c, ns_sas0t, ns_sas1c,
        ns_sas1t, ns_src0c, ns_src0t, ns_src1c, ns_src1t, pci0_2x,
        pci1_2x, pci2_2x, pci3_2x, pci4_2x, pd_ckpwrgd_n,
        ref14_3x_test_sel, smbclk, smbdat, src0c, src0t, src1c,
        src1t, src2c, src2t, test_mode, vdd14, vdd48, vddcpu1,
        vddcpu2, vddns, vddpci1, vddpci2, vddsrc1, vddsrc2, vddxtal,
        x1_25, x2_25);
    inout \48m_2x_100m_133m_n ;
    input avdd14;
    input avdd96;
    input avdd_ns_sas;
    input avdd_src;
    output cpu0c;
    output cpu0t;
    output cpu1c;
    output cpu1t;
    output cpu2c;
    output cpu2t;
    output cpu3c;
    output cpu3t;
    output dot96c;
    output dot96t;
    input gnd14_1;
    input gnd14_2;
    input gnd48;
    input gnd96;
    input gndcpu;
    input gndns_1;
    input gndns_2;
    input gndpci_1;
    input gndpci_2;
    input gndsrc_1;
    input gndsrc_2;
    input gndxtal;
    output iref;
    output ns_sas0c;
    output ns_sas0t;
    output ns_sas1c;
    output ns_sas1t;
    output ns_src0c;
    output ns_src0t;
    output ns_src1c;
    output ns_src1t;
    output pci0_2x;
    output pci1_2x;
    output pci2_2x;
    output pci3_2x;
    output pci4_2x;
    input pd_ckpwrgd_n;
    inout ref14_3x_test_sel;
    input smbclk;
    inout smbdat;
    output src0c;
    output src0t;
    output src1c;
    output src1t;
    output src2c;
    output src2t;
    input test_mode;
    input vdd14;
    input vdd48;
    input vddcpu1;
    input vddcpu2;
    input vddns;
    input vddpci1;
    input vddpci2;
    input vddsrc1;
    input vddsrc2;
    input vddxtal;
    input x1_25;
    output x2_25;


    initial
        begin
        end

endmodule
