-- generated by newgenasym Tue Aug 12 12:34:22 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity DSUB9X2_RA is
    port (    
	GND1:      INOUT  STD_LOGIC;    
	GND2:      INOUT  STD_LOGIC;    
	GND3:      INOUT  STD_LOGIC;    
	GND4:      INOUT  STD_LOGIC;    
	IO:        INOUT  STD_LOGIC_VECTOR (18 DOWNTO 1));
end DSUB9X2_RA;
