-- generated by newgenasym Fri Mar 30 10:36:14 2012

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity RESN is
    generic (
        size:positive:= 1
            );
    port (    
	A:         INOUT  STD_LOGIC_VECTOR (size-1 DOWNTO 0);    
	B:         INOUT  STD_LOGIC_VECTOR (size-1 DOWNTO 0));
end RESN;
