-- generated by newgenasym Mon Oct 13 18:21:21 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity ADT7490 is
    port (    
	\12vin\:   INOUT  STD_LOGIC;    
	\2v5in_therm_n\: INOUT  STD_LOGIC;    
	\5vin\:    INOUT  STD_LOGIC;    
	D1_M:      INOUT  STD_LOGIC;    
	D1_P:      INOUT  STD_LOGIC;    
	D2_M:      INOUT  STD_LOGIC;    
	D2_P:      INOUT  STD_LOGIC;    
	GND:       INOUT  STD_LOGIC;    
	GPIO1:     INOUT  STD_LOGIC;    
	GPIO2:     INOUT  STD_LOGIC;    
	IMON:      INOUT  STD_LOGIC;    
	PECI:      IN     STD_LOGIC;    
	PWM1_XTO:  OUT    STD_LOGIC;    
	PWM2_SMBALERT_N: OUT    STD_LOGIC;    
	PWM3_ADDREN_N: OUT    STD_LOGIC;    
	SCL:       IN     STD_LOGIC;    
	SDA:       INOUT  STD_LOGIC;    
	TACH1:     IN     STD_LOGIC;    
	TACH2:     IN     STD_LOGIC;    
	TACH3:     IN     STD_LOGIC;    
	TACH4_ADDRSELECT_N: INOUT  STD_LOGIC;    
	VCC:       IN     STD_LOGIC;    
	VCCP:      INOUT  STD_LOGIC;    
	VTT:       INOUT  STD_LOGIC);
end ADT7490;
