-- generated by newgenasym Wed Jan 05 11:50:30 2005

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \1x4hdr\ is
    generic (
        size:positive:= 1
            );
    port (    
	IO:        INOUT  STD_LOGIC_VECTOR (size DOWNTO 1));
end \1x4hdr\;
