-- generated by newgenasym Thu Aug 28 15:17:09 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity CM1230_02 is
    port (    
	CH1:       INOUT  STD_LOGIC;    
	CH2:       INOUT  STD_LOGIC;    
	VN:        IN     STD_LOGIC;    
	VP:        IN     STD_LOGIC);
end CM1230_02;
