-- generated by newgenasym Tue Mar 29 10:22:53 2005

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity CAP_P is
    generic (
        size:positive:= 1
            );
    port (    
	A:         INOUT  STD_LOGIC_VECTOR (size-1 DOWNTO 0);    
	B:         INOUT  STD_LOGIC_VECTOR (size-1 DOWNTO 0));
end CAP_P;
