-- generated by newgenasym Tue Jul 14 15:58:18 2009

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity AD5247 is
    port (    
	A:         INOUT  STD_LOGIC;    
	GND:       INOUT  STD_LOGIC;    
	SCL:       IN     STD_LOGIC;    
	SDA:       INOUT  STD_LOGIC;    
	VDD:       IN     STD_LOGIC;    
	W:         INOUT  STD_LOGIC);
end AD5247;
