-- generated by newgenasym Wed Mar 11 10:32:14 2009

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \74cbt3125\ is
    generic (
        size:positive:= 1
            );
    port (    
	A:         OUT    STD_LOGIC_VECTOR (size-1 DOWNTO 0);    
	B:         OUT    STD_LOGIC_VECTOR (size-1 DOWNTO 0);    
	GND:       IN     STD_LOGIC;    
	OE_N:      IN     STD_LOGIC_VECTOR (size-1 DOWNTO 0);    
	VCC:       IN     STD_LOGIC);
end \74cbt3125\;
