-- generated by newgenasym Tue Feb 16 13:27:01 2010

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \74lvc1g74\ is
    port (    
	\-q\:      OUT    STD_LOGIC;    
	\-rd\:     IN     STD_LOGIC;    
	\-sd\:     IN     STD_LOGIC;    
	CP:        IN     STD_LOGIC;    
	D:         IN     STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	Q:         OUT    STD_LOGIC;    
	VCC:       IN     STD_LOGIC);
end \74lvc1g74\;
