-- generated by newgenasym Wed Jan 05 12:10:09 2005

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \2x5hdr10\ is
    port (    
	IO1:       INOUT  STD_LOGIC;    
	IO2:       INOUT  STD_LOGIC;    
	IO3:       INOUT  STD_LOGIC;    
	IO4:       INOUT  STD_LOGIC;    
	IO5:       INOUT  STD_LOGIC;    
	IO6:       INOUT  STD_LOGIC;    
	IO7:       INOUT  STD_LOGIC;    
	IO8:       INOUT  STD_LOGIC;    
	IO9:       INOUT  STD_LOGIC);
end \2x5hdr10\;
