-- generated by newgenasym Tue Feb 13 16:29:15 2007

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \74cbt16209a\ is
    port (    
	\1a1\:     INOUT  STD_LOGIC;    
	\1a2\:     INOUT  STD_LOGIC;    
	\1b1\:     INOUT  STD_LOGIC;    
	\1b2\:     INOUT  STD_LOGIC;    
	\2a1\:     INOUT  STD_LOGIC;    
	\2a2\:     INOUT  STD_LOGIC;    
	\2b1\:     INOUT  STD_LOGIC;    
	\2b2\:     INOUT  STD_LOGIC;    
	\3a1\:     INOUT  STD_LOGIC;    
	\3a2\:     INOUT  STD_LOGIC;    
	\3b1\:     INOUT  STD_LOGIC;    
	\3b2\:     INOUT  STD_LOGIC;    
	\4a1\:     INOUT  STD_LOGIC;    
	\4a2\:     INOUT  STD_LOGIC;    
	\4b1\:     INOUT  STD_LOGIC;    
	\4b2\:     INOUT  STD_LOGIC;    
	\5a1\:     INOUT  STD_LOGIC;    
	\5a2\:     INOUT  STD_LOGIC;    
	\5b1\:     INOUT  STD_LOGIC;    
	\5b2\:     INOUT  STD_LOGIC;    
	\6a1\:     INOUT  STD_LOGIC;    
	\6a2\:     INOUT  STD_LOGIC;    
	\6b1\:     INOUT  STD_LOGIC;    
	\6b2\:     INOUT  STD_LOGIC;    
	\7a1\:     INOUT  STD_LOGIC;    
	\7a2\:     INOUT  STD_LOGIC;    
	\7b1\:     INOUT  STD_LOGIC;    
	\7b2\:     INOUT  STD_LOGIC;    
	\8a1\:     INOUT  STD_LOGIC;    
	\8a2\:     INOUT  STD_LOGIC;    
	\8b1\:     INOUT  STD_LOGIC;    
	\8b2\:     INOUT  STD_LOGIC;    
	\9a1\:     INOUT  STD_LOGIC;    
	\9a2\:     INOUT  STD_LOGIC;    
	\9b1\:     INOUT  STD_LOGIC;    
	\9b2\:     INOUT  STD_LOGIC;    
	GND_10:    IN     STD_LOGIC;    
	GND_15:    IN     STD_LOGIC;    
	GND_20:    IN     STD_LOGIC;    
	GND_29:    IN     STD_LOGIC;    
	GND_34:    IN     STD_LOGIC;    
	GND_39:    IN     STD_LOGIC;    
	GND_4:     IN     STD_LOGIC;    
	GND_42:    IN     STD_LOGIC;    
	S0:        IN     STD_LOGIC;    
	S1:        IN     STD_LOGIC;    
	S2:        IN     STD_LOGIC;    
	VCC:       IN     STD_LOGIC);
end \74cbt16209a\;
