-- generated by newgenasym Mon Sep 11 10:46:08 2000

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity FET is
    port (    
	B:         INOUT  STD_LOGIC;    
	C:         INOUT  STD_LOGIC;    
	E:         INOUT  STD_LOGIC);
end FET;
