-- generated by newgenasym Fri Sep 28 15:25:10 2007

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity QS3VH125 is
    port (    
	\1a\:      INOUT  STD_LOGIC;    
	\1oe_n\:   IN     STD_LOGIC;    
	\1y\:      INOUT  STD_LOGIC;    
	\2a\:      INOUT  STD_LOGIC;    
	\2oe_n\:   IN     STD_LOGIC;    
	\2y\:      INOUT  STD_LOGIC;    
	\3a\:      INOUT  STD_LOGIC;    
	\3oe_n\:   IN     STD_LOGIC;    
	\3y\:      INOUT  STD_LOGIC;    
	\4a\:      INOUT  STD_LOGIC;    
	\4oe_n\:   IN     STD_LOGIC;    
	\4y\:      INOUT  STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	NC_1:      INOUT  STD_LOGIC;    
	NC_9:      INOUT  STD_LOGIC;    
	VCC:       IN     STD_LOGIC);
end QS3VH125;
