-- generated by newgenasym Tue Feb 08 19:47:40 2005

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity CONN_SATA is
    port (    
	\a+\:      INOUT  STD_LOGIC;    
	\a-\:      INOUT  STD_LOGIC;    
	\b+\:      INOUT  STD_LOGIC;    
	\b-\:      INOUT  STD_LOGIC;    
	GND:       INOUT  STD_LOGIC_VECTOR (3 DOWNTO 1));
end CONN_SATA;
