-- generated by newgenasym Sun Jan 02 21:34:58 2005

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity RPAK4C_4R is
    generic (
        size:positive:= 1
            );
    port (    
	A:         INOUT  STD_LOGIC_VECTOR (size-1 DOWNTO 0);    
	B:         INOUT  STD_LOGIC_VECTOR (size-1 DOWNTO 0));
end RPAK4C_4R;
