-- generated by newgenasym Fri Aug 14 14:27:16 2009

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity HDR_HMZD_40PR_120P_VT is
    port (    
	A1:        INOUT  STD_LOGIC;    
	A10:       INOUT  STD_LOGIC;    
	A2:        INOUT  STD_LOGIC;    
	A3:        INOUT  STD_LOGIC;    
	A4:        INOUT  STD_LOGIC;    
	A5:        INOUT  STD_LOGIC;    
	A6:        INOUT  STD_LOGIC;    
	A7:        INOUT  STD_LOGIC;    
	A8:        INOUT  STD_LOGIC;    
	A9:        INOUT  STD_LOGIC;    
	B1:        INOUT  STD_LOGIC;    
	B10:       INOUT  STD_LOGIC;    
	B2:        INOUT  STD_LOGIC;    
	B3:        INOUT  STD_LOGIC;    
	B4:        INOUT  STD_LOGIC;    
	B5:        INOUT  STD_LOGIC;    
	B6:        INOUT  STD_LOGIC;    
	B7:        INOUT  STD_LOGIC;    
	B8:        INOUT  STD_LOGIC;    
	B9:        INOUT  STD_LOGIC;    
	BG1:       INOUT  STD_LOGIC;    
	BG10:      INOUT  STD_LOGIC;    
	BG2:       INOUT  STD_LOGIC;    
	BG3:       INOUT  STD_LOGIC;    
	BG4:       INOUT  STD_LOGIC;    
	BG5:       INOUT  STD_LOGIC;    
	BG6:       INOUT  STD_LOGIC;    
	BG7:       INOUT  STD_LOGIC;    
	BG8:       INOUT  STD_LOGIC;    
	BG9:       INOUT  STD_LOGIC;    
	C1:        INOUT  STD_LOGIC;    
	C10:       INOUT  STD_LOGIC;    
	C2:        INOUT  STD_LOGIC;    
	C3:        INOUT  STD_LOGIC;    
	C4:        INOUT  STD_LOGIC;    
	C5:        INOUT  STD_LOGIC;    
	C6:        INOUT  STD_LOGIC;    
	C7:        INOUT  STD_LOGIC;    
	C8:        INOUT  STD_LOGIC;    
	C9:        INOUT  STD_LOGIC;    
	D1:        INOUT  STD_LOGIC;    
	D10:       INOUT  STD_LOGIC;    
	D2:        INOUT  STD_LOGIC;    
	D3:        INOUT  STD_LOGIC;    
	D4:        INOUT  STD_LOGIC;    
	D5:        INOUT  STD_LOGIC;    
	D6:        INOUT  STD_LOGIC;    
	D7:        INOUT  STD_LOGIC;    
	D8:        INOUT  STD_LOGIC;    
	D9:        INOUT  STD_LOGIC;    
	DG1:       INOUT  STD_LOGIC;    
	DG10:      INOUT  STD_LOGIC;    
	DG2:       INOUT  STD_LOGIC;    
	DG3:       INOUT  STD_LOGIC;    
	DG4:       INOUT  STD_LOGIC;    
	DG5:       INOUT  STD_LOGIC;    
	DG6:       INOUT  STD_LOGIC;    
	DG7:       INOUT  STD_LOGIC;    
	DG8:       INOUT  STD_LOGIC;    
	DG9:       INOUT  STD_LOGIC;    
	E1:        INOUT  STD_LOGIC;    
	E10:       INOUT  STD_LOGIC;    
	E2:        INOUT  STD_LOGIC;    
	E3:        INOUT  STD_LOGIC;    
	E4:        INOUT  STD_LOGIC;    
	E5:        INOUT  STD_LOGIC;    
	E6:        INOUT  STD_LOGIC;    
	E7:        INOUT  STD_LOGIC;    
	E8:        INOUT  STD_LOGIC;    
	E9:        INOUT  STD_LOGIC;    
	F1:        INOUT  STD_LOGIC;    
	F10:       INOUT  STD_LOGIC;    
	F2:        INOUT  STD_LOGIC;    
	F3:        INOUT  STD_LOGIC;    
	F4:        INOUT  STD_LOGIC;    
	F5:        INOUT  STD_LOGIC;    
	F6:        INOUT  STD_LOGIC;    
	F7:        INOUT  STD_LOGIC;    
	F8:        INOUT  STD_LOGIC;    
	F9:        INOUT  STD_LOGIC;    
	FG1:       INOUT  STD_LOGIC;    
	FG10:      INOUT  STD_LOGIC;    
	FG2:       INOUT  STD_LOGIC;    
	FG3:       INOUT  STD_LOGIC;    
	FG4:       INOUT  STD_LOGIC;    
	FG5:       INOUT  STD_LOGIC;    
	FG6:       INOUT  STD_LOGIC;    
	FG7:       INOUT  STD_LOGIC;    
	FG8:       INOUT  STD_LOGIC;    
	FG9:       INOUT  STD_LOGIC;    
	G1:        INOUT  STD_LOGIC;    
	G10:       INOUT  STD_LOGIC;    
	G2:        INOUT  STD_LOGIC;    
	G3:        INOUT  STD_LOGIC;    
	G4:        INOUT  STD_LOGIC;    
	G5:        INOUT  STD_LOGIC;    
	G6:        INOUT  STD_LOGIC;    
	G7:        INOUT  STD_LOGIC;    
	G8:        INOUT  STD_LOGIC;    
	G9:        INOUT  STD_LOGIC;    
	H1:        INOUT  STD_LOGIC;    
	H10:       INOUT  STD_LOGIC;    
	H2:        INOUT  STD_LOGIC;    
	H3:        INOUT  STD_LOGIC;    
	H4:        INOUT  STD_LOGIC;    
	H5:        INOUT  STD_LOGIC;    
	H6:        INOUT  STD_LOGIC;    
	H7:        INOUT  STD_LOGIC;    
	H8:        INOUT  STD_LOGIC;    
	H9:        INOUT  STD_LOGIC;    
	HG1:       INOUT  STD_LOGIC;    
	HG10:      INOUT  STD_LOGIC;    
	HG2:       INOUT  STD_LOGIC;    
	HG3:       INOUT  STD_LOGIC;    
	HG4:       INOUT  STD_LOGIC;    
	HG5:       INOUT  STD_LOGIC;    
	HG6:       INOUT  STD_LOGIC;    
	HG7:       INOUT  STD_LOGIC;    
	HG8:       INOUT  STD_LOGIC;    
	HG9:       INOUT  STD_LOGIC);
end HDR_HMZD_40PR_120P_VT;
