-- generated by newgenasym Mon Aug 17 17:52:48 2009

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \74lvc1g14\ is
    port (    
	A:         IN     STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	NC:        INOUT  STD_LOGIC;    
	VCC:       IN     STD_LOGIC;    
	Y_N:       OUT    STD_LOGIC);
end \74lvc1g14\;
