-- generated by newgenasym Tue Oct 09 11:34:10 2007

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \74lvc1g07\ is
    port (    
	A:         IN     STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	NC:        INOUT  STD_LOGIC;    
	VCC:       IN     STD_LOGIC;    
	Y:         OUT    STD_LOGIC);
end \74lvc1g07\;
