-- generated by newgenasym Tue Oct 23 14:52:54 2007

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \74lvc2g125\ is
    port (    
	A:         IN     STD_LOGIC_VECTOR (0 DOWNTO 0);    
	GND:       IN     STD_LOGIC;    
	OE_N:      IN     STD_LOGIC_VECTOR (0 DOWNTO 0);    
	VCC:       IN     STD_LOGIC;    
	Y:         OUT    STD_LOGIC_VECTOR (0 DOWNTO 0));
end \74lvc2g125\;
