-- generated by newgenasym Tue Sep 18 12:53:39 2007

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity CONN240_DDR3_DIMM is
    port (    
	A:         INOUT  STD_LOGIC_VECTOR (15 DOWNTO 0);    
	A16_BA2:   INOUT  STD_LOGIC;    
	BA:        INOUT  STD_LOGIC_VECTOR (1 DOWNTO 0);    
	CAS_N:     INOUT  STD_LOGIC;    
	CB:        INOUT  STD_LOGIC_VECTOR (7 DOWNTO 0);    
	CK0N:      INOUT  STD_LOGIC;    
	CK0P:      INOUT  STD_LOGIC;    
	CKE:       INOUT  STD_LOGIC_VECTOR (1 DOWNTO 0);    
	CS:        INOUT  STD_LOGIC_VECTOR (3 DOWNTO 0);    
	DQ:        INOUT  STD_LOGIC_VECTOR (63 DOWNTO 0);    
	DQS0N:     INOUT  STD_LOGIC;    
	DQS0P:     INOUT  STD_LOGIC;    
	DQS10N_NC: INOUT  STD_LOGIC;    
	DQS10P_DM1: INOUT  STD_LOGIC;    
	DQS11N_NC: INOUT  STD_LOGIC;    
	DQS11P_DM2: INOUT  STD_LOGIC;    
	DQS12N_NC: INOUT  STD_LOGIC;    
	DQS12P_DM3: INOUT  STD_LOGIC;    
	DQS13N_NC: INOUT  STD_LOGIC;    
	DQS13P_DM4: INOUT  STD_LOGIC;    
	DQS14N_NC: INOUT  STD_LOGIC;    
	DQS14P_DM5: INOUT  STD_LOGIC;    
	DQS15N_NC: INOUT  STD_LOGIC;    
	DQS15P_DM6: INOUT  STD_LOGIC;    
	DQS16N_NC: INOUT  STD_LOGIC;    
	DQS16P_DM7: INOUT  STD_LOGIC;    
	DQS17N_NC: INOUT  STD_LOGIC;    
	DQS17P_DM8: INOUT  STD_LOGIC;    
	DQS1N:     INOUT  STD_LOGIC;    
	DQS1P:     INOUT  STD_LOGIC;    
	DQS2N:     INOUT  STD_LOGIC;    
	DQS2P:     INOUT  STD_LOGIC;    
	DQS3N:     INOUT  STD_LOGIC;    
	DQS3P:     INOUT  STD_LOGIC;    
	DQS4N:     INOUT  STD_LOGIC;    
	DQS4P:     INOUT  STD_LOGIC;    
	DQS5N:     INOUT  STD_LOGIC;    
	DQS5P:     INOUT  STD_LOGIC;    
	DQS6N:     INOUT  STD_LOGIC;    
	DQS6P:     INOUT  STD_LOGIC;    
	DQS7N:     INOUT  STD_LOGIC;    
	DQS7P:     INOUT  STD_LOGIC;    
	DQS8N:     INOUT  STD_LOGIC;    
	DQS8P:     INOUT  STD_LOGIC;    
	DQS9N_NC:  INOUT  STD_LOGIC;    
	DQS9P_DM0: INOUT  STD_LOGIC;    
	ERR_OUT_NC: INOUT  STD_LOGIC;    
	EVENT_N_NC: INOUT  STD_LOGIC;    
	NC_CK1N:   INOUT  STD_LOGIC;    
	NC_CK1P:   INOUT  STD_LOGIC;    
	NC_TEST:   INOUT  STD_LOGIC;    
	ODT:       INOUT  STD_LOGIC_VECTOR (1 DOWNTO 0);    
	PAR_IN_NC: INOUT  STD_LOGIC;    
	RAS_N:     INOUT  STD_LOGIC;    
	RESET_N:   INOUT  STD_LOGIC;    
	SA:        INOUT  STD_LOGIC_VECTOR (2 DOWNTO 0);    
	SCL:       INOUT  STD_LOGIC;    
	SDA:       INOUT  STD_LOGIC;    
	VDD_170:   INOUT  STD_LOGIC;    
	VDD_173:   INOUT  STD_LOGIC;    
	VDD_176:   INOUT  STD_LOGIC;    
	VDD_179:   INOUT  STD_LOGIC;    
	VDD_182:   INOUT  STD_LOGIC;    
	VDD_183:   INOUT  STD_LOGIC;    
	VDD_186:   INOUT  STD_LOGIC;    
	VDD_189:   INOUT  STD_LOGIC;    
	VDD_191:   INOUT  STD_LOGIC;    
	VDD_194:   INOUT  STD_LOGIC;    
	VDD_197:   INOUT  STD_LOGIC;    
	VDD_51:    INOUT  STD_LOGIC;    
	VDD_54:    INOUT  STD_LOGIC;    
	VDD_57:    INOUT  STD_LOGIC;    
	VDD_60:    INOUT  STD_LOGIC;    
	VDD_62:    INOUT  STD_LOGIC;    
	VDD_65:    INOUT  STD_LOGIC;    
	VDD_66:    INOUT  STD_LOGIC;    
	VDD_69:    INOUT  STD_LOGIC;    
	VDD_72:    INOUT  STD_LOGIC;    
	VDD_75:    INOUT  STD_LOGIC;    
	VDD_78:    INOUT  STD_LOGIC;    
	VDDSPD:    INOUT  STD_LOGIC;    
	VREFCA:    INOUT  STD_LOGIC;    
	VREFDQ:    INOUT  STD_LOGIC;    
	VSS_101:   INOUT  STD_LOGIC;    
	VSS_104:   INOUT  STD_LOGIC;    
	VSS_107:   INOUT  STD_LOGIC;    
	VSS_11:    INOUT  STD_LOGIC;    
	VSS_110:   INOUT  STD_LOGIC;    
	VSS_113:   INOUT  STD_LOGIC;    
	VSS_116:   INOUT  STD_LOGIC;    
	VSS_121:   INOUT  STD_LOGIC;    
	VSS_124:   INOUT  STD_LOGIC;    
	VSS_127:   INOUT  STD_LOGIC;    
	VSS_130:   INOUT  STD_LOGIC;    
	VSS_133:   INOUT  STD_LOGIC;    
	VSS_136:   INOUT  STD_LOGIC;    
	VSS_139:   INOUT  STD_LOGIC;    
	VSS_14:    INOUT  STD_LOGIC;    
	VSS_142:   INOUT  STD_LOGIC;    
	VSS_145:   INOUT  STD_LOGIC;    
	VSS_148:   INOUT  STD_LOGIC;    
	VSS_151:   INOUT  STD_LOGIC;    
	VSS_154:   INOUT  STD_LOGIC;    
	VSS_157:   INOUT  STD_LOGIC;    
	VSS_160:   INOUT  STD_LOGIC;    
	VSS_163:   INOUT  STD_LOGIC;    
	VSS_166:   INOUT  STD_LOGIC;    
	VSS_17:    INOUT  STD_LOGIC;    
	VSS_199:   INOUT  STD_LOGIC;    
	VSS_2:     INOUT  STD_LOGIC;    
	VSS_20:    INOUT  STD_LOGIC;    
	VSS_202:   INOUT  STD_LOGIC;    
	VSS_205:   INOUT  STD_LOGIC;    
	VSS_208:   INOUT  STD_LOGIC;    
	VSS_211:   INOUT  STD_LOGIC;    
	VSS_214:   INOUT  STD_LOGIC;    
	VSS_217:   INOUT  STD_LOGIC;    
	VSS_220:   INOUT  STD_LOGIC;    
	VSS_223:   INOUT  STD_LOGIC;    
	VSS_226:   INOUT  STD_LOGIC;    
	VSS_229:   INOUT  STD_LOGIC;    
	VSS_23:    INOUT  STD_LOGIC;    
	VSS_232:   INOUT  STD_LOGIC;    
	VSS_235:   INOUT  STD_LOGIC;    
	VSS_239:   INOUT  STD_LOGIC;    
	VSS_26:    INOUT  STD_LOGIC;    
	VSS_29:    INOUT  STD_LOGIC;    
	VSS_32:    INOUT  STD_LOGIC;    
	VSS_35:    INOUT  STD_LOGIC;    
	VSS_38:    INOUT  STD_LOGIC;    
	VSS_41:    INOUT  STD_LOGIC;    
	VSS_44:    INOUT  STD_LOGIC;    
	VSS_47:    INOUT  STD_LOGIC;    
	VSS_5:     INOUT  STD_LOGIC;    
	VSS_8:     INOUT  STD_LOGIC;    
	VSS_80:    INOUT  STD_LOGIC;    
	VSS_83:    INOUT  STD_LOGIC;    
	VSS_86:    INOUT  STD_LOGIC;    
	VSS_89:    INOUT  STD_LOGIC;    
	VSS_92:    INOUT  STD_LOGIC;    
	VSS_95:    INOUT  STD_LOGIC;    
	VSS_98:    INOUT  STD_LOGIC;    
	VTT_120:   INOUT  STD_LOGIC;    
	VTT_240:   INOUT  STD_LOGIC;    
	VTT_48:    INOUT  STD_LOGIC;    
	VTT_49:    INOUT  STD_LOGIC;    
	WE_N:      INOUT  STD_LOGIC);
end CONN240_DDR3_DIMM;
