
// generated by NetAssembler Version 16.3-p002 (v16-3-85A) 10/19/2009 
// on Thu Jul 11 16:16:48 2013


`timescale 1ns/1ns

`define scale_fs	* 0.000001000000000
`define scale_ps	* 0.001000000000000
`define scale_ns	* 1.000000000000000
`define scale_us	* 1000.000000000000000
`define scale_ms	* 1000000.000000000000000
`define scale_sec	* 1000000000.000000000000000
`define scale_min	* 60000000000.000000000000000
`define scale_hr	* 3600000000000.000000000000000



module alias_vector (a, a);
 parameter size = 1;
 inout [size-1:0] a;
endmodule

module alias_bit (a, a);
 inout a;
endmodule


module glbl ();
// Verilog global signals module 
  wire agnd_1p0;
  wire agnd_sa;
  wire agnd_vtt;
  wire bp_gnd;
`ifdef VAN
	wire gnd;
`else
	supply0 gnd;
`endif
  wire vcc12n_ps;
  wire vcc12_flt_ddr3;
  wire vcc12_flt_vccp_cpu;
  wire vcc12_ps;
  wire vcc12_ps_cpu;
  wire vcc12_ps_ddr;
  wire vcc12_vcc5_aux;
  wire vcc1p05_aux;
  wire vcc1p05_fuse;
  wire vcc1p0_aux;
  wire vcc1p0_pch;
  wire vcc1p0_stby;
  wire vcc1p0_stby_vr;
  wire vcc1p5_pch;
  wire vcc1p8_aux;
  wire vcc1p8_aux_vr;
  wire vcc1p8_cpu;
  wire vcc1p8_pch;
  wire vcc1p8_stby;
  wire vcc1p8_stby_vr;
  wire vcc3p3_aux;
  wire vcc3p3_ps;
  wire vcc3p3_rtc;
  wire vcc3p3_stby;
  wire vcc5_aux;
  wire vcc5_flt_ddr3;
  wire vcc5_ps;
  wire vcc5_ps_stby;
  wire vcc5_sw;
  wire vccdmi_pch;
  wire vcc_core_cpu;
  wire vdd1p5_ddr;
  wire vtt0p75_ddr;
  wire vtt_cpu;
  wire vtt_sa_cpu;
endmodule
