-- generated by newgenasym Fri Jan 25 13:50:19 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity ADM561 is
    port (    
	C1_M:      INOUT  STD_LOGIC;    
	C1_P:      INOUT  STD_LOGIC;    
	C2_M:      INOUT  STD_LOGIC;    
	C2_P:      INOUT  STD_LOGIC;    
	EN_N:      IN     STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	R1_IN:     IN     STD_LOGIC;    
	R1_OUT:    OUT    STD_LOGIC;    
	R2_IN:     IN     STD_LOGIC;    
	R2_OUT:    OUT    STD_LOGIC;    
	R3_IN:     IN     STD_LOGIC;    
	R3_OUT:    OUT    STD_LOGIC;    
	R4_IN:     IN     STD_LOGIC;    
	R4_OUT:    OUT    STD_LOGIC;    
	R5_IN:     IN     STD_LOGIC;    
	R5_OUT:    OUT    STD_LOGIC;    
	SHDN:      IN     STD_LOGIC;    
	T1_IN:     IN     STD_LOGIC;    
	T1_OUT:    OUT    STD_LOGIC;    
	T2_IN:     IN     STD_LOGIC;    
	T2_OUT:    OUT    STD_LOGIC;    
	T3_IN:     IN     STD_LOGIC;    
	T3_OUT:    OUT    STD_LOGIC;    
	T4_IN:     IN     STD_LOGIC;    
	T4_OUT:    OUT    STD_LOGIC;    
	V_M:       IN     STD_LOGIC;    
	V_P:       IN     STD_LOGIC;    
	VCC:       IN     STD_LOGIC);
end ADM561;
