Hierarchy	Input	Constant Input	Unused Input	Floating Input	Output	Constant Output	Unused Output	Floating Output	Bidir	Constant Bidir	Unused Bidir	Input only Bidir	Output only Bidir
u_core|u_dual_config|dual_boot_0|alt_dual_boot_avmm_comp	39	0	28	0	32	0	0	0	0	0	0	0	0
u_core|u_dual_config|dual_boot_0	39	0	0	0	32	0	0	0	0	0	0	0	0
u_core|u_dual_config	39	37	0	37	0	37	37	37	0	0	0	0	0
u_core|u_jtag_unlock|jtag_atom	7	0	0	0	2	0	0	0	0	0	0	0	0
u_core|u_jtag_unlock	6	1	0	1	1	1	1	1	0	0	0	0	0
u_core|u_smbus_filtered_relay_3|sync_slave_sda_inst	2	0	0	0	3	0	0	0	0	0	0	0	0
u_core|u_smbus_filtered_relay_3|sync_slave_scl_inst	2	0	0	0	3	0	0	0	0	0	0	0	0
u_core|u_smbus_filtered_relay_3|sync_master_sda_inst	2	0	0	0	3	0	0	0	0	0	0	0	0
u_core|u_smbus_filtered_relay_3|sync_master_scl_inst	2	0	0	0	3	0	0	0	0	0	0	0	0
u_core|u_smbus_filtered_relay_3	49	43	0	43	4	43	43	43	0	0	0	0	0
u_core|u_smbus_filtered_relay_2|sync_slave_sda_inst	2	0	0	0	3	0	0	0	0	0	0	0	0
u_core|u_smbus_filtered_relay_2|sync_slave_scl_inst	2	0	0	0	3	0	0	0	0	0	0	0	0
u_core|u_smbus_filtered_relay_2|sync_master_sda_inst	2	0	0	0	3	0	0	0	0	0	0	0	0
u_core|u_smbus_filtered_relay_2|sync_master_scl_inst	2	0	0	0	3	0	0	0	0	0	0	0	0
u_core|u_smbus_filtered_relay_2	49	43	0	43	4	43	43	43	0	0	0	0	0
u_core|u_smbus_filtered_relay_1|sync_slave_sda_inst	2	0	0	0	3	0	0	0	0	0	0	0	0
u_core|u_smbus_filtered_relay_1|sync_slave_scl_inst	2	0	0	0	3	0	0	0	0	0	0	0	0
u_core|u_smbus_filtered_relay_1|sync_master_sda_inst	2	0	0	0	3	0	0	0	0	0	0	0	0
u_core|u_smbus_filtered_relay_1|sync_master_scl_inst	2	0	0	0	3	0	0	0	0	0	0	0	0
u_core|u_smbus_filtered_relay_1	49	43	0	43	4	43	43	43	0	0	0	0	0
u_core	57	10	29	10	44	10	10	10	30	0	1	0	1
u_common_core|mWilson_City_Main|mGSX_Master|mToggle100KHz_SClock	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mGSX_Master	28	24	0	24	27	24	24	24	0	0	0	0	0
u_common_core|mWilson_City_Main|mRST_DEDI_BUSY_PLD_N	6	2	0	2	1	2	2	2	0	0	0	0	0
u_common_core|mWilson_City_Main|mRSMRST_Delay_Dedi	10	6	0	6	1	6	6	6	0	0	0	0	0
u_common_core|mWilson_City_Main|mEventLogger|mSampleCounter	3	0	0	0	32	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mEventLogger	35	0	0	0	43	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mIICRegs|mEventsRegs|mAccessDoneDelay	4	1	0	1	1	1	1	1	0	0	0	0	0
u_common_core|mWilson_City_Main|mIICRegs|mEventsRegs|mEventBRAM|mBlok3	39	9	0	9	8	9	9	9	0	0	0	0	0
u_common_core|mWilson_City_Main|mIICRegs|mEventsRegs|mEventBRAM|mBlok2	39	9	0	9	8	9	9	9	0	0	0	0	0
u_common_core|mWilson_City_Main|mIICRegs|mEventsRegs|mEventBRAM|mBlok1	39	9	0	9	8	9	9	9	0	0	0	0	0
u_common_core|mWilson_City_Main|mIICRegs|mEventsRegs|mEventBRAM|mBlok0	39	9	0	9	8	9	9	9	0	0	0	0	0
u_common_core|mWilson_City_Main|mIICRegs|mEventsRegs|mEventBRAM	56	0	0	0	8	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mIICRegs|mEventsRegs	59	0	1	0	9	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mIICRegs|mRWLUTRegs	18	0	0	0	17	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mIICRegs|mReadOnlyRegs	393	0	0	0	9	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mIICRegs|mIICRegsController|mIICSlave	13	0	0	0	15	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mIICRegs|mIICRegsController	31	0	0	0	28	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mIICRegs	176	22	0	22	9	22	22	22	0	0	0	0	0
u_common_core|mWilson_City_Main|mSCLGlitchFilter	4	1	0	1	1	1	1	1	0	0	0	0	0
u_common_core|mWilson_City_Main|mSDAGlitchFilter	4	1	0	1	1	1	1	1	0	0	0	0	0
u_common_core|mWilson_City_Main|mFault2Code8bits|mMainCounter	13	1	0	1	9	1	1	1	0	0	0	0	0
u_common_core|mWilson_City_Main|mFault2Code8bits	266	244	0	244	12	244	244	244	0	0	0	0	0
u_common_core|mWilson_City_Main|mLEDMuxy8	132	51	0	51	8	51	51	51	0	0	0	0	0
u_common_core|mWilson_City_Main|mLatchThermTrip_N_CPU2|mLatchOut	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mLatchThermTrip_N_CPU2|mLatchClr	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mLatchThermTrip_N_CPU2|mLatchSet	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mLatchThermTrip_N_CPU2	4	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mLatchThermTrip_N_CPU1|mLatchOut	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mLatchThermTrip_N_CPU1|mLatchClr	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mLatchThermTrip_N_CPU1|mLatchSet	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mLatchThermTrip_N_CPU1	4	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mGSX	84	47	0	47	81	47	47	47	0	0	0	0	0
u_common_core|mWilson_City_Main|mPwrBtnDebouncer	4	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mOnctl_fix	5	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|meSPI_Ctl|mDelayedBMCRst	4	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|meSPI_Ctl|mDelayedRsmRst	4	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|meSPI_Ctl	5	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mCaterr|caterr_dly_160ns	4	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mCaterr|caterr_dly_500us	4	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mCaterr	4	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mRst_Perst|mPERst	11	0	0	0	3	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mRst_Perst	11	0	0	0	3	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mled_control	90	5	0	5	16	5	5	5	0	0	0	0	0
u_common_core|mWilson_City_Main|mthermtrip_dly|thermtripDelayCounter	4	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mthermtrip_dly	8	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mThermTripDly	8	4	0	4	1	4	4	4	0	0	0	0	0
u_common_core|mWilson_City_Main|mSmaRT	6	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mProchot_CPU2	7	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mProchot_CPU1	7	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mMemhot_CPU2	7	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mMemhot_CPU1	7	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|Mstr_Seq_inst|WatchDogTimer_PSU	27	22	0	22	1	22	22	22	0	0	0	0	0
u_common_core|mWilson_City_Main|Mstr_Seq_inst|WatchDogTimer	27	22	0	22	1	22	22	22	0	0	0	0	0
u_common_core|mWilson_City_Main|Mstr_Seq_inst|counter	29	18	0	18	1	18	18	18	0	0	0	0	0
u_common_core|mWilson_City_Main|Mstr_Seq_inst	29	2	1	2	16	2	2	2	0	0	0	0	0
u_common_core|mWilson_City_Main|mADR|mPSPwrgdDlyDwn	12	8	0	8	1	8	8	8	0	0	0	0	0
u_common_core|mWilson_City_Main|mADR|mPSPwrgdDlyUp	15	11	0	11	1	11	11	11	0	0	0	0	0
u_common_core|mWilson_City_Main|mADR|mFM_P5V_EN_DLY	8	4	0	4	1	4	4	4	0	0	0	0	0
u_common_core|mWilson_City_Main|mADR|mFM_AUX_SW_EN_ADR_DLR	8	4	0	4	1	4	4	4	0	0	0	0	0
u_common_core|mWilson_City_Main|mADR	15	1	3	1	6	1	1	1	0	0	0	0	0
u_common_core|mWilson_City_Main|mPwrgdLogic|mPWRGD_PCH_Pwrok_DLY	7	3	0	3	1	3	3	3	0	0	0	0	0
u_common_core|mWilson_City_Main|mPwrgdLogic	12	0	0	0	4	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mCpu_Seq_CPU2|ForceOff_500usDly	15	10	0	10	1	10	10	10	0	0	0	0	0
u_common_core|mWilson_City_Main|mCpu_Seq_CPU2	12	1	1	1	16	1	1	1	0	0	0	0	0
u_common_core|mWilson_City_Main|mCpu_Seq_CPU1|ForceOff_500usDly	15	10	0	10	1	10	10	10	0	0	0	0	0
u_common_core|mWilson_City_Main|mCpu_Seq_CPU1	12	1	1	1	16	1	1	1	0	0	0	0	0
u_common_core|mWilson_City_Main|mMem_SeqCPU2|ForceOff_500usDly	15	10	0	10	1	10	10	10	0	0	0	0	0
u_common_core|mWilson_City_Main|mMem_SeqCPU2|mP3V3_DLY	7	3	0	3	1	3	3	3	0	0	0	0	0
u_common_core|mWilson_City_Main|mMem_SeqCPU2|mVDD_DLY	7	3	0	3	1	3	3	3	0	0	0	0	0
u_common_core|mWilson_City_Main|mMem_SeqCPU2	10	1	0	1	8	1	1	1	0	0	0	0	0
u_common_core|mWilson_City_Main|mMem_SeqCPU1|ForceOff_500usDly	15	10	0	10	1	10	10	10	0	0	0	0	0
u_common_core|mWilson_City_Main|mMem_SeqCPU1|mP3V3_DLY	7	3	0	3	1	3	3	3	0	0	0	0	0
u_common_core|mWilson_City_Main|mMem_SeqCPU1|mVDD_DLY	7	3	0	3	1	3	3	3	0	0	0	0	0
u_common_core|mWilson_City_Main|mMem_SeqCPU1	10	1	0	1	8	1	1	1	0	0	0	0	0
u_common_core|mWilson_City_Main|mClockLogic	5	0	0	0	2	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mMainVR_Seq	6	0	0	0	5	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mPSU_Seq|mPS_EN_dly	7	3	0	3	1	3	3	3	0	0	0	0	0
u_common_core|mWilson_City_Main|mPSU_Seq|mPS_PWROK_DLY	11	7	0	7	1	7	7	7	0	0	0	0	0
u_common_core|mWilson_City_Main|mPSU_Seq	6	0	0	0	4	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSysCheck|mLatchOut2	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSysCheck|mSocket2Removed	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSysCheck|mLatchOut1	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSysCheck|mSocket1Removed	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSysCheck	17	0	0	0	4	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mPch_Seq|mP1V8_AUX_EN	6	2	0	2	1	2	2	2	0	0	0	0	0
u_common_core|mWilson_City_Main|mPch_Seq|mRSMRST	9	5	0	5	1	5	5	5	0	0	0	0	0
u_common_core|mWilson_City_Main|mPch_Seq	12	0	0	0	6	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mBmc_Seq|mSLP_SUS	5	1	0	1	1	1	1	1	0	0	0	0	0
u_common_core|mWilson_City_Main|mBmc_Seq|mRST_SRST_BMC_N	6	2	0	2	1	2	2	2	0	0	0	0	0
u_common_core|mWilson_City_Main|mBmc_Seq	9	0	0	0	4	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync3|SyncBlock[7].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync3|SyncBlock[6].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync3|SyncBlock[5].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync3|SyncBlock[4].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync3|SyncBlock[3].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync3|SyncBlock[2].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync3|SyncBlock[1].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync3|SyncBlock[0].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync3	10	0	0	0	8	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[21].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[20].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[19].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[18].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[17].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[16].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[15].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[14].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[13].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[12].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[11].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[10].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[9].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[8].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[7].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[6].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[5].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[4].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[3].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[2].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[1].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[0].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync2	24	0	0	0	22	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync1|SyncBlock[3].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync1|SyncBlock[2].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync1|SyncBlock[1].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync1|SyncBlock[0].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync1	6	0	0	0	4	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[19].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[18].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[17].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[16].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[15].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[14].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[13].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[12].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[11].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[10].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[9].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[8].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[7].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[6].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[5].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[4].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[3].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[2].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[1].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[0].mISync	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mSlpSync0	22	0	0	0	20	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mTogglew1SCE	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mTogglew20mSCE	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mToggle250mSCE	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mClkDivTree|m20mSCE	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mClkDivTree|m1SCE	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mClkDivTree|m250mSCE	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mClkDivTree|m1mSCE	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mClkDivTree|m500uSCE	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mClkDivTree|m50uSCE	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mClkDivTree|m10uSCE	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mClkDivTree|m5uSCE	3	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mClkDivTree|m1uSCE	3	1	0	1	1	1	1	1	0	0	0	0	0
u_common_core|mWilson_City_Main|mClkDivTree	2	0	0	0	8	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main|mReset	2	0	0	0	1	0	0	0	0	0	0	0	0
u_common_core|mWilson_City_Main	85	1	2	1	72	1	1	1	1	0	0	0	0
u_common_core	85	0	0	0	71	0	0	0	2	0	0	0	0
u_pfr_sys_clocks_reset|u_reset_sync_spi_clk	5	1	0	1	1	1	1	1	0	0	0	0	0
u_pfr_sys_clocks_reset|u_reset_sync_sys_clk	5	1	0	1	1	1	1	1	0	0	0	0	0
u_pfr_sys_clocks_reset|u_reset_sync_clk2M	5	1	0	1	1	1	1	1	0	0	0	0	0
u_pfr_sys_clocks_reset|u_reset_sync_clk50M	5	1	0	1	1	1	1	1	0	0	0	0	0
u_pfr_sys_clocks_reset|u_sys_pll_ip|altpll_component|auto_generated	3	0	0	0	6	0	0	0	0	0	0	0	0
u_pfr_sys_clocks_reset|u_sys_pll_ip	2	0	0	0	5	0	0	0	0	0	0	0	0
u_pfr_sys_clocks_reset	2	0	0	0	9	0	0	0	0	0	0	0	0