| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| u_core|u_smbus_filtered_relay_3|gen_filter_enabled.cmd_enable_mem|auto_generated |
56 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_filtered_relay_3|sync_slave_sda_inst |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_filtered_relay_3|sync_slave_scl_inst |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_filtered_relay_3|sync_master_sda_inst |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_filtered_relay_3|sync_master_scl_inst |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_filtered_relay_3 |
49 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_filtered_relay_2|gen_filter_enabled.cmd_enable_mem|auto_generated |
56 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_filtered_relay_2|sync_slave_sda_inst |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_filtered_relay_2|sync_slave_scl_inst |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_filtered_relay_2|sync_master_sda_inst |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_filtered_relay_2|sync_master_scl_inst |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_filtered_relay_2 |
49 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_filtered_relay_1|gen_filter_enabled.cmd_enable_mem|auto_generated |
56 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_filtered_relay_1|sync_slave_sda_inst |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_filtered_relay_1|sync_slave_scl_inst |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_filtered_relay_1|sync_master_sda_inst |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_filtered_relay_1|sync_master_scl_inst |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_filtered_relay_1 |
49 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|pch_spi_filter_inst|cmd_enable_mem|auto_generated |
55 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|pch_spi_filter_inst |
51 |
35 |
3 |
35 |
34 |
35 |
35 |
35 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|bmc_spi_filter_inst|cmd_enable_mem|auto_generated |
57 |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|bmc_spi_filter_inst |
52 |
35 |
0 |
35 |
34 |
35 |
35 |
35 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|qspi_inf_inst|clk_div_new_inst_2 |
9 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|qspi_inf_inst|inf_sc_fifo_ser_data_inst|inf_sc_fifo_ser_data |
60 |
38 |
0 |
38 |
20 |
38 |
38 |
38 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|qspi_inf_inst|inf_sc_fifo_ser_data_inst |
22 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|qspi_inf_inst|qspi_inf_mux_inst|qspi_inf_mux|arb|adder |
12 |
3 |
0 |
3 |
6 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|qspi_inf_inst|qspi_inf_mux_inst|qspi_inf_mux|arb |
7 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|qspi_inf_inst|qspi_inf_mux_inst|qspi_inf_mux |
60 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|qspi_inf_inst|qspi_inf_mux_inst |
60 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|qspi_inf_inst|adapter_8_4_inst |
26 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|qspi_inf_inst|adapter_8_2_inst |
26 |
2 |
0 |
2 |
20 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|qspi_inf_inst|adapter_8_1_inst |
26 |
3 |
0 |
3 |
20 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|qspi_inf_inst|demultiplexer_inst |
28 |
9 |
2 |
9 |
70 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|qspi_inf_inst |
67 |
0 |
4 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|serial_flash_inf_cmd_gen_inst|data_adapter_8_32_inst |
14 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|serial_flash_inf_cmd_gen_inst|data_adapter_32_8_inst |
36 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|serial_flash_inf_cmd_gen_inst |
126 |
1 |
0 |
1 |
81 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|multiplexer|arb|adder |
8 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|multiplexer|arb |
6 |
0 |
4 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|multiplexer |
77 |
0 |
0 |
0 |
39 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|merlin_demultiplexer_0 |
41 |
4 |
2 |
4 |
75 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|xip_addr_adaption |
106 |
7 |
2 |
7 |
111 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|xip_controller|avst_fifo_inst|avst_fifo |
77 |
39 |
0 |
39 |
36 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|xip_controller|avst_fifo_inst |
38 |
0 |
0 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|xip_controller |
162 |
3 |
16 |
3 |
106 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst|csr_controller |
84 |
37 |
3 |
37 |
177 |
37 |
37 |
37 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control|spi_master_inst |
116 |
11 |
0 |
11 |
78 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_spi_control |
206 |
1 |
0 |
1 |
153 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_rfnvram_master|u0|u_rxfifo|the_dp_ram|auto_generated |
18 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_rfnvram_master|u0|u_rxfifo |
13 |
0 |
0 |
0 |
15 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_rfnvram_master|u0|u_txfifo|the_dp_ram|auto_generated |
20 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_rfnvram_master|u0|u_txfifo |
15 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_rfnvram_master|u0|u_txout |
29 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_rfnvram_master|u0|u_clk_cnt |
65 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_rfnvram_master|u0|u_condt_gen |
12 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_rfnvram_master|u0|u_condt_det |
9 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_rfnvram_master|u0|u_spksupp |
12 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_rfnvram_master|u0|u_txshifter |
20 |
0 |
0 |
0 |
19 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_rfnvram_master|u0|u_rxshifter |
11 |
0 |
0 |
0 |
18 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_rfnvram_master|u0|u_mstfsm |
26 |
0 |
7 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_rfnvram_master|u0|u_csr |
67 |
50 |
28 |
50 |
95 |
50 |
50 |
50 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_rfnvram_master|u0 |
42 |
0 |
0 |
0 |
34 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_rfnvram_master |
42 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|reg_file_0|u_fifo|u_sp_ram|altsyncram_component|auto_generated |
17 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|reg_file_0|u_fifo|u_sp_ram |
17 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|reg_file_0|u_fifo |
13 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|reg_file_0|dp_ram_0|altsyncram_component|auto_generated |
35 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|reg_file_0|dp_ram_0 |
35 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|reg_file_0 |
56 |
72 |
0 |
72 |
103 |
72 |
72 |
72 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|bmc_slave|i_altr_i2c_clk_cnt |
98 |
78 |
0 |
78 |
12 |
78 |
78 |
78 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|bmc_slave|i_altr_i2c_txout |
34 |
23 |
0 |
23 |
2 |
23 |
23 |
23 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|bmc_slave|i_altr_i2c_rxshifter |
38 |
17 |
0 |
17 |
27 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|bmc_slave|i_altr_i2c_txshifter |
42 |
21 |
0 |
21 |
24 |
21 |
21 |
21 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|bmc_slave|i_altr_i2c_avl_mst_intf_gen |
50 |
24 |
24 |
24 |
75 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|bmc_slave|i_altr_i2c_slvfsm |
31 |
9 |
7 |
9 |
17 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|bmc_slave|rx_databuffer |
13 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|bmc_slave|tx_databuffer |
13 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|bmc_slave|i_altr_i2c_condt_det |
12 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|bmc_slave|i_altr_i2c_spksupp |
12 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|bmc_slave |
39 |
0 |
0 |
0 |
68 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|pch_slave|i_altr_i2c_clk_cnt |
98 |
78 |
0 |
78 |
12 |
78 |
78 |
78 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|pch_slave|i_altr_i2c_txout |
34 |
23 |
0 |
23 |
2 |
23 |
23 |
23 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|pch_slave|i_altr_i2c_rxshifter |
38 |
17 |
0 |
17 |
27 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|pch_slave|i_altr_i2c_txshifter |
42 |
21 |
0 |
21 |
24 |
21 |
21 |
21 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|pch_slave|i_altr_i2c_avl_mst_intf_gen |
50 |
24 |
24 |
24 |
75 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|pch_slave|i_altr_i2c_slvfsm |
31 |
9 |
7 |
9 |
17 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|pch_slave|rx_databuffer |
13 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|pch_slave|tx_databuffer |
13 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|pch_slave|i_altr_i2c_condt_det |
12 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|pch_slave|i_altr_i2c_spksupp |
12 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox|pch_slave |
39 |
0 |
0 |
0 |
68 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_smbus_mailbox |
48 |
0 |
24 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_mem411|altsyncram_component|auto_generated |
132 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_mem411 |
132 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_mem412|altsyncram_component|auto_generated |
132 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_mem412 |
132 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_mem221|altsyncram_component|auto_generated |
140 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_mem221 |
140 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_mem222|altsyncram_component|auto_generated |
140 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_mem222 |
140 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_mem211|altsyncram_component|auto_generated |
140 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_mem211 |
140 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_mem212|altsyncram_component|auto_generated |
140 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_mem212 |
140 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_jpc |
7 |
5 |
0 |
5 |
22 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_ma256|i_cs411 |
531 |
1 |
0 |
1 |
266 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_ma256|i_m256_9 |
265 |
1 |
0 |
1 |
265 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_ma256|i_cm32|altsyncram_component|auto_generated |
136 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_ma256|i_cm32 |
136 |
1 |
0 |
1 |
8 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_ma256|i_cm31|altsyncram_component|auto_generated |
136 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_ma256|i_cm31 |
136 |
1 |
0 |
1 |
8 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa|i_ma256 |
775 |
1 |
0 |
1 |
258 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_ecdsa |
267 |
0 |
0 |
0 |
259 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|sha_inst_top|sha_rnd_0|csa6 |
193 |
1 |
0 |
1 |
128 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|sha_inst_top|sha_rnd_0|csa5 |
193 |
1 |
0 |
1 |
128 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|sha_inst_top|sha_rnd_0|csa4 |
193 |
1 |
0 |
1 |
128 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|sha_inst_top|sha_rnd_0|csa3 |
193 |
1 |
0 |
1 |
128 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|sha_inst_top|sha_rnd_0|csa2 |
193 |
1 |
0 |
1 |
128 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|sha_inst_top|sha_rnd_0|csa1 |
193 |
1 |
0 |
1 |
128 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|sha_inst_top|sha_rnd_0|csa0 |
193 |
1 |
0 |
1 |
128 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|sha_inst_top|sha_rnd_0|fn_Sigma1 |
65 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|sha_inst_top|sha_rnd_0|fn_ch |
192 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|sha_inst_top|sha_rnd_0|fn_Sigma0 |
65 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|sha_inst_top|sha_rnd_0|fn_maj |
192 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|sha_inst_top|sha_rnd_0 |
641 |
0 |
0 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|sha_inst_top |
653 |
0 |
7 |
0 |
128 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|init_state |
140 |
0 |
0 |
0 |
896 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|msg_schedule_top|msg_sch_inst|csa1 |
193 |
1 |
0 |
1 |
128 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|msg_schedule_top|msg_sch_inst|csa0 |
193 |
1 |
0 |
1 |
128 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|msg_schedule_top|msg_sch_inst |
257 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|msg_schedule_top |
1037 |
0 |
8 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst|kt_inst |
8 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha|sha_inst |
1030 |
0 |
0 |
0 |
769 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto|u_sha |
1030 |
514 |
0 |
514 |
257 |
514 |
514 |
514 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_crypto |
40 |
0 |
1 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_timer_bank |
40 |
11 |
13 |
11 |
32 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|rst_controller |
33 |
31 |
0 |
31 |
2 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|irq_mapper |
2 |
32 |
2 |
32 |
32 |
32 |
32 |
32 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_018|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_018 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_017|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_017 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_016|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_016 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_015|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_015 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_014|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_014 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_013|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_013 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_012|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_012 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_011|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_011 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_010|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_010 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_009|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_009 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_008|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_008 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_007|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_007 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_006|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_006 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_005|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_005 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_004|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_004 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_003|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_003 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_002|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_002 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_001|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter_001 |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter|error_adapter_0 |
38 |
1 |
2 |
1 |
37 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|avalon_st_adapter |
38 |
0 |
0 |
0 |
37 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|crosser_003|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|crosser_003|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|crosser_003|clock_xer |
140 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|crosser_003 |
142 |
2 |
0 |
2 |
136 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|crosser_002|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|crosser_002|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|crosser_002|clock_xer |
140 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|crosser_002 |
142 |
2 |
0 |
2 |
136 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|crosser_001|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|crosser_001|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|crosser_001|clock_xer |
140 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|crosser_001 |
142 |
2 |
0 |
2 |
136 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|crosser|clock_xer|out_to_in_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|crosser|clock_xer|in_to_out_synchronizer |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|crosser|clock_xer |
140 |
0 |
0 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|crosser |
142 |
2 |
0 |
2 |
136 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_mux_001|arb|adder |
12 |
6 |
0 |
6 |
6 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_mux_001|arb |
7 |
0 |
4 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_mux_001 |
408 |
0 |
0 |
0 |
138 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_mux|arb|adder |
76 |
38 |
0 |
38 |
38 |
38 |
38 |
38 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_mux|arb |
23 |
0 |
4 |
0 |
19 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_mux |
2568 |
0 |
0 |
0 |
154 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_018 |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_017 |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_016 |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_015 |
139 |
4 |
2 |
4 |
271 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_014 |
139 |
4 |
2 |
4 |
271 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_013 |
139 |
4 |
2 |
4 |
271 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_012 |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_011 |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_010 |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_009 |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_008 |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_007 |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_006 |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_005 |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_004 |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_003 |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_002 |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux_001 |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|rsp_demux |
138 |
1 |
2 |
1 |
136 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_018 |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_017 |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_016 |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_015|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_015|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_015 |
273 |
0 |
0 |
0 |
137 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_014|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_014|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_014 |
273 |
0 |
0 |
0 |
137 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_013|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_013|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_013 |
273 |
0 |
0 |
0 |
137 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_012 |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_011 |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_010 |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_009 |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_008 |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_007 |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_006 |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_005 |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_004 |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_003 |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_002 |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux_001 |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_mux |
138 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_demux_001 |
140 |
9 |
2 |
9 |
406 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|cmd_demux |
156 |
361 |
2 |
361 |
2566 |
361 |
361 |
361 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_020|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_020 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_019|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_019 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_018|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_018 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_017|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_017 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_016|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_016 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_015|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_015 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_014|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_014 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_013|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_013 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_012|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_012 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_011|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_011 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_010|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_010 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_009|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_009 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_008|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_008 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_007|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_007 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_006|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_006 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_005|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_005 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_004|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_004 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_003|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_003 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_002|the_default_decode |
0 |
19 |
0 |
19 |
19 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_002 |
119 |
0 |
2 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_001|the_default_decode |
0 |
24 |
0 |
24 |
24 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router_001 |
119 |
0 |
7 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router|the_default_decode |
0 |
24 |
0 |
24 |
24 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|router |
119 |
0 |
7 |
0 |
136 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_gpi_1_s1_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_gpi_1_s1_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_gpi_1_s1_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_gpo_1_s1_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_gpo_1_s1_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_gpo_1_s1_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_global_state_reg_s1_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_global_state_reg_s1_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_global_state_reg_s1_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_nios_ram_s1_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_nios_ram_s1_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_nios_ram_s1_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_nios_debug_mem_slave_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_nios_debug_mem_slave_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_nios_debug_mem_slave_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_ufm_data_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_ufm_data_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_ufm_data_agent |
330 |
39 |
56 |
39 |
347 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_ufm_csr_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_ufm_csr_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_ufm_csr_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_timer_bank_avmm_bridge_avmm_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_timer_bank_avmm_bridge_avmm_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_timer_bank_avmm_bridge_avmm_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_pch_we_avmm_bridge_avmm_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_pch_we_avmm_bridge_avmm_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_pch_we_avmm_bridge_avmm_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_avmm_bridge_avmm_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_avmm_bridge_avmm_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_avmm_bridge_avmm_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_avmm_bridge_avmm_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_bmc_we_avmm_bridge_avmm_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_bmc_we_avmm_bridge_avmm_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_bmc_we_avmm_bridge_avmm_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_rfnvram_smbus_master_avmm_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_rfnvram_smbus_master_avmm_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_rfnvram_smbus_master_avmm_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_mailbox_avmm_bridge_avmm_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_mailbox_avmm_bridge_avmm_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_mailbox_avmm_bridge_avmm_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_relay3_avmm_bridge_avmm_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_relay3_avmm_bridge_avmm_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_relay3_avmm_bridge_avmm_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_relay2_avmm_bridge_avmm_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_relay2_avmm_bridge_avmm_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_relay2_avmm_bridge_avmm_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_csr_avmm_bridge_0_avmm_agent_rdata_fifo |
79 |
41 |
0 |
41 |
36 |
41 |
41 |
41 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_csr_avmm_bridge_0_avmm_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_csr_avmm_bridge_0_avmm_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_csr_avmm_bridge_0_avmm_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_relay1_avmm_bridge_avmm_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_relay1_avmm_bridge_avmm_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_relay1_avmm_bridge_avmm_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_crypto_avmm_bridge_avmm_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_crypto_avmm_bridge_avmm_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_crypto_avmm_bridge_avmm_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_dual_config_avalon_agent_rsp_fifo |
159 |
39 |
0 |
39 |
118 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_dual_config_avalon_agent|uncompressor |
49 |
1 |
0 |
1 |
47 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_dual_config_avalon_agent |
330 |
39 |
56 |
39 |
346 |
39 |
39 |
39 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_nios_instruction_master_agent |
213 |
42 |
104 |
42 |
151 |
42 |
42 |
42 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_nios_data_master_agent |
213 |
42 |
104 |
42 |
151 |
42 |
42 |
42 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_gpi_1_s1_translator |
115 |
6 |
33 |
6 |
36 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_gpo_1_s1_translator |
115 |
6 |
33 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_global_state_reg_s1_translator |
115 |
6 |
33 |
6 |
70 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_nios_ram_s1_translator |
115 |
7 |
20 |
7 |
85 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_nios_debug_mem_slave_translator |
115 |
5 |
23 |
5 |
82 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_ufm_data_translator |
116 |
4 |
14 |
4 |
88 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_ufm_csr_translator |
115 |
6 |
31 |
6 |
69 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_timer_bank_avmm_bridge_avmm_translator |
115 |
5 |
21 |
5 |
79 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_pch_we_avmm_bridge_avmm_translator |
115 |
5 |
21 |
5 |
79 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_avmm_bridge_avmm_translator |
115 |
4 |
7 |
4 |
93 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_bmc_we_avmm_bridge_avmm_translator |
115 |
5 |
21 |
5 |
79 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_rfnvram_smbus_master_avmm_translator |
115 |
4 |
28 |
4 |
72 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_mailbox_avmm_bridge_avmm_translator |
115 |
4 |
24 |
4 |
76 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_relay3_avmm_bridge_avmm_translator |
115 |
5 |
24 |
5 |
76 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_relay2_avmm_bridge_avmm_translator |
115 |
5 |
24 |
5 |
76 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_spi_filter_csr_avmm_bridge_0_avmm_translator |
115 |
4 |
26 |
4 |
74 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_relay1_avmm_bridge_avmm_translator |
115 |
5 |
24 |
5 |
76 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_crypto_avmm_bridge_avmm_translator |
115 |
5 |
25 |
5 |
75 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_dual_config_avalon_translator |
115 |
6 |
29 |
6 |
71 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_nios_instruction_master_translator |
116 |
51 |
0 |
51 |
108 |
51 |
51 |
51 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0|u_nios_data_master_translator |
116 |
12 |
0 |
12 |
108 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|mm_interconnect_0 |
734 |
0 |
0 |
0 |
846 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_ufm|altera_onchip_flash_block |
34 |
2 |
0 |
2 |
36 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_ufm|avmm_data_controller|sector_convertor |
3 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_ufm|avmm_data_controller|sector_address_write_protection_checker |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_ufm|avmm_data_controller|access_address_write_protection_checker |
28 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_ufm|avmm_data_controller|address_convertor |
23 |
0 |
0 |
0 |
23 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_ufm|avmm_data_controller|address_range_checker |
23 |
5 |
0 |
5 |
1 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_ufm|avmm_data_controller |
124 |
6 |
2 |
6 |
76 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_ufm|avmm_csr_controller |
47 |
4 |
4 |
4 |
64 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_ufm |
91 |
0 |
0 |
0 |
66 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_timer_bank_avmm_bridge |
80 |
0 |
0 |
0 |
80 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_spi_filter_pch_we_avmm_bridge |
80 |
0 |
0 |
0 |
80 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_spi_filter_csr_avmm_bridge_0 |
76 |
0 |
0 |
0 |
76 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_spi_filter_bmc_we_avmm_bridge |
80 |
0 |
0 |
0 |
80 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_spi_filter_avmm_bridge |
95 |
0 |
0 |
0 |
95 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_rfnvram_smbus_master |
74 |
0 |
0 |
0 |
74 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_relay3_avmm_bridge |
77 |
0 |
0 |
0 |
77 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_relay2_avmm_bridge |
77 |
0 |
0 |
0 |
77 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_relay1_avmm_bridge |
77 |
0 |
0 |
0 |
77 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios_ram|the_altsyncram|auto_generated |
51 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios_ram |
55 |
1 |
1 |
1 |
32 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_debug_slave_wrapper|the_pfr_sys_u_nios_cpu_debug_slave_sysclk |
43 |
0 |
0 |
0 |
48 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_debug_slave_wrapper|the_pfr_sys_u_nios_cpu_debug_slave_tck |
130 |
0 |
1 |
0 |
43 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_debug_slave_wrapper |
123 |
0 |
0 |
0 |
50 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_nios2_ocimem|pfr_sys_u_nios_cpu_ociram_sp_ram|the_altsyncram|auto_generated |
47 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_nios2_ocimem|pfr_sys_u_nios_cpu_ociram_sp_ram |
47 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_nios2_ocimem |
92 |
0 |
6 |
0 |
65 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_nios2_avalon_reg |
48 |
0 |
29 |
0 |
68 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_nios2_oci_im |
54 |
38 |
51 |
38 |
47 |
38 |
38 |
38 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_nios2_oci_pib |
0 |
36 |
0 |
36 |
36 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_nios2_oci_fifo|the_pfr_sys_u_nios_cpu_nios2_oci_fifo_cnt_inc |
5 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_nios2_oci_fifo|the_pfr_sys_u_nios_cpu_nios2_oci_fifo_wrptr_inc |
4 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_nios2_oci_fifo|the_pfr_sys_u_nios_cpu_nios2_oci_compute_input_tm_cnt |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_nios2_oci_fifo |
115 |
0 |
65 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_nios2_oci_dtrace|pfr_sys_u_nios_cpu_nios2_oci_trc_ctrl_td_mode |
9 |
0 |
6 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_nios2_oci_dtrace |
117 |
0 |
106 |
0 |
72 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_nios2_oci_itrace |
24 |
53 |
24 |
53 |
53 |
53 |
53 |
53 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_nios2_oci_dbrk |
102 |
0 |
0 |
0 |
106 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_nios2_oci_xbrk |
68 |
5 |
65 |
5 |
6 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_nios2_oci_break |
51 |
36 |
6 |
36 |
71 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci|the_pfr_sys_u_nios_cpu_nios2_oci_debug |
50 |
1 |
30 |
1 |
7 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_nios2_oci |
184 |
0 |
0 |
0 |
69 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|pfr_sys_u_nios_cpu_register_bank_b|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|pfr_sys_u_nios_cpu_register_bank_b |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|pfr_sys_u_nios_cpu_register_bank_a|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|pfr_sys_u_nios_cpu_register_bank_a |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu|the_pfr_sys_u_nios_cpu_test_bench |
603 |
3 |
569 |
3 |
33 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios|cpu |
149 |
2 |
32 |
2 |
139 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_nios |
148 |
0 |
0 |
0 |
137 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_mailbox_avmm_bridge |
78 |
0 |
0 |
0 |
78 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_gpo_1 |
38 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_gpi_1 |
36 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_global_state_reg |
38 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_dual_config|alt_dual_boot_avmm_comp |
39 |
0 |
28 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_dual_config |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys|u_crypto_avmm_bridge |
76 |
0 |
0 |
0 |
76 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_core|u_pfr_sys |
403 |
201 |
0 |
201 |
567 |
201 |
201 |
201 |
0 |
0 |
0 |
0 |
0 |
| u_core |
59 |
4 |
20 |
4 |
41 |
4 |
4 |
4 |
27 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mGSX_Master|mToggle100KHz_SClock |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mGSX_Master |
28 |
24 |
0 |
24 |
27 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mRST_DEDI_BUSY_PLD_N |
6 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mRSMRST_Delay_Dedi |
10 |
6 |
0 |
6 |
1 |
6 |
6 |
6 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mEventLogger|mSampleCounter |
3 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mEventLogger |
35 |
0 |
0 |
0 |
43 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mIICRegs|mEventsRegs|mAccessDoneDelay |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mIICRegs|mEventsRegs|mEventBRAM|mBlok3 |
39 |
9 |
0 |
9 |
8 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mIICRegs|mEventsRegs|mEventBRAM|mBlok2 |
39 |
9 |
0 |
9 |
8 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mIICRegs|mEventsRegs|mEventBRAM|mBlok1 |
39 |
9 |
0 |
9 |
8 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mIICRegs|mEventsRegs|mEventBRAM|mBlok0 |
39 |
9 |
0 |
9 |
8 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mIICRegs|mEventsRegs|mEventBRAM |
56 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mIICRegs|mEventsRegs |
59 |
0 |
1 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mIICRegs|mRWLUTRegs |
18 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mIICRegs|mReadOnlyRegs |
393 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mIICRegs|mIICRegsController|mIICSlave |
13 |
0 |
0 |
0 |
15 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mIICRegs|mIICRegsController |
31 |
0 |
0 |
0 |
28 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mIICRegs |
176 |
22 |
0 |
22 |
9 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSCLGlitchFilter |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSDAGlitchFilter |
4 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mFault2Code8bits|mMainCounter |
13 |
1 |
0 |
1 |
9 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mFault2Code8bits |
266 |
244 |
0 |
244 |
12 |
244 |
244 |
244 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mLEDMuxy8 |
132 |
51 |
0 |
51 |
8 |
51 |
51 |
51 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mLatchThermTrip_N_CPU2|mLatchOut |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mLatchThermTrip_N_CPU2|mLatchClr |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mLatchThermTrip_N_CPU2|mLatchSet |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mLatchThermTrip_N_CPU2 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mLatchThermTrip_N_CPU1|mLatchOut |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mLatchThermTrip_N_CPU1|mLatchClr |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mLatchThermTrip_N_CPU1|mLatchSet |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mLatchThermTrip_N_CPU1 |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mGSX |
84 |
47 |
0 |
47 |
81 |
47 |
47 |
47 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mPwrBtnDebouncer |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mOnctl_fix |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|meSPI_Ctl|mDelayedBMCRst |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|meSPI_Ctl|mDelayedRsmRst |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|meSPI_Ctl |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mCaterr|caterr_dly_160ns |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mCaterr|caterr_dly_500us |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mCaterr |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mRst_Perst|mPERst |
11 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mRst_Perst |
11 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mled_control |
90 |
5 |
0 |
5 |
16 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mthermtrip_dly|thermtripDelayCounter |
4 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mthermtrip_dly |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mThermTripDly |
8 |
4 |
0 |
4 |
1 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSmaRT |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mProchot_CPU2 |
7 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mProchot_CPU1 |
7 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mMemhot_CPU2 |
7 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mMemhot_CPU1 |
7 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|Mstr_Seq_inst|WatchDogTimer_PSU |
27 |
22 |
0 |
22 |
1 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|Mstr_Seq_inst|WatchDogTimer |
27 |
22 |
0 |
22 |
1 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|Mstr_Seq_inst|counter |
29 |
18 |
0 |
18 |
1 |
18 |
18 |
18 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|Mstr_Seq_inst |
29 |
2 |
1 |
2 |
16 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mADR|mPSPwrgdDlyDwn |
12 |
8 |
0 |
8 |
1 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mADR|mPSPwrgdDlyUp |
15 |
11 |
0 |
11 |
1 |
11 |
11 |
11 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mADR|mFM_P5V_EN_DLY |
8 |
4 |
0 |
4 |
1 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mADR|mFM_AUX_SW_EN_ADR_DLR |
8 |
4 |
0 |
4 |
1 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mADR |
15 |
1 |
3 |
1 |
6 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mPwrgdLogic|mPWRGD_PCH_Pwrok_DLY |
7 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mPwrgdLogic |
12 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mCpu_Seq_CPU2|ForceOff_500usDly |
15 |
10 |
0 |
10 |
1 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mCpu_Seq_CPU2 |
12 |
1 |
1 |
1 |
16 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mCpu_Seq_CPU1|ForceOff_500usDly |
15 |
10 |
0 |
10 |
1 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mCpu_Seq_CPU1 |
12 |
1 |
1 |
1 |
16 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mMem_SeqCPU2|ForceOff_500usDly |
15 |
10 |
0 |
10 |
1 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mMem_SeqCPU2|mP3V3_DLY |
7 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mMem_SeqCPU2|mVDD_DLY |
7 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mMem_SeqCPU2 |
10 |
1 |
0 |
1 |
8 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mMem_SeqCPU1|ForceOff_500usDly |
15 |
10 |
0 |
10 |
1 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mMem_SeqCPU1|mP3V3_DLY |
7 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mMem_SeqCPU1|mVDD_DLY |
7 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mMem_SeqCPU1 |
10 |
1 |
0 |
1 |
8 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mClockLogic |
5 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mMainVR_Seq |
6 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mPSU_Seq|mPS_EN_dly |
7 |
3 |
0 |
3 |
1 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mPSU_Seq|mPS_PWROK_DLY |
11 |
7 |
0 |
7 |
1 |
7 |
7 |
7 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mPSU_Seq |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSysCheck|mLatchOut2 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSysCheck|mSocket2Removed |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSysCheck|mLatchOut1 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSysCheck|mSocket1Removed |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSysCheck |
17 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mPch_Seq|mP1V8_AUX_EN |
6 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mPch_Seq|mRSMRST |
9 |
5 |
0 |
5 |
1 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mPch_Seq |
12 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mBmc_Seq|mSLP_SUS |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mBmc_Seq|mRST_SRST_BMC_N |
6 |
2 |
0 |
2 |
1 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mBmc_Seq |
9 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync3|SyncBlock[7].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync3|SyncBlock[6].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync3|SyncBlock[5].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync3|SyncBlock[4].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync3|SyncBlock[3].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync3|SyncBlock[2].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync3|SyncBlock[1].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync3|SyncBlock[0].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync3 |
10 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[21].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[20].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[19].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[18].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[17].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[16].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[15].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[14].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[13].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[12].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[11].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[10].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[9].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[8].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[7].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[6].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[5].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[4].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[3].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[2].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[1].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2|SyncBlock[0].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync2 |
24 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync1|SyncBlock[3].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync1|SyncBlock[2].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync1|SyncBlock[1].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync1|SyncBlock[0].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync1 |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[19].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[18].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[17].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[16].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[15].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[14].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[13].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[12].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[11].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[10].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[9].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[8].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[7].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[6].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[5].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[4].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[3].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[2].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[1].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0|SyncBlock[0].mISync |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mSlpSync0 |
22 |
0 |
0 |
0 |
20 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mTogglew1SCE |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mTogglew20mSCE |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mToggle250mSCE |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mClkDivTree|m20mSCE |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mClkDivTree|m1SCE |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mClkDivTree|m250mSCE |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mClkDivTree|m1mSCE |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mClkDivTree|m500uSCE |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mClkDivTree|m50uSCE |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mClkDivTree|m10uSCE |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mClkDivTree|m5uSCE |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mClkDivTree|m1uSCE |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mClkDivTree |
2 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main|mReset |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_common_core|mWilson_City_Main |
85 |
1 |
2 |
1 |
72 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
| u_common_core |
85 |
0 |
0 |
0 |
71 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
| u_pfr_sys_clocks_reset|u_reset_sync_spi_clk |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_pfr_sys_clocks_reset|u_reset_sync_sys_clk |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_pfr_sys_clocks_reset|u_reset_sync_clk2M |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_pfr_sys_clocks_reset|u_reset_sync_clk50M |
5 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u_pfr_sys_clocks_reset|u_sys_pll_ip|altpll_component|auto_generated |
3 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_pfr_sys_clocks_reset|u_sys_pll_ip |
2 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u_pfr_sys_clocks_reset |
2 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |