
State Machine - |pfr_top|pfr_core:u_core|spi_control:u_spi_control|spi_master_spi_master:spi_master_inst|spi_master_spi_master_qspi_inf_inst:qspi_inf_inst|state
Name state.ST_DEASSERT_CS_DLY state.ST_DEASSERT_CS state.ST_STOP_CLK state.ST_RECEIVE state.ST_DUMMY_CYCLES state.ST_SEND state.ST_ASSERT_CS state.ST_START_CLK state.ST_ASSERT_CS_DLY state.ST_IDLE 
state.ST_IDLE 0 0 0 0 0 0 0 0 0 0 
state.ST_ASSERT_CS_DLY 0 0 0 0 0 0 0 0 1 1 
state.ST_START_CLK 0 0 0 0 0 0 0 1 0 1 
state.ST_ASSERT_CS 0 0 0 0 0 0 1 0 0 1 
state.ST_SEND 0 0 0 0 0 1 0 0 0 1 
state.ST_DUMMY_CYCLES 0 0 0 0 1 0 0 0 0 1 
state.ST_RECEIVE 0 0 0 1 0 0 0 0 0 1 
state.ST_STOP_CLK 0 0 1 0 0 0 0 0 0 1 
state.ST_DEASSERT_CS 0 1 0 0 0 0 0 0 0 1 
state.ST_DEASSERT_CS_DLY 1 0 0 0 0 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|spi_control:u_spi_control|spi_master_spi_master:spi_master_inst|intel_generic_serial_flash_interface_cmd:serial_flash_inf_cmd_gen_inst|state
Name state.ST_COMPLETE state.ST_SEND_DUMMY_RSP state.ST_WAIT_BUFFER state.ST_WAIT_RSP state.ST_SEND_DATA state.ST_SEND_ADDR state.ST_SEND_OPCODE state.ST_IDLE 
state.ST_IDLE 0 0 0 0 0 0 0 0 
state.ST_SEND_OPCODE 0 0 0 0 0 0 1 1 
state.ST_SEND_ADDR 0 0 0 0 0 1 0 1 
state.ST_SEND_DATA 0 0 0 0 1 0 0 1 
state.ST_WAIT_RSP 0 0 0 1 0 0 0 1 
state.ST_WAIT_BUFFER 0 0 1 0 0 0 0 1 
state.ST_SEND_DUMMY_RSP 0 1 0 0 0 0 0 1 
state.ST_COMPLETE 1 0 0 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|spi_control:u_spi_control|spi_master_spi_master:spi_master_inst|spi_master_spi_master_xip_controller:xip_controller|current_state
Name current_state.STATE_COMPLETE current_state.STATE_READ_DATA current_state.STATE_READ_CMD current_state.STATE_READ_NVCR_RSP current_state.STATE_READ_NVCR_CMD current_state.STATE_POLL_RSP current_state.STATE_POLL_CMD current_state.STATE_WR_DATA current_state.STATE_WR_CMD current_state.STATE_WRENABLE_RSP current_state.STATE_WRENABLE_CMD current_state.STATE_STATUS_RSP current_state.STATE_STATUS_CMD current_state.STATE_IDLE 
current_state.STATE_IDLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
current_state.STATE_STATUS_CMD 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
current_state.STATE_STATUS_RSP 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
current_state.STATE_WRENABLE_CMD 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
current_state.STATE_WRENABLE_RSP 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
current_state.STATE_WR_CMD 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
current_state.STATE_WR_DATA 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
current_state.STATE_POLL_CMD 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
current_state.STATE_POLL_RSP 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
current_state.STATE_READ_NVCR_CMD 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
current_state.STATE_READ_NVCR_RSP 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_READ_CMD 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_READ_DATA 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_COMPLETE 1 0 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|spi_control:u_spi_control|spi_master_spi_master:spi_master_inst|intel_generic_serial_flash_interface_csr:csr_controller|state
Name state.ST_WAIT_RSP state.ST_SEND_DATA_1 state.ST_SEND_DATA_0 state.ST_SEND_HEADER state.ST_IDLE 
state.ST_IDLE 0 0 0 0 0 
state.ST_SEND_HEADER 0 0 0 1 1 
state.ST_SEND_DATA_0 0 0 1 0 1 
state.ST_SEND_DATA_1 0 1 0 0 1 
state.ST_WAIT_RSP 1 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|rfnvram_smbus_master:u_rfnvram_master|i2c_master:u0|altera_avalon_i2c_condt_gen:u_condt_gen|stop_state
Name stop_state.STOP_SETUP stop_state.STOP_SCL_LOW stop_state.STOP_LOAD stop_state.STOP_IDLE stop_state.STOP_DONE 
stop_state.STOP_IDLE 0 0 0 0 0 
stop_state.STOP_LOAD 0 0 1 1 0 
stop_state.STOP_SCL_LOW 0 1 0 1 0 
stop_state.STOP_SETUP 1 0 0 1 0 
stop_state.STOP_DONE 0 0 0 1 1 

State Machine - |pfr_top|pfr_core:u_core|rfnvram_smbus_master:u_rfnvram_master|i2c_master:u0|altera_avalon_i2c_condt_gen:u_condt_gen|restart_state
Name restart_state.RESTART_DONE restart_state.RESTART_HOLD restart_state.RESTART_SETUP restart_state.RESTART_SCL_LOW restart_state.RESTART_LOAD restart_state.RESTART_IDLE 
restart_state.RESTART_IDLE 0 0 0 0 0 0 
restart_state.RESTART_LOAD 0 0 0 0 1 1 
restart_state.RESTART_SCL_LOW 0 0 0 1 0 1 
restart_state.RESTART_SETUP 0 0 1 0 0 1 
restart_state.RESTART_HOLD 0 1 0 0 0 1 
restart_state.RESTART_DONE 1 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|rfnvram_smbus_master:u_rfnvram_master|i2c_master:u0|altera_avalon_i2c_condt_gen:u_condt_gen|start_state
Name start_state.START_DONE start_state.START_HOLD start_state.START_LOAD start_state.START_IDLE 
start_state.START_IDLE 0 0 0 0 
start_state.START_LOAD 0 0 1 1 
start_state.START_HOLD 0 1 0 1 
start_state.START_DONE 1 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|rfnvram_smbus_master:u_rfnvram_master|i2c_master:u0|altera_avalon_i2c_condt_det:u_condt_det|bus_state
Name bus_state.BUS_COUNTING bus_state.BUS_LOAD_CNT bus_state.BUS_BUSY bus_state.BUS_IDLE 
bus_state.BUS_IDLE 0 0 0 0 
bus_state.BUS_BUSY 0 0 1 1 
bus_state.BUS_LOAD_CNT 0 1 0 1 
bus_state.BUS_COUNTING 1 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|rfnvram_smbus_master:u_rfnvram_master|i2c_master:u0|altera_avalon_i2c_txshifter:u_txshifter|tx_shiftfsm_state
Name tx_shiftfsm_state.TX_DONE tx_shiftfsm_state.TX_CLK_HOLD tx_shiftfsm_state.TX_CLK_HIGH tx_shiftfsm_state.TX_CLK_LOW tx_shiftfsm_state.TX_CLK_LOAD tx_shiftfsm_state.TX_IDLE 
tx_shiftfsm_state.TX_IDLE 0 0 0 0 0 0 
tx_shiftfsm_state.TX_CLK_LOAD 0 0 0 0 1 1 
tx_shiftfsm_state.TX_CLK_LOW 0 0 0 1 0 1 
tx_shiftfsm_state.TX_CLK_HIGH 0 0 1 0 0 1 
tx_shiftfsm_state.TX_CLK_HOLD 0 1 0 0 0 1 
tx_shiftfsm_state.TX_DONE 1 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|rfnvram_smbus_master:u_rfnvram_master|i2c_master:u0|altera_avalon_i2c_rxshifter:u_rxshifter|rx_shiftfsm_state
Name rx_shiftfsm_state.RX_DONE rx_shiftfsm_state.RX_HOLD rx_shiftfsm_state.RX_CLK_HIGH rx_shiftfsm_state.RX_CLK_LOW rx_shiftfsm_state.RX_CLK_LOAD rx_shiftfsm_state.IDLE 
rx_shiftfsm_state.IDLE 0 0 0 0 0 0 
rx_shiftfsm_state.RX_CLK_LOAD 0 0 0 0 1 1 
rx_shiftfsm_state.RX_CLK_LOW 0 0 0 1 0 1 
rx_shiftfsm_state.RX_CLK_HIGH 0 0 1 0 0 1 
rx_shiftfsm_state.RX_HOLD 0 1 0 0 0 1 
rx_shiftfsm_state.RX_DONE 1 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|rfnvram_smbus_master:u_rfnvram_master|i2c_master:u0|altera_avalon_i2c_mstfsm:u_mstfsm|mst_fsm_state
Name mst_fsm_state.PRE_IDLE mst_fsm_state.GEN_STOP mst_fsm_state.BUS_HOLD mst_fsm_state.GEN_RESTART_7BIT mst_fsm_state.GEN_7BIT_ADDR mst_fsm_state.RX_BYTE mst_fsm_state.TX_BYTE mst_fsm_state.POP_TX_FIFO mst_fsm_state.GEN_START mst_fsm_state.PRE_START mst_fsm_state.IDLE 
mst_fsm_state.IDLE 0 0 0 0 0 0 0 0 0 0 0 
mst_fsm_state.PRE_START 0 0 0 0 0 0 0 0 0 1 1 
mst_fsm_state.GEN_START 0 0 0 0 0 0 0 0 1 0 1 
mst_fsm_state.POP_TX_FIFO 0 0 0 0 0 0 0 1 0 0 1 
mst_fsm_state.TX_BYTE 0 0 0 0 0 0 1 0 0 0 1 
mst_fsm_state.RX_BYTE 0 0 0 0 0 1 0 0 0 0 1 
mst_fsm_state.GEN_7BIT_ADDR 0 0 0 0 1 0 0 0 0 0 1 
mst_fsm_state.GEN_RESTART_7BIT 0 0 0 1 0 0 0 0 0 0 1 
mst_fsm_state.BUS_HOLD 0 0 1 0 0 0 0 0 0 0 1 
mst_fsm_state.GEN_STOP 0 1 0 0 0 0 0 0 0 0 1 
mst_fsm_state.PRE_IDLE 1 0 0 0 0 0 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|smbus_mailbox:u_smbus_mailbox|i2c_slave:bmc_slave|altr_i2c_rxshifter:i_altr_i2c_rxshifter|rx_shiftfsm_state
Name rx_shiftfsm_state.RX_DONE rx_shiftfsm_state.RX_SLV_SHIFT rx_shiftfsm_state.RX_HOLD rx_shiftfsm_state.RX_CLK_HIGH rx_shiftfsm_state.RX_CLK_LOW rx_shiftfsm_state.RX_CLK_LOAD rx_shiftfsm_state.IDLE 
rx_shiftfsm_state.IDLE 0 0 0 0 0 0 0 
rx_shiftfsm_state.RX_CLK_LOAD 0 0 0 0 0 1 1 
rx_shiftfsm_state.RX_CLK_LOW 0 0 0 0 1 0 1 
rx_shiftfsm_state.RX_CLK_HIGH 0 0 0 1 0 0 1 
rx_shiftfsm_state.RX_HOLD 0 0 1 0 0 0 1 
rx_shiftfsm_state.RX_SLV_SHIFT 0 1 0 0 0 0 1 
rx_shiftfsm_state.RX_DONE 1 0 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|smbus_mailbox:u_smbus_mailbox|i2c_slave:bmc_slave|altr_i2c_txshifter:i_altr_i2c_txshifter|tx_shiftfsm_state
Name tx_shiftfsm_state.TX_DONE tx_shiftfsm_state.TX_SLV_SHIFT tx_shiftfsm_state.TX_CLK_HOLD tx_shiftfsm_state.TX_CLK_HIGH tx_shiftfsm_state.TX_CLK_LOW tx_shiftfsm_state.TX_CLK_LOAD tx_shiftfsm_state.TX_IDLE 
tx_shiftfsm_state.TX_IDLE 0 0 0 0 0 0 0 
tx_shiftfsm_state.TX_CLK_LOAD 0 0 0 0 0 1 1 
tx_shiftfsm_state.TX_CLK_LOW 0 0 0 0 1 0 1 
tx_shiftfsm_state.TX_CLK_HIGH 0 0 0 1 0 0 1 
tx_shiftfsm_state.TX_CLK_HOLD 0 0 1 0 0 0 1 
tx_shiftfsm_state.TX_SLV_SHIFT 0 1 0 0 0 0 1 
tx_shiftfsm_state.TX_DONE 1 0 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|smbus_mailbox:u_smbus_mailbox|i2c_slave:bmc_slave|altr_i2c_avl_mst_intf_gen:i_altr_i2c_avl_mst_intf_gen|fsm_state
Name fsm_state.RDDATABYTE fsm_state.ISSUE_READ fsm_state.SPLIT_WRITE fsm_state.WRITE_COMPLETE fsm_state.NEXT_WRITE fsm_state.ISSUE_WRITE fsm_state.WRDATABYTE fsm_state.ASSIGN_WRADDR fsm_state.ASSIGN_RDADDR fsm_state.WORDADDRBYTE_4 fsm_state.WORDADDRBYTE_3 fsm_state.WORDADDRBYTE_2 fsm_state.WORDADDRBYTE_1 fsm_state.IDLE 
fsm_state.IDLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
fsm_state.WORDADDRBYTE_1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
fsm_state.WORDADDRBYTE_2 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
fsm_state.WORDADDRBYTE_3 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
fsm_state.WORDADDRBYTE_4 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
fsm_state.ASSIGN_RDADDR 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
fsm_state.ASSIGN_WRADDR 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
fsm_state.WRDATABYTE 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
fsm_state.ISSUE_WRITE 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
fsm_state.NEXT_WRITE 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
fsm_state.WRITE_COMPLETE 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
fsm_state.SPLIT_WRITE 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
fsm_state.ISSUE_READ 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
fsm_state.RDDATABYTE 1 0 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|smbus_mailbox:u_smbus_mailbox|i2c_slave:bmc_slave|altr_i2c_slvfsm:i_altr_i2c_slvfsm|slv_fsm_state
Name slv_fsm_state.TX_LOOP slv_fsm_state.WAIT_DATA slv_fsm_state.RX_LOOP slv_fsm_state.RX_10BIT_2_ADDR slv_fsm_state.RX_1BYTE slv_fsm_state.IDLE 
slv_fsm_state.IDLE 0 0 0 0 0 0 
slv_fsm_state.RX_1BYTE 0 0 0 0 1 1 
slv_fsm_state.RX_10BIT_2_ADDR 0 0 0 1 0 1 
slv_fsm_state.RX_LOOP 0 0 1 0 0 1 
slv_fsm_state.WAIT_DATA 0 1 0 0 0 1 
slv_fsm_state.TX_LOOP 1 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|smbus_mailbox:u_smbus_mailbox|i2c_slave:bmc_slave|altr_i2c_condt_det:i_altr_i2c_condt_det|bus_state
Name bus_state.BUS_COUNTING bus_state.BUS_LOAD_CNT bus_state.BUS_BUSY bus_state.BUS_IDLE 
bus_state.BUS_IDLE 0 0 0 0 
bus_state.BUS_BUSY 0 0 1 1 
bus_state.BUS_LOAD_CNT 0 1 0 1 
bus_state.BUS_COUNTING 1 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|smbus_mailbox:u_smbus_mailbox|i2c_slave:pch_slave|altr_i2c_rxshifter:i_altr_i2c_rxshifter|rx_shiftfsm_state
Name rx_shiftfsm_state.RX_DONE rx_shiftfsm_state.RX_SLV_SHIFT rx_shiftfsm_state.RX_HOLD rx_shiftfsm_state.RX_CLK_HIGH rx_shiftfsm_state.RX_CLK_LOW rx_shiftfsm_state.RX_CLK_LOAD rx_shiftfsm_state.IDLE 
rx_shiftfsm_state.IDLE 0 0 0 0 0 0 0 
rx_shiftfsm_state.RX_CLK_LOAD 0 0 0 0 0 1 1 
rx_shiftfsm_state.RX_CLK_LOW 0 0 0 0 1 0 1 
rx_shiftfsm_state.RX_CLK_HIGH 0 0 0 1 0 0 1 
rx_shiftfsm_state.RX_HOLD 0 0 1 0 0 0 1 
rx_shiftfsm_state.RX_SLV_SHIFT 0 1 0 0 0 0 1 
rx_shiftfsm_state.RX_DONE 1 0 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|smbus_mailbox:u_smbus_mailbox|i2c_slave:pch_slave|altr_i2c_txshifter:i_altr_i2c_txshifter|tx_shiftfsm_state
Name tx_shiftfsm_state.TX_DONE tx_shiftfsm_state.TX_SLV_SHIFT tx_shiftfsm_state.TX_CLK_HOLD tx_shiftfsm_state.TX_CLK_HIGH tx_shiftfsm_state.TX_CLK_LOW tx_shiftfsm_state.TX_CLK_LOAD tx_shiftfsm_state.TX_IDLE 
tx_shiftfsm_state.TX_IDLE 0 0 0 0 0 0 0 
tx_shiftfsm_state.TX_CLK_LOAD 0 0 0 0 0 1 1 
tx_shiftfsm_state.TX_CLK_LOW 0 0 0 0 1 0 1 
tx_shiftfsm_state.TX_CLK_HIGH 0 0 0 1 0 0 1 
tx_shiftfsm_state.TX_CLK_HOLD 0 0 1 0 0 0 1 
tx_shiftfsm_state.TX_SLV_SHIFT 0 1 0 0 0 0 1 
tx_shiftfsm_state.TX_DONE 1 0 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|smbus_mailbox:u_smbus_mailbox|i2c_slave:pch_slave|altr_i2c_avl_mst_intf_gen:i_altr_i2c_avl_mst_intf_gen|fsm_state
Name fsm_state.RDDATABYTE fsm_state.ISSUE_READ fsm_state.SPLIT_WRITE fsm_state.WRITE_COMPLETE fsm_state.NEXT_WRITE fsm_state.ISSUE_WRITE fsm_state.WRDATABYTE fsm_state.ASSIGN_WRADDR fsm_state.ASSIGN_RDADDR fsm_state.WORDADDRBYTE_4 fsm_state.WORDADDRBYTE_3 fsm_state.WORDADDRBYTE_2 fsm_state.WORDADDRBYTE_1 fsm_state.IDLE 
fsm_state.IDLE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
fsm_state.WORDADDRBYTE_1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
fsm_state.WORDADDRBYTE_2 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
fsm_state.WORDADDRBYTE_3 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
fsm_state.WORDADDRBYTE_4 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
fsm_state.ASSIGN_RDADDR 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
fsm_state.ASSIGN_WRADDR 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
fsm_state.WRDATABYTE 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
fsm_state.ISSUE_WRITE 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
fsm_state.NEXT_WRITE 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
fsm_state.WRITE_COMPLETE 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
fsm_state.SPLIT_WRITE 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
fsm_state.ISSUE_READ 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
fsm_state.RDDATABYTE 1 0 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|smbus_mailbox:u_smbus_mailbox|i2c_slave:pch_slave|altr_i2c_slvfsm:i_altr_i2c_slvfsm|slv_fsm_state
Name slv_fsm_state.TX_LOOP slv_fsm_state.WAIT_DATA slv_fsm_state.RX_LOOP slv_fsm_state.RX_10BIT_2_ADDR slv_fsm_state.RX_1BYTE slv_fsm_state.IDLE 
slv_fsm_state.IDLE 0 0 0 0 0 0 
slv_fsm_state.RX_1BYTE 0 0 0 0 1 1 
slv_fsm_state.RX_10BIT_2_ADDR 0 0 0 1 0 1 
slv_fsm_state.RX_LOOP 0 0 1 0 0 1 
slv_fsm_state.WAIT_DATA 0 1 0 0 0 1 
slv_fsm_state.TX_LOOP 1 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|smbus_mailbox:u_smbus_mailbox|i2c_slave:pch_slave|altr_i2c_condt_det:i_altr_i2c_condt_det|bus_state
Name bus_state.BUS_COUNTING bus_state.BUS_LOAD_CNT bus_state.BUS_BUSY bus_state.BUS_IDLE 
bus_state.BUS_IDLE 0 0 0 0 
bus_state.BUS_BUSY 0 0 1 1 
bus_state.BUS_LOAD_CNT 0 1 0 1 
bus_state.BUS_COUNTING 1 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|crypto256_top:u_crypto|ecdsa256_top:u_ecdsa|multr_all_256x256:i_ma256|in_t2_sel
Name in_t2_sel.01 in_t2_sel.11 in_t2_sel.00 
in_t2_sel.00 0 0 0 
in_t2_sel.01 1 0 1 
in_t2_sel.11 0 1 1 

State Machine - |pfr_top|pfr_core:u_core|pfr_sys:u_pfr_sys|altera_onchip_flash:u_ufm|altera_onchip_flash_avmm_data_controller:avmm_data_controller|avmm_read_valid_state
Name avmm_read_valid_state.READ_VALID_IDLE avmm_read_valid_state.READ_VALID_PRE_READING avmm_read_valid_state.READ_VALID_READING 
avmm_read_valid_state.READ_VALID_IDLE 0 0 0 
avmm_read_valid_state.READ_VALID_READING 1 0 1 
avmm_read_valid_state.READ_VALID_PRE_READING 1 1 0 

State Machine - |pfr_top|pfr_core:u_core|pfr_sys:u_pfr_sys|altera_onchip_flash:u_ufm|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_state
Name read_state.READ_STATE_PULSE_SE read_state.READ_STATE_CLEAR read_state.READ_STATE_FINAL read_state.READ_STATE_READY read_state.READ_STATE_DUMMY read_state.READ_STATE_SETUP read_state.READ_STATE_ADDR read_state.READ_STATE_IDLE 
read_state.READ_STATE_IDLE 0 0 0 0 0 0 0 0 
read_state.READ_STATE_ADDR 0 0 0 0 0 0 1 1 
read_state.READ_STATE_SETUP 0 0 0 0 0 1 0 1 
read_state.READ_STATE_DUMMY 0 0 0 0 1 0 0 1 
read_state.READ_STATE_READY 0 0 0 1 0 0 0 1 
read_state.READ_STATE_FINAL 0 0 1 0 0 0 0 1 
read_state.READ_STATE_CLEAR 0 1 0 0 0 0 0 1 
read_state.READ_STATE_PULSE_SE 1 0 0 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|pfr_sys:u_pfr_sys|altera_onchip_flash:u_ufm|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state
Name erase_state.ERASE_STATE_ERROR erase_state.ERASE_STATE_RESET erase_state.ERASE_STATE_WAIT_DONE erase_state.ERASE_STATE_WAIT_BUSY erase_state.ERASE_STATE_ADDR erase_state.ERASE_STATE_IDLE 
erase_state.ERASE_STATE_IDLE 0 0 0 0 0 0 
erase_state.ERASE_STATE_ADDR 0 0 0 0 1 1 
erase_state.ERASE_STATE_WAIT_BUSY 0 0 0 1 0 1 
erase_state.ERASE_STATE_WAIT_DONE 0 0 1 0 0 1 
erase_state.ERASE_STATE_RESET 0 1 0 0 0 1 
erase_state.ERASE_STATE_ERROR 1 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|pfr_sys:u_pfr_sys|altera_onchip_flash:u_ufm|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_state
Name write_state.WRITE_STATE_ERROR write_state.WRITE_STATE_RESET write_state.WRITE_STATE_WAIT_DONE write_state.WRITE_STATE_WAIT_BUSY write_state.WRITE_STATE_WRITE write_state.WRITE_STATE_ADDR write_state.WRITE_STATE_IDLE 
write_state.WRITE_STATE_IDLE 0 0 0 0 0 0 0 
write_state.WRITE_STATE_ADDR 0 0 0 0 0 1 1 
write_state.WRITE_STATE_WRITE 0 0 0 0 1 0 1 
write_state.WRITE_STATE_WAIT_BUSY 0 0 0 1 0 0 1 
write_state.WRITE_STATE_WAIT_DONE 0 0 1 0 0 0 1 
write_state.WRITE_STATE_RESET 0 1 0 0 0 0 1 
write_state.WRITE_STATE_ERROR 1 0 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|pfr_sys:u_pfr_sys|pfr_sys_u_nios:u_nios|pfr_sys_u_nios_cpu:cpu|pfr_sys_u_nios_cpu_nios2_oci:the_pfr_sys_u_nios_cpu_nios2_oci|pfr_sys_u_nios_cpu_debug_slave_wrapper:the_pfr_sys_u_nios_cpu_debug_slave_wrapper|pfr_sys_u_nios_cpu_debug_slave_tck:the_pfr_sys_u_nios_cpu_debug_slave_tck|DRsize
Name DRsize.101 DRsize.100 DRsize.011 DRsize.010 DRsize.001 DRsize.000 
DRsize.000 0 0 0 0 0 0 
DRsize.001 0 0 0 0 1 1 
DRsize.010 0 0 0 1 0 1 
DRsize.011 0 0 1 0 0 1 
DRsize.100 0 1 0 0 0 1 
DRsize.101 1 0 0 0 0 1 

State Machine - |pfr_top|pfr_core:u_core|pfr_sys:u_pfr_sys|altera_dual_boot:u_dual_config|alt_dual_boot_avmm:alt_dual_boot_avmm_comp|alt_dual_boot:alt_dual_boot|current_state
Name current_state.STATE_CLR_BUSY current_state.STATE_CLR_END current_state.STATE_CLR_WR_INREG current_state.STATE_CLR_RD_INREG current_state.STATE_CLR_RD_APP2 current_state.STATE_CLR_RD_APP1 current_state.STATE_CLR_RD_WD current_state.STATE_CLR current_state.STATE_WRITE_UPDATE current_state.STATE_WRITE current_state.STATE_WRITE_SETUP current_state.STATE_READ_UPDATE current_state.STATE_READ_EXTRA current_state.STATE_READ current_state.STATE_READ_CAPTURE current_state.STATE_READ_DUMMY current_state.STATE_READ_WRITE current_state.STATE_READ_SETUP current_state.STATE_SAME current_state.STATE_INIT 
current_state.STATE_INIT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
current_state.STATE_SAME 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
current_state.STATE_READ_SETUP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
current_state.STATE_READ_WRITE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
current_state.STATE_READ_DUMMY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
current_state.STATE_READ_CAPTURE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
current_state.STATE_READ 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
current_state.STATE_READ_EXTRA 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
current_state.STATE_READ_UPDATE 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
current_state.STATE_WRITE_SETUP 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
current_state.STATE_WRITE 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_WRITE_UPDATE 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_CLR 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_CLR_RD_WD 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_CLR_RD_APP1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_CLR_RD_APP2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_CLR_RD_INREG 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_CLR_WR_INREG 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_CLR_END 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
current_state.STATE_CLR_BUSY 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |pfr_top|Wilson_City_Main_wrapper:u_common_core|Wilson_City_Main:mWilson_City_Main|EventLogger:mEventLogger|rvState_q
Name rvState_q.WRITE_TICKS_STATE1 rvState_q.WRITE_TICKS_STATE0 rvState_q.SET_TICKS_STATE rvState_q.WRITE_EVENT_STATE0 rvState_q.SET_EVENT_STATE rvState_q.SAMPLE_STATE rvState_q.IDLE_STATE 
rvState_q.IDLE_STATE 0 0 0 0 0 0 0 
rvState_q.SAMPLE_STATE 0 0 0 0 0 1 1 
rvState_q.SET_EVENT_STATE 0 0 0 0 1 0 1 
rvState_q.WRITE_EVENT_STATE0 0 0 0 1 0 0 1 
rvState_q.SET_TICKS_STATE 0 0 1 0 0 0 1 
rvState_q.WRITE_TICKS_STATE0 0 1 0 0 0 0 1 
rvState_q.WRITE_TICKS_STATE1 1 0 0 0 0 0 1 

State Machine - |pfr_top|Wilson_City_Main_wrapper:u_common_core|Wilson_City_Main:mWilson_City_Main|IICRegs:mIICRegs|IICRegsController:mIICRegsController|rvState_q
Name rvState_q.REG_CNTROLLER_WAIT_ACCESS_STATE rvState_q.REG_CNTROLLER_RX_DATA_STATE rvState_q.REG_CNTROLLER_TX_DATA_STATE rvState_q.REG_CNTROLLER_ADDRESS_STATE1 rvState_q.REG_CNTROLLER_ADDRESS_STATE0 rvState_q.REG_CNTROLLER_WAIT_ADDRESS_MATCH_STATE rvState_q.REG_CNTROLLER_IDLE_STATE 
rvState_q.REG_CNTROLLER_IDLE_STATE 0 0 0 0 0 0 0 
rvState_q.REG_CNTROLLER_WAIT_ADDRESS_MATCH_STATE 0 0 0 0 0 1 1 
rvState_q.REG_CNTROLLER_ADDRESS_STATE0 0 0 0 0 1 0 1 
rvState_q.REG_CNTROLLER_ADDRESS_STATE1 0 0 0 1 0 0 1 
rvState_q.REG_CNTROLLER_TX_DATA_STATE 0 0 1 0 0 0 1 
rvState_q.REG_CNTROLLER_RX_DATA_STATE 0 1 0 0 0 0 1 
rvState_q.REG_CNTROLLER_WAIT_ACCESS_STATE 1 0 0 0 0 0 1 

State Machine - |pfr_top|Wilson_City_Main_wrapper:u_common_core|Wilson_City_Main:mWilson_City_Main|IICRegs:mIICRegs|IICRegsController:mIICRegsController|IICSlave:mIICSlave|rvState_q
Name rvState_q.IDLE_STATE rvState_q.RX_DATA_STATE rvState_q.TX_DATA_STATE rvState_q.ADDRESS_CAPTURE_STATE rvState_q.WAIT_START_STATE 
rvState_q.IDLE_STATE 0 0 0 0 0 
rvState_q.WAIT_START_STATE 1 0 0 0 1 
rvState_q.ADDRESS_CAPTURE_STATE 1 0 0 1 0 
rvState_q.TX_DATA_STATE 1 0 1 0 0 
rvState_q.RX_DATA_STATE 1 1 0 0 0 

State Machine - |pfr_top|Wilson_City_Main_wrapper:u_common_core|Wilson_City_Main:mWilson_City_Main|caterr:mCaterr|rCurrSt
Name rCurrSt.STATE_WAIT_IDLE rCurrSt.STATE_PULSE_INPRG rCurrSt.STATE_DELAY_INPRG rCurrSt.STATE_IDLE 
rCurrSt.STATE_IDLE 0 0 0 0 
rCurrSt.STATE_DELAY_INPRG 0 0 1 1 
rCurrSt.STATE_PULSE_INPRG 0 1 0 1 
rCurrSt.STATE_WAIT_IDLE 1 0 0 1 

State Machine - |pfr_top|Wilson_City_Main_wrapper:u_common_core|Wilson_City_Main:mWilson_City_Main|led_control:mled_control|rCurrLedSt
Name rCurrLedSt.ST_FANFLT_LED rCurrLedSt.ST_POSTSEG2_LED_DECAY rCurrLedSt.ST_POSTSEG2_LED rCurrLedSt.ST_POSTSEG1_LED_DECAY rCurrLedSt.ST_POSTSEG1_LED rCurrLedSt.ST_DIMMFAULT3_LED rCurrLedSt.ST_DIMMFAULT2_LED rCurrLedSt.ST_DIMMFAULT1_LED rCurrLedSt.ST_DIMMFAULT0_LED rCurrLedSt.ST_POST_LED 
rCurrLedSt.ST_POST_LED 0 0 0 0 0 0 0 0 0 0 
rCurrLedSt.ST_DIMMFAULT0_LED 0 0 0 0 0 0 0 0 1 1 
rCurrLedSt.ST_DIMMFAULT1_LED 0 0 0 0 0 0 0 1 0 1 
rCurrLedSt.ST_DIMMFAULT2_LED 0 0 0 0 0 0 1 0 0 1 
rCurrLedSt.ST_DIMMFAULT3_LED 0 0 0 0 0 1 0 0 0 1 
rCurrLedSt.ST_POSTSEG1_LED 0 0 0 0 1 0 0 0 0 1 
rCurrLedSt.ST_POSTSEG1_LED_DECAY 0 0 0 1 0 0 0 0 0 1 
rCurrLedSt.ST_POSTSEG2_LED 0 0 1 0 0 0 0 0 0 1 
rCurrLedSt.ST_POSTSEG2_LED_DECAY 0 1 0 0 0 0 0 0 0 1 
rCurrLedSt.ST_FANFLT_LED 1 0 0 0 0 0 0 0 0 1 
