---

u_crypto_avmm_bridge

basic_avmm_bridge v1.0

Parameters ADDRESS_WIDTH 7 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

u_dual_config

altera_dual_boot v18.1

Parameters INTENDED_DEVICE_FAMILY MAX10FPGA CLOCK_FREQUENCY 80.0 CONFIG_CYCLE 29 RESET_TIMER_CYCLE 41 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

u_global_state_reg

altera_avalon_pio v18.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 32 clockRate 50000000 derived_has_tri false derived_has_out true derived_has_in false derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 32 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 50000000 HAS_IN 0 HAS_OUT 1 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0

---

u_gpi_1

altera_avalon_pio v18.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Input edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 32 clockRate 50000000 derived_has_tri false derived_has_out false derived_has_in true derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 32 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 50000000 HAS_IN 1 HAS_OUT 0 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0

---

u_gpo_1

altera_avalon_pio v18.1

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 32 clockRate 50000000 derived_has_tri false derived_has_out true derived_has_in false derived_do_test_bench_wiring false derived_capture false derived_edge_type NONE derived_irq_type NONE derived_has_irq false deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 CAPTURE 0 DATA_WIDTH 32 DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0 EDGE_TYPE NONE FREQ 50000000 HAS_IN 0 HAS_OUT 1 HAS_TRI 0 IRQ_TYPE NONE RESET_VALUE 0

---

u_mailbox_avmm_bridge

basic_avmm_bridge_rdv v1.0

Parameters ADDRESS_WIDTH 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

---

u_nios

altera_nios2_gen2 v18.1

Parameters tmr_enabled false setting_disable_tmr_inj false setting_showUnpublishedSettings false setting_showInternalSettings false setting_preciseIllegalMemAccessException false setting_exportPCB false setting_exportdebuginfo false setting_clearXBitsLDNonBypass true setting_bigEndian false setting_export_large_RAMs false setting_asic_enabled false register_file_por false setting_asic_synopsys_translate_on_off false setting_asic_third_party_synthesis false setting_asic_add_scan_mode_input false setting_oci_version 1 setting_fast_register_read false setting_exportHostDebugPort false setting_oci_export_jtag_signals false setting_avalonDebugPortPresent false setting_alwaysEncrypt true io_regionbase 0 io_regionsize 0 setting_support31bitdcachebypass false setting_activateTrace true setting_allow_break_inst false setting_activateTestEndChecker false setting_ecc_sim_test_ports false setting_disableocitrace false setting_activateMonitors true setting_HDLSimCachesCleared true setting_HBreakTest false setting_breakslaveoveride false mpu_useLimit false mpu_enabled false mmu_enabled false mmu_autoAssignTlbPtrSz true cpuReset false resetrequest_enabled false setting_removeRAMinit false setting_tmr_output_disable false setting_shadowRegisterSets 0 mpu_numOfInstRegion 8 mpu_numOfDataRegion 8 mmu_TLBMissExcOffset 0 resetOffset 262144 exceptionOffset 262176 cpuID 0 breakOffset 32 userDefinedSettings tracefilename resetSlave u_ufm.data mmu_TLBMissExcSlave None exceptionSlave u_ufm.data breakSlave None setting_interruptControllerType Internal setting_branchpredictiontype Dynamic setting_bhtPtrSz 8 cpuArchRev 1 stratix_dspblock_shift_mul false shifterType medium_le_shift multiplierType no_mul mul_shift_choice 0 mul_32_impl 2 mul_64_impl 0 shift_rot_impl 1 dividerType no_div mpu_minInstRegionSize 12 mpu_minDataRegionSize 12 mmu_uitlbNumEntries 4 mmu_udtlbNumEntries 6 mmu_tlbPtrSz 7 mmu_tlbNumWays 16 mmu_processIDNumBits 8 impl Tiny icache_size 0 fa_cache_line 2 fa_cache_linesize 0 icache_tagramBlockType Automatic icache_ramBlockType Automatic icache_numTCIM 0 icache_burstType None dcache_bursts false dcache_victim_buf_impl ram dcache_size 0 dcache_tagramBlockType Automatic dcache_ramBlockType Automatic dcache_numTCDM 0 setting_exportvectors false setting_usedesignware false setting_ecc_present false setting_ic_ecc_present true setting_rf_ecc_present true setting_mmu_ecc_present true setting_dc_ecc_present true setting_itcm_ecc_present true setting_dtcm_ecc_present true regfile_ramBlockType Automatic ocimem_ramBlockType Automatic ocimem_ramInit false mmu_ramBlockType Automatic bht_ramBlockType Automatic cdx_enabled false mpx_enabled false debug_enabled true debug_triggerArming true debug_debugReqSignals false debug_assignJtagInstanceID false debug_jtagInstanceID 0 debug_OCIOnchipTrace _128 debug_hwbreakpoint 4 debug_datatrigger 0 debug_traceType none debug_traceStorage onchip_trace master_addr_map false instruction_master_paddr_base 0 instruction_master_paddr_size 0 flash_instruction_master_paddr_base 0 flash_instruction_master_paddr_size 0 data_master_paddr_base 0 data_master_paddr_size 0 tightly_coupled_instruction_master_0_paddr_base 0 tightly_coupled_instruction_master_0_paddr_size 0 tightly_coupled_instruction_master_1_paddr_base 0 tightly_coupled_instruction_master_1_paddr_size 0 tightly_coupled_instruction_master_2_paddr_base 0 tightly_coupled_instruction_master_2_paddr_size 0 tightly_coupled_instruction_master_3_paddr_base 0 tightly_coupled_instruction_master_3_paddr_size 0 tightly_coupled_data_master_0_paddr_base 0 tightly_coupled_data_master_0_paddr_size 0 tightly_coupled_data_master_1_paddr_base 0 tightly_coupled_data_master_1_paddr_size 0 tightly_coupled_data_master_2_paddr_base 0 tightly_coupled_data_master_2_paddr_size 0 tightly_coupled_data_master_3_paddr_base 0 tightly_coupled_data_master_3_paddr_size 0 instruction_master_high_performance_paddr_base 0 instruction_master_high_performance_paddr_size 0 data_master_high_performance_paddr_base 0 data_master_high_performance_paddr_size 0 resetAbsoluteAddr 1310720 exceptionAbsoluteAddr 1310752 breakAbsoluteAddr 10272 mmu_TLBMissExcAbsAddr 0 dcache_bursts_derived false dcache_size_derived 0 breakSlave_derived u_nios.debug_mem_slave dcache_lineSize_derived 32 setting_ioregionBypassDCache false setting_bit31BypassDCache false translate_on "synthesis translate_on" translate_off "synthesis translate_off" debug_onchiptrace false debug_offchiptrace false debug_insttrace false debug_datatrace false instAddrWidth 32 faAddrWidth 1 dataAddrWidth 32 tightlyCoupledDataMaster0AddrWidth 1 tightlyCoupledDataMaster1AddrWidth 1 tightlyCoupledDataMaster2AddrWidth 1 tightlyCoupledDataMaster3AddrWidth 1 tightlyCoupledInstructionMaster0AddrWidth 1 tightlyCoupledInstructionMaster1AddrWidth 1 tightlyCoupledInstructionMaster2AddrWidth 1 tightlyCoupledInstructionMaster3AddrWidth 1 dataMasterHighPerformanceAddrWidth 1 instructionMasterHighPerformanceAddrWidth 1 instSlaveMapParam <address-map><slave name='u_nios.debug_mem_slave' start='0x2800' end='0x3000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='u_ufm.data' start='0x100000' end='0x18C000' type='altera_onchip_flash.data' /><slave name='u_nios_ram.s1' start='0xFFFF0000' end='0xFFFF3000' type='altera_avalon_onchip_memory2.s1' /></address-map> faSlaveMapParam dataSlaveMapParam <address-map><slave name='u_timer_bank_avmm_bridge.avmm' start='0x0' end='0x2000' type='basic_avmm_bridge.avmm' /><slave name='u_nios.debug_mem_slave' start='0x2800' end='0x3000' type='altera_nios2_gen2.debug_mem_slave' /><slave name='u_mailbox_avmm_bridge.avmm' start='0x3000' end='0x3400' type='basic_avmm_bridge_rdv.avmm' /><slave name='u_relay3_avmm_bridge.avmm' start='0x3400' end='0x3800' type='basic_avmm_bridge.avmm' /><slave name='u_relay2_avmm_bridge.avmm' start='0x3800' end='0x3C00' type='basic_avmm_bridge.avmm' /><slave name='u_spi_filter_csr_avmm_bridge_0.avmm' start='0x3C00' end='0x3D00' type='basic_avmm_bridge_rdv.avmm' /><slave name='u_rfnvram_smbus_master.avmm' start='0x3D00' end='0x3D40' type='basic_avmm_bridge_rdv.avmm' /><slave name='u_dual_config.avalon' start='0x3D60' end='0x3D80' type='altera_dual_boot.avalon' /><slave name='u_gpi_1.s1' start='0x3D80' end='0x3D90' type='altera_avalon_pio.s1' /><slave name='u_gpo_1.s1' start='0x3D90' end='0x3DA0' type='altera_avalon_pio.s1' /><slave name='u_global_state_reg.s1' start='0x3DA0' end='0x3DB0' type='altera_avalon_pio.s1' /><slave name='u_ufm.csr' start='0x3DB0' end='0x3DB8' type='altera_onchip_flash.csr' /><slave name='u_spi_filter_bmc_we_avmm_bridge.avmm' start='0x4000' end='0x6000' type='basic_avmm_bridge.avmm' /><slave name='u_spi_filter_pch_we_avmm_bridge.avmm' start='0x6000' end='0x8000' type='basic_avmm_bridge.avmm' /><slave name='u_ufm.data' start='0x100000' end='0x18C000' type='altera_onchip_flash.data' /><slave name='u_relay1_avmm_bridge.avmm' start='0x200000' end='0x200400' type='basic_avmm_bridge.avmm' /><slave name='u_crypto_avmm_bridge.avmm' start='0x200800' end='0x200A00' type='basic_avmm_bridge.avmm' /><slave name='u_spi_filter_avmm_bridge.avmm' start='0x80000000' end='0x88000000' type='basic_avmm_bridge_rdv.avmm' /><slave name='u_nios_ram.s1' start='0xFFFF0000' end='0xFFFF3000' type='altera_avalon_onchip_memory2.s1' /></address-map> tightlyCoupledDataMaster0MapParam tightlyCoupledDataMaster1MapParam tightlyCoupledDataMaster2MapParam tightlyCoupledDataMaster3MapParam tightlyCoupledInstructionMaster0MapParam tightlyCoupledInstructionMaster1MapParam tightlyCoupledInstructionMaster2MapParam tightlyCoupledInstructionMaster3MapParam dataMasterHighPerformanceMapParam instructionMasterHighPerformanceMapParam clockFrequency 50000000 deviceFamilyName MAX10FPGA internalIrqMaskSystemInfo 0 customInstSlavesSystemInfo <info/> customInstSlavesSystemInfo_nios_a <info/> customInstSlavesSystemInfo_nios_b <info/> customInstSlavesSystemInfo_nios_c <info/> deviceFeaturesSystemInfo ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 AUTO_DEVICE 10M16SAU324I7G AUTO_DEVICE_SPEEDGRADE 7 AUTO_CLK_CLOCK_DOMAIN 3 AUTO_CLK_RESET_DOMAIN 3 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BIG_ENDIAN 0 BREAK_ADDR 0x00002820 CPU_ARCH_NIOS2_R1 CPU_FREQ 50000000u CPU_ID_SIZE 1 CPU_ID_VALUE 0x00000000 CPU_IMPLEMENTATION "tiny" DATA_ADDR_WIDTH 32 DCACHE_LINE_SIZE 0 DCACHE_LINE_SIZE_LOG2 0 DCACHE_SIZE 0 EXCEPTION_ADDR 0x00140020 FLASH_ACCELERATOR_LINES 0 FLASH_ACCELERATOR_LINE_SIZE 0 FLUSHDA_SUPPORTED HARDWARE_DIVIDE_PRESENT 0 HARDWARE_MULTIPLY_PRESENT 0 HARDWARE_MULX_PRESENT 0 HAS_DEBUG_CORE 1 HAS_DEBUG_STUB HAS_ILLEGAL_INSTRUCTION_EXCEPTION HAS_JMPI_INSTRUCTION ICACHE_LINE_SIZE 0 ICACHE_LINE_SIZE_LOG2 0 ICACHE_SIZE 0 INST_ADDR_WIDTH 32 OCI_VERSION 1 RESET_ADDR 0x00140000

---

u_nios_ram

altera_avalon_onchip_memory2 v18.1

Parameters allowInSystemMemoryContentEditor false blockType AUTO dataWidth 32 dataWidth2 32 dualPort false enableDiffWidth false derived_enableDiffWidth false initMemContent false initializationFileName onchip_mem.hex enPRInitMode false instanceID NONE memorySize 12288 readDuringWriteMode DONT_CARE simAllowMRAMContentsFile false simMemInitOnlyFilename 0 singleClockOperation false derived_singleClockOperation false slave1Latency 1 slave2Latency 1 useNonDefaultInitFile false copyInitFile false useShallowMemBlocks false writable true ecc_enabled false resetrequest_enabled true autoInitializationFileName pfr_sys_u_nios_ram deviceFamily MAX10FPGA deviceFeatures ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 1 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 0 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 0 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 0 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 1 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 1 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 0 HAS_BSDL_FILE_GENERATION 0 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 0 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 0 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 0 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 0 HAS_FPGA_XCHANGE_SUPPORT 0 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 0 HAS_HSSI_POWER_CALCULATOR 1 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 0 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 1 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 0 HAS_POWER_BINNING_LIMITS_DATA 1 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 0 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 0 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 1 HAS_XIBISO_WRITER_SUPPORT 0 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_JW_NEW_BINNING_PLAN 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 0 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 0 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 0 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 0 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_1P0V_IOSTD 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_NEW_BINNING_PLAN 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 0 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 1 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 0 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 derived_set_addr_width 12 derived_set_addr_width2 12 derived_set_data_width 32 derived_set_data_width2 32 derived_gui_ram_block_type Automatic derived_is_hardcopy false derived_init_file_name pfr_sys_u_nios_ram.hex generateLegacySim false

  

Software Assignments ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0 ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0 CONTENTS_INFO "" DUAL_PORT 0 GUI_RAM_BLOCK_TYPE AUTO INIT_CONTENTS_FILE pfr_sys_u_nios_ram INIT_MEM_CONTENT 0 INSTANCE_ID NONE NON_DEFAULT_INIT_FILE_ENABLED 0 RAM_BLOCK_TYPE AUTO READ_DURING_WRITE_MODE DONT_CARE SINGLE_CLOCK_OP 0 SIZE_MULTIPLE 1 SIZE_VALUE 12288 WRITABLE 1

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u_relay1_avmm_bridge

basic_avmm_bridge v1.0

Parameters ADDRESS_WIDTH 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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u_relay2_avmm_bridge

basic_avmm_bridge v1.0

Parameters ADDRESS_WIDTH 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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u_relay3_avmm_bridge

basic_avmm_bridge v1.0

Parameters ADDRESS_WIDTH 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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u_rfnvram_smbus_master

basic_avmm_bridge_rdv v1.0

Parameters ADDRESS_WIDTH 4 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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u_spi_clk

altera_clock_bridge v18.1

Parameters DERIVED_CLOCK_RATE 0 EXPLICIT_CLOCK_RATE 80000000 NUM_CLOCK_OUTPUTS 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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u_spi_clk_reset

altera_reset_bridge v18.1

Parameters ACTIVE_LOW_RESET 0 SYNCHRONOUS_EDGES deassert NUM_RESET_OUTPUTS 1 USE_RESET_REQUEST 0 AUTO_CLK_CLOCK_RATE 80000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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u_spi_filter_avmm_bridge

basic_avmm_bridge_rdv v1.0

Parameters ADDRESS_WIDTH 25 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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u_spi_filter_bmc_we_avmm_bridge

basic_avmm_bridge v1.0

Parameters ADDRESS_WIDTH 11 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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u_spi_filter_csr_avmm_bridge_0

basic_avmm_bridge_rdv v1.0

Parameters ADDRESS_WIDTH 6 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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u_spi_filter_pch_we_avmm_bridge

basic_avmm_bridge v1.0

Parameters ADDRESS_WIDTH 11 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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u_sys_clk

altera_clock_bridge v18.1

Parameters DERIVED_CLOCK_RATE 0 EXPLICIT_CLOCK_RATE 50000000 NUM_CLOCK_OUTPUTS 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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u_sys_clk_reset

altera_reset_bridge v18.1

Parameters ACTIVE_LOW_RESET 0 SYNCHRONOUS_EDGES deassert NUM_RESET_OUTPUTS 1 USE_RESET_REQUEST 0 AUTO_CLK_CLOCK_RATE 50000000 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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u_timer_bank_avmm_bridge

basic_avmm_bridge v1.0

Parameters ADDRESS_WIDTH 11 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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u_ufm

altera_onchip_flash v18.1

Parameters DATA_INTERFACE Parallel READ_BURST_MODE Incrementing READ_BURST_COUNT 2 CLOCK_FREQUENCY 100.0 CONFIGURATION_SCHEME Internal Configuration CONFIGURATION_MODE Dual Compressed Images SECTOR_ID 1,2,3,4,5 SECTOR_ACCESS_MODE Read and write,Read and write,Read and write,Read and write,Read and write SECTOR_ADDRESS_MAPPING 0x00000 - 0x03fff,0x04000 - 0x07fff,0x08000 - 0x2dfff,0x2e000 - 0x49fff,0x4a000 - 0x8bfff SECTOR_STORAGE_TYPE UFM,UFM,CFM (Image 2),CFM (Image 2),CFM (Image 1) initFlashContent false useNonDefaultInitFile true initializationFileName rom_mem.hex initializationFileNameForSim rom_mem.dat autoInitializationFileName pfr_sys_u_ufm INIT_FILENAME INIT_FILENAME_SIM DEVICE_FAMILY MAX10FPGA PART_NAME 10M16SAU324I7G AUTO_CLOCK_RATE 50000000 DEVICE_ID 16 SECTOR1_START_ADDR 0 SECTOR1_END_ADDR 4095 SECTOR2_START_ADDR 4096 SECTOR2_END_ADDR 8191 SECTOR3_START_ADDR 8192 SECTOR3_END_ADDR 47103 SECTOR4_START_ADDR 47104 SECTOR4_END_ADDR 75775 SECTOR5_START_ADDR 75776 SECTOR5_END_ADDR 143359 MIN_VALID_ADDR 0 MAX_VALID_ADDR 143359 MIN_UFM_VALID_ADDR 0 MAX_UFM_VALID_ADDR 8191 SECTOR1_MAP 1 SECTOR2_MAP 2 SECTOR3_MAP 3 SECTOR4_MAP 4 SECTOR5_MAP 5 ADDR_RANGE1_END_ADDR 143359 ADDR_RANGE2_END_ADDR 143359 ADDR_RANGE1_OFFSET 1024 ADDR_RANGE2_OFFSET 0 ADDR_RANGE3_OFFSET 0 AVMM_DATA_ADDR_WIDTH 18 AVMM_DATA_DATA_WIDTH 32 AVMM_DATA_BURSTCOUNT_WIDTH 2 SECTOR_READ_PROTECTION_MODE 0 FLASH_SEQ_READ_DATA_COUNT 4 FLASH_ADDR_ALIGNMENT_BITS 2 FLASH_READ_CYCLE_MAX_INDEX 4 FLASH_RESET_CYCLE_MAX_INDEX 12 FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX 60 FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX 17500000 FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX 15250 PARALLEL_MODE true READ_AND_WRITE_MODE true WRAPPING_BURST_MODE false IS_DUAL_BOOT True IS_ERAM_SKIP True IS_COMPRESSED_IMAGE True deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments BYTES_PER_PAGE 4096 READ_ONLY_MODE 0 SECTOR1_ENABLED 1 SECTOR1_END_ADDR 16383 SECTOR1_START_ADDR 0 SECTOR2_ENABLED 1 SECTOR2_END_ADDR 32767 SECTOR2_START_ADDR 16384 SECTOR3_ENABLED 1 SECTOR3_END_ADDR 188415 SECTOR3_START_ADDR 32768 SECTOR4_ENABLED 1 SECTOR4_END_ADDR 303103 SECTOR4_START_ADDR 188416 SECTOR5_ENABLED 1 SECTOR5_END_ADDR 573439 SECTOR5_START_ADDR 303104