#ifndef __MrcMcRegisterStructTgl2xxx_h__
#define __MrcMcRegisterStructTgl2xxx_h__
/** @file
  This file was automatically generated. Modify at your own risk.
  Note that no error checking is done in these functions so ensure that the correct values are passed.

@copyright
  Copyright (c) 2010 - 2019 Intel Corporation. All rights reserved
  This software and associated documentation (if any) is furnished
  under a license and may only be used or copied in accordance
  with the terms of the license. Except as permitted by the
  license, no part of this software or documentation may be
  reproduced, stored in a retrieval system, or transmitted in any
  form or by any means without the express written consent of
  Intel Corporation.
  This file contains an 'Intel Peripheral Driver' and is uniquely
  identified as "Intel Reference Module" and is licensed for Intel
  CPUs and chipsets under the terms of your license agreement with
  Intel or your vendor. This file may be modified by the user, subject
  to additional terms of the license agreement.

@par Specification Reference:
**/

#pragma pack(push, 1)

typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK0LANE0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK0LANE1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK0LANE2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK0LANE3_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK0LANE4_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK0LANE5_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK0LANE6_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK0LANE7_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK0LANE8_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK1LANE0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK1LANE1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK1LANE2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK1LANE3_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK1LANE4_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK1LANE5_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK1LANE6_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK1LANE7_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK1LANE8_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK2LANE0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK2LANE1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK2LANE2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK2LANE3_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK2LANE4_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK2LANE5_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK2LANE6_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK2LANE7_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK2LANE8_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK3LANE0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK3LANE1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK3LANE2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK3LANE3_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK3LANE4_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK3LANE5_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK3LANE6_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK3LANE7_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH0_CR_DDRDATADQRANK3LANE8_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQSRANK0_STRUCT DATA8CH0_CR_DDRDATADQSRANK0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQSRANK0_STRUCT DATA8CH0_CR_DDRDATADQSRANK1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQSRANK0_STRUCT DATA8CH0_CR_DDRDATADQSRANK2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQSRANK0_STRUCT DATA8CH0_CR_DDRDATADQSRANK3_P0_STRUCT;
typedef DATA0CH0_CR_RXCONTROL0RANK0_STRUCT DATA8CH0_CR_RXCONTROL0RANK0_P0_STRUCT;
typedef DATA0CH0_CR_RXCONTROL0RANK0_STRUCT DATA8CH0_CR_RXCONTROL0RANK1_P0_STRUCT;
typedef DATA0CH0_CR_RXCONTROL0RANK0_STRUCT DATA8CH0_CR_RXCONTROL0RANK2_P0_STRUCT;
typedef DATA0CH0_CR_RXCONTROL0RANK0_STRUCT DATA8CH0_CR_RXCONTROL0RANK3_P0_STRUCT;
typedef DATA0CH0_CR_TXCONTROL0RANK0_STRUCT DATA8CH0_CR_TXCONTROL0RANK0_P0_STRUCT;
typedef DATA0CH0_CR_TXCONTROL0RANK0_STRUCT DATA8CH0_CR_TXCONTROL0RANK1_P0_STRUCT;
typedef DATA0CH0_CR_TXCONTROL0RANK0_STRUCT DATA8CH0_CR_TXCONTROL0RANK2_P0_STRUCT;
typedef DATA0CH0_CR_TXCONTROL0RANK0_STRUCT DATA8CH0_CR_TXCONTROL0RANK3_P0_STRUCT;
typedef DATA0CH0_CR_RCOMPDATA0_STRUCT DATA8CH0_CR_RCOMPDATA0_P0_STRUCT;
typedef DATA0CH0_CR_RCOMPDATA1_STRUCT DATA8CH0_CR_RCOMPDATA1_P0_STRUCT;
typedef DATA0CH0_CR_DATACOMPVTT_STRUCT DATA8CH0_CR_DATACOMPVTT_P0_STRUCT;
typedef DATA0CH0_CR_DATATRAINFEEDBACK_STRUCT DATA8CH0_CR_DATATRAINFEEDBACK_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT DATA8CH0_CR_DDRCRDATAOFFSETCOMP_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT DATA8CH0_CR_DDRCRDATAOFFSETTRAIN_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL0_STRUCT DATA8CH0_CR_DDRCRDATACONTROL0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL1_STRUCT DATA8CH0_CR_DDRCRDATACONTROL1_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL2_STRUCT DATA8CH0_CR_DDRCRDATACONTROL2_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL3_STRUCT DATA8CH0_CR_DDRCRDATACONTROL3_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL4_STRUCT DATA8CH0_CR_DDRCRDATACONTROL4_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL5_STRUCT DATA8CH0_CR_DDRCRDATACONTROL5_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL6_STRUCT DATA8CH0_CR_DDRCRDATACONTROL6_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRCMDBUSTRAIN_STRUCT DATA8CH0_CR_DDRCRCMDBUSTRAIN_P0_STRUCT;
typedef DATA0CH0_CR_DCCFSMCONTROL_STRUCT DATA8CH0_CR_DCCFSMCONTROL_P0_STRUCT;
typedef DATA0CH0_CR_DCCCALCCONTROL_STRUCT DATA8CH0_CR_DCCCALCCONTROL_P0_STRUCT;
typedef DATA0CH0_CR_DCCFSMSTATUS_STRUCT DATA8CH0_CR_DCCFSMSTATUS_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANESTATUS0_STRUCT DATA8CH0_CR_DCCLANESTATUS0_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANESTATUS1_STRUCT DATA8CH0_CR_DCCLANESTATUS1_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANESTATUS2_STRUCT DATA8CH0_CR_DCCLANESTATUS2_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANESTATUS3_STRUCT DATA8CH0_CR_DCCLANESTATUS3_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT0_STRUCT DATA8CH0_CR_DCCPILUT0_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT1_STRUCT DATA8CH0_CR_DCCPILUT1_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT2_STRUCT DATA8CH0_CR_DCCPILUT2_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT3_STRUCT DATA8CH0_CR_DCCPILUT3_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATATCOCONTROL0_STRUCT DATA8CH0_CR_DDRCRDATATCOCONTROL0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATATCOCONTROL1_STRUCT DATA8CH0_CR_DDRCRDATATCOCONTROL1_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT4_STRUCT DATA8CH0_CR_DCCPILUT4_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANETARGET_STRUCT DATA8CH0_CR_DCCLANETARGET_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINSWIZZLECONTROL_STRUCT DATA8CH0_CR_DDRCRWRRETRAINSWIZZLECONTROL_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINRANK3_STRUCT DATA8CH0_CR_DDRCRWRRETRAINRANK3_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINRANK3_STRUCT DATA8CH0_CR_DDRCRWRRETRAINRANK2_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINRANK3_STRUCT DATA8CH0_CR_DDRCRWRRETRAINRANK1_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINRANK3_STRUCT DATA8CH0_CR_DDRCRWRRETRAINRANK0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINCONTROLSTATUS_STRUCT DATA8CH0_CR_DDRCRWRRETRAINCONTROLSTATUS_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRMARGINMODECONTROL0_STRUCT DATA8CH0_CR_DDRCRMARGINMODECONTROL0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRMARGINMODEDEBUGMSB0_STRUCT DATA8CH0_CR_DDRCRMARGINMODEDEBUGMSB0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRMARGINMODEDEBUGMSB0_STRUCT DATA8CH0_CR_DDRCRMARGINMODEDEBUGLSB0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK0LANE0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK0LANE1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK0LANE2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK0LANE3_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK0LANE4_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK0LANE5_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK0LANE6_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK0LANE7_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK0LANE8_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK1LANE0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK1LANE1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK1LANE2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK1LANE3_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK1LANE4_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK1LANE5_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK1LANE6_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK1LANE7_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK1LANE8_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK2LANE0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK2LANE1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK2LANE2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK2LANE3_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK2LANE4_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK2LANE5_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK2LANE6_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK2LANE7_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK2LANE8_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK3LANE0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK3LANE1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK3LANE2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK3LANE3_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK3LANE4_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK3LANE5_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK3LANE6_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK3LANE7_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA8CH1_CR_DDRDATADQRANK3LANE8_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQSRANK0_STRUCT DATA8CH1_CR_DDRDATADQSRANK0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQSRANK0_STRUCT DATA8CH1_CR_DDRDATADQSRANK1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQSRANK0_STRUCT DATA8CH1_CR_DDRDATADQSRANK2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQSRANK0_STRUCT DATA8CH1_CR_DDRDATADQSRANK3_P0_STRUCT;
typedef DATA0CH0_CR_RXCONTROL0RANK0_STRUCT DATA8CH1_CR_RXCONTROL0RANK0_P0_STRUCT;
typedef DATA0CH0_CR_RXCONTROL0RANK0_STRUCT DATA8CH1_CR_RXCONTROL0RANK1_P0_STRUCT;
typedef DATA0CH0_CR_RXCONTROL0RANK0_STRUCT DATA8CH1_CR_RXCONTROL0RANK2_P0_STRUCT;
typedef DATA0CH0_CR_RXCONTROL0RANK0_STRUCT DATA8CH1_CR_RXCONTROL0RANK3_P0_STRUCT;
typedef DATA0CH0_CR_TXCONTROL0RANK0_STRUCT DATA8CH1_CR_TXCONTROL0RANK0_P0_STRUCT;
typedef DATA0CH0_CR_TXCONTROL0RANK0_STRUCT DATA8CH1_CR_TXCONTROL0RANK1_P0_STRUCT;
typedef DATA0CH0_CR_TXCONTROL0RANK0_STRUCT DATA8CH1_CR_TXCONTROL0RANK2_P0_STRUCT;
typedef DATA0CH0_CR_TXCONTROL0RANK0_STRUCT DATA8CH1_CR_TXCONTROL0RANK3_P0_STRUCT;
typedef DATA0CH0_CR_RCOMPDATA0_STRUCT DATA8CH1_CR_RCOMPDATA0_P0_STRUCT;
typedef DATA0CH0_CR_RCOMPDATA1_STRUCT DATA8CH1_CR_RCOMPDATA1_P0_STRUCT;
typedef DATA0CH0_CR_DATACOMPVTT_STRUCT DATA8CH1_CR_DATACOMPVTT_P0_STRUCT;
typedef DATA0CH0_CR_DATATRAINFEEDBACK_STRUCT DATA8CH1_CR_DATATRAINFEEDBACK_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT DATA8CH1_CR_DDRCRDATAOFFSETCOMP_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT DATA8CH1_CR_DDRCRDATAOFFSETTRAIN_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL0_STRUCT DATA8CH1_CR_DDRCRDATACONTROL0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL1_STRUCT DATA8CH1_CR_DDRCRDATACONTROL1_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL2_STRUCT DATA8CH1_CR_DDRCRDATACONTROL2_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL3_STRUCT DATA8CH1_CR_DDRCRDATACONTROL3_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL4_STRUCT DATA8CH1_CR_DDRCRDATACONTROL4_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL5_STRUCT DATA8CH1_CR_DDRCRDATACONTROL5_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL6_STRUCT DATA8CH1_CR_DDRCRDATACONTROL6_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRCMDBUSTRAIN_STRUCT DATA8CH1_CR_DDRCRCMDBUSTRAIN_P0_STRUCT;
typedef DATA0CH0_CR_DCCFSMCONTROL_STRUCT DATA8CH1_CR_DCCFSMCONTROL_P0_STRUCT;
typedef DATA0CH0_CR_DCCCALCCONTROL_STRUCT DATA8CH1_CR_DCCCALCCONTROL_P0_STRUCT;
typedef DATA0CH0_CR_DCCFSMSTATUS_STRUCT DATA8CH1_CR_DCCFSMSTATUS_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANESTATUS0_STRUCT DATA8CH1_CR_DCCLANESTATUS0_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANESTATUS1_STRUCT DATA8CH1_CR_DCCLANESTATUS1_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANESTATUS2_STRUCT DATA8CH1_CR_DCCLANESTATUS2_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANESTATUS3_STRUCT DATA8CH1_CR_DCCLANESTATUS3_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT0_STRUCT DATA8CH1_CR_DCCPILUT0_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT1_STRUCT DATA8CH1_CR_DCCPILUT1_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT2_STRUCT DATA8CH1_CR_DCCPILUT2_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT3_STRUCT DATA8CH1_CR_DCCPILUT3_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATATCOCONTROL0_STRUCT DATA8CH1_CR_DDRCRDATATCOCONTROL0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATATCOCONTROL1_STRUCT DATA8CH1_CR_DDRCRDATATCOCONTROL1_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT4_STRUCT DATA8CH1_CR_DCCPILUT4_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANETARGET_STRUCT DATA8CH1_CR_DCCLANETARGET_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINSWIZZLECONTROL_STRUCT DATA8CH1_CR_DDRCRWRRETRAINSWIZZLECONTROL_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINRANK3_STRUCT DATA8CH1_CR_DDRCRWRRETRAINRANK3_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINRANK3_STRUCT DATA8CH1_CR_DDRCRWRRETRAINRANK2_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINRANK3_STRUCT DATA8CH1_CR_DDRCRWRRETRAINRANK1_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINRANK3_STRUCT DATA8CH1_CR_DDRCRWRRETRAINRANK0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINCONTROLSTATUS_STRUCT DATA8CH1_CR_DDRCRWRRETRAINCONTROLSTATUS_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRMARGINMODECONTROL0_STRUCT DATA8CH1_CR_DDRCRMARGINMODECONTROL0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRMARGINMODEDEBUGMSB0_STRUCT DATA8CH1_CR_DDRCRMARGINMODEDEBUGMSB0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRMARGINMODEDEBUGMSB0_STRUCT DATA8CH1_CR_DDRCRMARGINMODEDEBUGLSB0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK0LANE0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK0LANE1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK0LANE2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK0LANE3_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK0LANE4_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK0LANE5_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK0LANE6_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK0LANE7_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK0LANE8_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK1LANE0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK1LANE1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK1LANE2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK1LANE3_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK1LANE4_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK1LANE5_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK1LANE6_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK1LANE7_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK1LANE8_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK2LANE0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK2LANE1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK2LANE2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK2LANE3_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK2LANE4_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK2LANE5_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK2LANE6_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK2LANE7_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK2LANE8_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK3LANE0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK3LANE1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK3LANE2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK3LANE3_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK3LANE4_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK3LANE5_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK3LANE6_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK3LANE7_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH0_CR_DDRDATADQRANK3LANE8_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQSRANK0_STRUCT DATA9CH0_CR_DDRDATADQSRANK0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQSRANK0_STRUCT DATA9CH0_CR_DDRDATADQSRANK1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQSRANK0_STRUCT DATA9CH0_CR_DDRDATADQSRANK2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQSRANK0_STRUCT DATA9CH0_CR_DDRDATADQSRANK3_P0_STRUCT;
typedef DATA0CH0_CR_RXCONTROL0RANK0_STRUCT DATA9CH0_CR_RXCONTROL0RANK0_P0_STRUCT;
typedef DATA0CH0_CR_RXCONTROL0RANK0_STRUCT DATA9CH0_CR_RXCONTROL0RANK1_P0_STRUCT;
typedef DATA0CH0_CR_RXCONTROL0RANK0_STRUCT DATA9CH0_CR_RXCONTROL0RANK2_P0_STRUCT;
typedef DATA0CH0_CR_RXCONTROL0RANK0_STRUCT DATA9CH0_CR_RXCONTROL0RANK3_P0_STRUCT;
typedef DATA0CH0_CR_TXCONTROL0RANK0_STRUCT DATA9CH0_CR_TXCONTROL0RANK0_P0_STRUCT;
typedef DATA0CH0_CR_TXCONTROL0RANK0_STRUCT DATA9CH0_CR_TXCONTROL0RANK1_P0_STRUCT;
typedef DATA0CH0_CR_TXCONTROL0RANK0_STRUCT DATA9CH0_CR_TXCONTROL0RANK2_P0_STRUCT;
typedef DATA0CH0_CR_TXCONTROL0RANK0_STRUCT DATA9CH0_CR_TXCONTROL0RANK3_P0_STRUCT;
typedef DATA0CH0_CR_RCOMPDATA0_STRUCT DATA9CH0_CR_RCOMPDATA0_P0_STRUCT;
typedef DATA0CH0_CR_RCOMPDATA1_STRUCT DATA9CH0_CR_RCOMPDATA1_P0_STRUCT;
typedef DATA0CH0_CR_DATACOMPVTT_STRUCT DATA9CH0_CR_DATACOMPVTT_P0_STRUCT;
typedef DATA0CH0_CR_DATATRAINFEEDBACK_STRUCT DATA9CH0_CR_DATATRAINFEEDBACK_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT DATA9CH0_CR_DDRCRDATAOFFSETCOMP_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT DATA9CH0_CR_DDRCRDATAOFFSETTRAIN_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL0_STRUCT DATA9CH0_CR_DDRCRDATACONTROL0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL1_STRUCT DATA9CH0_CR_DDRCRDATACONTROL1_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL2_STRUCT DATA9CH0_CR_DDRCRDATACONTROL2_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL3_STRUCT DATA9CH0_CR_DDRCRDATACONTROL3_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL4_STRUCT DATA9CH0_CR_DDRCRDATACONTROL4_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL5_STRUCT DATA9CH0_CR_DDRCRDATACONTROL5_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL6_STRUCT DATA9CH0_CR_DDRCRDATACONTROL6_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRCMDBUSTRAIN_STRUCT DATA9CH0_CR_DDRCRCMDBUSTRAIN_P0_STRUCT;
typedef DATA0CH0_CR_DCCFSMCONTROL_STRUCT DATA9CH0_CR_DCCFSMCONTROL_P0_STRUCT;
typedef DATA0CH0_CR_DCCCALCCONTROL_STRUCT DATA9CH0_CR_DCCCALCCONTROL_P0_STRUCT;
typedef DATA0CH0_CR_DCCFSMSTATUS_STRUCT DATA9CH0_CR_DCCFSMSTATUS_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANESTATUS0_STRUCT DATA9CH0_CR_DCCLANESTATUS0_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANESTATUS1_STRUCT DATA9CH0_CR_DCCLANESTATUS1_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANESTATUS2_STRUCT DATA9CH0_CR_DCCLANESTATUS2_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANESTATUS3_STRUCT DATA9CH0_CR_DCCLANESTATUS3_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT0_STRUCT DATA9CH0_CR_DCCPILUT0_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT1_STRUCT DATA9CH0_CR_DCCPILUT1_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT2_STRUCT DATA9CH0_CR_DCCPILUT2_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT3_STRUCT DATA9CH0_CR_DCCPILUT3_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATATCOCONTROL0_STRUCT DATA9CH0_CR_DDRCRDATATCOCONTROL0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATATCOCONTROL1_STRUCT DATA9CH0_CR_DDRCRDATATCOCONTROL1_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT4_STRUCT DATA9CH0_CR_DCCPILUT4_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANETARGET_STRUCT DATA9CH0_CR_DCCLANETARGET_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINSWIZZLECONTROL_STRUCT DATA9CH0_CR_DDRCRWRRETRAINSWIZZLECONTROL_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINRANK3_STRUCT DATA9CH0_CR_DDRCRWRRETRAINRANK3_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINRANK3_STRUCT DATA9CH0_CR_DDRCRWRRETRAINRANK2_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINRANK3_STRUCT DATA9CH0_CR_DDRCRWRRETRAINRANK1_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINRANK3_STRUCT DATA9CH0_CR_DDRCRWRRETRAINRANK0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINCONTROLSTATUS_STRUCT DATA9CH0_CR_DDRCRWRRETRAINCONTROLSTATUS_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRMARGINMODECONTROL0_STRUCT DATA9CH0_CR_DDRCRMARGINMODECONTROL0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRMARGINMODEDEBUGMSB0_STRUCT DATA9CH0_CR_DDRCRMARGINMODEDEBUGMSB0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRMARGINMODEDEBUGMSB0_STRUCT DATA9CH0_CR_DDRCRMARGINMODEDEBUGLSB0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK0LANE0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK0LANE1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK0LANE2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK0LANE3_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK0LANE4_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK0LANE5_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK0LANE6_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK0LANE7_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK0LANE8_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK1LANE0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK1LANE1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK1LANE2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK1LANE3_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK1LANE4_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK1LANE5_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK1LANE6_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK1LANE7_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK1LANE8_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK2LANE0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK2LANE1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK2LANE2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK2LANE3_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK2LANE4_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK2LANE5_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK2LANE6_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK2LANE7_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK2LANE8_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK3LANE0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK3LANE1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK3LANE2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK3LANE3_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK3LANE4_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK3LANE5_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK3LANE6_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK3LANE7_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQRANK0LANE0_STRUCT DATA9CH1_CR_DDRDATADQRANK3LANE8_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQSRANK0_STRUCT DATA9CH1_CR_DDRDATADQSRANK0_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQSRANK0_STRUCT DATA9CH1_CR_DDRDATADQSRANK1_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQSRANK0_STRUCT DATA9CH1_CR_DDRDATADQSRANK2_P0_STRUCT;
typedef DATA0CH0_CR_DDRDATADQSRANK0_STRUCT DATA9CH1_CR_DDRDATADQSRANK3_P0_STRUCT;
typedef DATA0CH0_CR_RXCONTROL0RANK0_STRUCT DATA9CH1_CR_RXCONTROL0RANK0_P0_STRUCT;
typedef DATA0CH0_CR_RXCONTROL0RANK0_STRUCT DATA9CH1_CR_RXCONTROL0RANK1_P0_STRUCT;
typedef DATA0CH0_CR_RXCONTROL0RANK0_STRUCT DATA9CH1_CR_RXCONTROL0RANK2_P0_STRUCT;
typedef DATA0CH0_CR_RXCONTROL0RANK0_STRUCT DATA9CH1_CR_RXCONTROL0RANK3_P0_STRUCT;
typedef DATA0CH0_CR_TXCONTROL0RANK0_STRUCT DATA9CH1_CR_TXCONTROL0RANK0_P0_STRUCT;
typedef DATA0CH0_CR_TXCONTROL0RANK0_STRUCT DATA9CH1_CR_TXCONTROL0RANK1_P0_STRUCT;
typedef DATA0CH0_CR_TXCONTROL0RANK0_STRUCT DATA9CH1_CR_TXCONTROL0RANK2_P0_STRUCT;
typedef DATA0CH0_CR_TXCONTROL0RANK0_STRUCT DATA9CH1_CR_TXCONTROL0RANK3_P0_STRUCT;
typedef DATA0CH0_CR_RCOMPDATA0_STRUCT DATA9CH1_CR_RCOMPDATA0_P0_STRUCT;
typedef DATA0CH0_CR_RCOMPDATA1_STRUCT DATA9CH1_CR_RCOMPDATA1_P0_STRUCT;
typedef DATA0CH0_CR_DATACOMPVTT_STRUCT DATA9CH1_CR_DATACOMPVTT_P0_STRUCT;
typedef DATA0CH0_CR_DATATRAINFEEDBACK_STRUCT DATA9CH1_CR_DATATRAINFEEDBACK_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATAOFFSETCOMP_STRUCT DATA9CH1_CR_DDRCRDATAOFFSETCOMP_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATAOFFSETTRAIN_STRUCT DATA9CH1_CR_DDRCRDATAOFFSETTRAIN_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL0_STRUCT DATA9CH1_CR_DDRCRDATACONTROL0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL1_STRUCT DATA9CH1_CR_DDRCRDATACONTROL1_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL2_STRUCT DATA9CH1_CR_DDRCRDATACONTROL2_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL3_STRUCT DATA9CH1_CR_DDRCRDATACONTROL3_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL4_STRUCT DATA9CH1_CR_DDRCRDATACONTROL4_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL5_STRUCT DATA9CH1_CR_DDRCRDATACONTROL5_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATACONTROL6_STRUCT DATA9CH1_CR_DDRCRDATACONTROL6_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRCMDBUSTRAIN_STRUCT DATA9CH1_CR_DDRCRCMDBUSTRAIN_P0_STRUCT;
typedef DATA0CH0_CR_DCCFSMCONTROL_STRUCT DATA9CH1_CR_DCCFSMCONTROL_P0_STRUCT;
typedef DATA0CH0_CR_DCCCALCCONTROL_STRUCT DATA9CH1_CR_DCCCALCCONTROL_P0_STRUCT;
typedef DATA0CH0_CR_DCCFSMSTATUS_STRUCT DATA9CH1_CR_DCCFSMSTATUS_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANESTATUS0_STRUCT DATA9CH1_CR_DCCLANESTATUS0_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANESTATUS1_STRUCT DATA9CH1_CR_DCCLANESTATUS1_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANESTATUS2_STRUCT DATA9CH1_CR_DCCLANESTATUS2_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANESTATUS3_STRUCT DATA9CH1_CR_DCCLANESTATUS3_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT0_STRUCT DATA9CH1_CR_DCCPILUT0_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT1_STRUCT DATA9CH1_CR_DCCPILUT1_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT2_STRUCT DATA9CH1_CR_DCCPILUT2_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT3_STRUCT DATA9CH1_CR_DCCPILUT3_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATATCOCONTROL0_STRUCT DATA9CH1_CR_DDRCRDATATCOCONTROL0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRDATATCOCONTROL1_STRUCT DATA9CH1_CR_DDRCRDATATCOCONTROL1_P0_STRUCT;
typedef DATA0CH0_CR_DCCPILUT4_STRUCT DATA9CH1_CR_DCCPILUT4_P0_STRUCT;
typedef DATA0CH0_CR_DCCLANETARGET_STRUCT DATA9CH1_CR_DCCLANETARGET_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINSWIZZLECONTROL_STRUCT DATA9CH1_CR_DDRCRWRRETRAINSWIZZLECONTROL_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINRANK3_STRUCT DATA9CH1_CR_DDRCRWRRETRAINRANK3_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINRANK3_STRUCT DATA9CH1_CR_DDRCRWRRETRAINRANK2_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINRANK3_STRUCT DATA9CH1_CR_DDRCRWRRETRAINRANK1_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINRANK3_STRUCT DATA9CH1_CR_DDRCRWRRETRAINRANK0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRWRRETRAINCONTROLSTATUS_STRUCT DATA9CH1_CR_DDRCRWRRETRAINCONTROLSTATUS_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRMARGINMODECONTROL0_STRUCT DATA9CH1_CR_DDRCRMARGINMODECONTROL0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRMARGINMODEDEBUGMSB0_STRUCT DATA9CH1_CR_DDRCRMARGINMODEDEBUGMSB0_P0_STRUCT;
typedef DATA0CH0_CR_DDRCRMARGINMODEDEBUGMSB0_STRUCT DATA9CH1_CR_DDRCRMARGINMODEDEBUGLSB0_P0_STRUCT;
typedef union {
  struct {
    UINT32 Target                                  :  7;  // Bits 6:0
    UINT32 HiBWDivider                             :  2;  // Bits 8:7
    UINT32 LoBWDivider                             :  2;  // Bits 10:9
    UINT32 SampleDivider                           :  2;  // Bits 12:11
    UINT32 Bypass                                  :  1;  // Bits 13:13
    UINT32 OpenLoop                                :  1;  // Bits 14:14
    UINT32 BWError                                 :  2;  // Bits 16:15
    UINT32 PanicEn                                 :  1;  // Bits 17:17
    UINT32 EnDacPM                                 :  2;  // Bits 19:18
    UINT32 Spare                                   :  1;  // Bits 20:20
    UINT32 EnRemoteSense                           :  1;  // Bits 21:21
    UINT32 SelCode                                 :  1;  // Bits 22:22
    UINT32 OutputCode                              :  9;  // Bits 31:23
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVCCDLL0_CR_DDRCRVCCDLLCONTROL_STRUCT;
typedef union {
  struct {
    UINT32 FFCodeWeak                              :  6;  // Bits 5:0
    UINT32 FFCodeIdle                              :  6;  // Bits 11:6
    UINT32 FFCodePI                                :  6;  // Bits 17:12
    UINT32 CodeVtp                                 :  6;  // Bits 23:18
    UINT32 RloadDqs                                :  6;  // Bits 29:24
    UINT32 Spare                                   :  2;  // Bits 31:30
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVCCDLL0_CR_DDRCRVCCDLLCOMPDLL_STRUCT;
typedef union {
  struct {
    UINT32 PullDownSlope                           :  2;  // Bits 1:0
    UINT32 FBOverlap                               :  2;  // Bits 3:2
    UINT32 Panic                                   :  5;  // Bits 8:4
    UINT32 GainBoost                               :  2;  // Bits 10:9
    UINT32 Spare1                                  :  1;  // Bits 11:11
    UINT32 DisOffset                               :  1;  // Bits 12:12
    UINT32 NSalCMCap                               :  3;  // Bits 15:13
    UINT32 CodeReset                               :  3;  // Bits 18:16
    UINT32 LoBWDividerLP                           :  2;  // Bits 20:19
    UINT32 LoBWSGatedMode                          :  2;  // Bits 22:21
    UINT32 WakeUpDelay                             :  3;  // Bits 25:23
    UINT32 LocalVsxHiBypass                        :  1;  // Bits 26:26
    UINT32 LockTimer                               :  2;  // Bits 28:27
    UINT32 AckOffset                               :  1;  // Bits 29:29
    UINT32 Spare3                                  :  2;  // Bits 31:30
  } Bits;
  struct {
    UINT32 Spare0                                  :  2;  // Bits 1:0
    UINT32 FBOverlap                               :  2;  // Bits 3:2
    UINT32 Panic                                   :  5;  // Bits 8:4
    UINT32 GainBoost                               :  2;  // Bits 10:9
    UINT32 Spare1                                  :  1;  // Bits 11:11
    UINT32 DisOffset                               :  1;  // Bits 12:12
    UINT32 NSalCMCap                               :  3;  // Bits 15:13
    UINT32 CodeReset                               :  3;  // Bits 18:16
    UINT32 LoBWDividerLP                           :  2;  // Bits 20:19
    UINT32 LoBWSGatedMode                          :  2;  // Bits 22:21
    UINT32 WakeUpDelay                             :  3;  // Bits 25:23
    UINT32 LocalVsxHiBypass                        :  1;  // Bits 26:26
    UINT32 LockTimer                               :  2;  // Bits 28:27
    UINT32 AckOffset                               :  1;  // Bits 29:29
    UINT32 Spare3                                  :  2;  // Bits 31:30
  } A0Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVCCDLL0_CR_DDRCRVCCDLLSAMPLER_STRUCT;
typedef union {
  struct {
    UINT32 SpareCompOfst                           :  6;  // Bits 5:0
    UINT32 TargetCompOfst                          :  6;  // Bits 11:6
    UINT32 PanicLoCompOfst                         :  6;  // Bits 17:12
    UINT32 PanicHiCompOfst                         :  6;  // Bits 23:18
    UINT32 Spare                                   :  8;  // Bits 31:24
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVCCDLL0_CR_DDRCRVCCDLLVOLTAGES_STRUCT;

typedef DDRVCCDLL0_CR_DDRCRVCCDLLCONTROL_STRUCT DDRVCCDLL1_CR_DDRCRVCCDLLCONTROL_STRUCT;

typedef DDRVCCDLL0_CR_DDRCRVCCDLLCOMPDLL_STRUCT DDRVCCDLL1_CR_DDRCRVCCDLLCOMPDLL_STRUCT;

typedef DDRVCCDLL0_CR_DDRCRVCCDLLSAMPLER_STRUCT DDRVCCDLL1_CR_DDRCRVCCDLLSAMPLER_STRUCT;

typedef DDRVCCDLL0_CR_DDRCRVCCDLLVOLTAGES_STRUCT DDRVCCDLL1_CR_DDRCRVCCDLLVOLTAGES_STRUCT;
typedef union {
  struct {
    UINT32 Target                                  :  8;  // Bits 7:0
    UINT32 Panic0                                  :  4;  // Bits 11:8
    UINT32 Panic1                                  :  5;  // Bits 16:12
    UINT32 Spare1                                  :  1;  // Bits 17:17
    UINT32 DisOffset                               :  1;  // Bits 18:18
    UINT32 Spare3                                  :  1;  // Bits 19:19
    UINT32 EnDacPM                                 :  2;  // Bits 21:20
    UINT32 DdrCRForceODTOn                         :  1;  // Bits 22:22
    UINT32 EnVttOdt                                :  1;  // Bits 23:23
    UINT32 WakeUpDelay                             :  3;  // Bits 26:24
    UINT32 UseFLLDuringDVFS                        :  1;  // Bits 27:27
    UINT32 LockTimer                               :  2;  // Bits 29:28
    UINT32 AckOffset                               :  1;  // Bits 30:30
    UINT32 Spare                                   :  1;  // Bits 31:31
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVTT0_CR_DDRCRVTTGENCONTROL_STRUCT;

typedef DDRVCCDLL0_CR_DDRCRVCCDLLCONTROL_STRUCT DDRVCCDLL2_CR_DDRCRVCCDLLCONTROL_P0_STRUCT;
typedef union {
  struct {
    UINT32 EnCount                                 :  1;  // Bits 0:0
    UINT32 SelCount                                :  3;  // Bits 3:1
    UINT32 RstCount                                :  1;  // Bits 4:4
    UINT32 Count                                   :  16;  // Bits 20:5
    UINT32 Spare                                   :  11;  // Bits 31:21
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVTT0_CR_DDRCRVTTGENSTATUS_STRUCT;

typedef DDRVCCDLL0_CR_DDRCRVCCDLLCOMPDLL_STRUCT DDRVCCDLL2_CR_DDRCRVCCDLLCOMPDLL_P0_STRUCT;
typedef union {
  struct {
    UINT32 SpareNmosCompOfst                       :  6;  // Bits 5:0
    UINT32 PanicLo0CompOfst                        :  6;  // Bits 11:6
    UINT32 PanicLo1CompOfst                        :  6;  // Bits 17:12
    UINT32 PanicHi0CompOfst                        :  6;  // Bits 23:18
    UINT32 PanicHi1CompOfst                        :  6;  // Bits 29:24
    UINT32 spare                                   :  2;  // Bits 31:30
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVTT0_CR_DDRCRVTTCOMPOFFSET_STRUCT;

typedef DDRVCCDLL0_CR_DDRCRVCCDLLSAMPLER_STRUCT DDRVCCDLL2_CR_DDRCRVCCDLLSAMPLER_P0_STRUCT;
typedef union {
  struct {
    UINT32 SparePmosCompOfst                       :  6;  // Bits 5:0
    UINT32 PanicLo0UsePmos                         :  1;  // Bits 6:6
    UINT32 PanicLo1UsePmos                         :  1;  // Bits 7:7
    UINT32 PanicHi0UsePmos                         :  1;  // Bits 8:8
    UINT32 PanicHi1UsePmos                         :  1;  // Bits 9:9
    UINT32 spare                                   :  22;  // Bits 31:10
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVTT0_CR_DDRCRVTTCOMPOFFSET2_STRUCT;

typedef DDRVCCDLL0_CR_DDRCRVCCDLLVOLTAGES_STRUCT DDRVCCDLL2_CR_DDRCRVCCDLLVOLTAGES_P0_STRUCT;

typedef DDRVTT0_CR_DDRCRVTTGENCONTROL_STRUCT DDRVTT1_CR_DDRCRVTTGENCONTROL_STRUCT;

typedef DDRVTT0_CR_DDRCRVTTGENSTATUS_STRUCT DDRVTT1_CR_DDRCRVTTGENSTATUS_STRUCT;

typedef DDRVTT0_CR_DDRCRVTTCOMPOFFSET_STRUCT DDRVTT1_CR_DDRCRVTTCOMPOFFSET_STRUCT;

typedef DDRVTT0_CR_DDRCRVTTCOMPOFFSET2_STRUCT DDRVTT1_CR_DDRCRVTTCOMPOFFSET2_STRUCT;

typedef DDRVTT0_CR_DDRCRVTTGENCONTROL_STRUCT DDRVTT2_CR_DDRCRVTTGENCONTROL_STRUCT;

typedef DDRVTT0_CR_DDRCRVTTGENSTATUS_STRUCT DDRVTT2_CR_DDRCRVTTGENSTATUS_STRUCT;

typedef DDRVTT0_CR_DDRCRVTTCOMPOFFSET_STRUCT DDRVTT2_CR_DDRCRVTTCOMPOFFSET_STRUCT;

typedef DDRVTT0_CR_DDRCRVTTCOMPOFFSET2_STRUCT DDRVTT2_CR_DDRCRVTTCOMPOFFSET2_STRUCT;

typedef DDRVTT0_CR_DDRCRVTTGENCONTROL_STRUCT DDRVTT3_CR_DDRCRVTTGENCONTROL_STRUCT;

typedef DDRVTT0_CR_DDRCRVTTGENSTATUS_STRUCT DDRVTT3_CR_DDRCRVTTGENSTATUS_STRUCT;

typedef DDRVTT0_CR_DDRCRVTTCOMPOFFSET_STRUCT DDRVTT3_CR_DDRCRVTTCOMPOFFSET_STRUCT;

typedef DDRVTT0_CR_DDRCRVTTCOMPOFFSET2_STRUCT DDRVTT3_CR_DDRCRVTTCOMPOFFSET2_STRUCT;
typedef union {
  struct {
    UINT32 VTComp                                  :  6;  // Bits 5:0
    UINT32 ViewDrvUp                               :  6;  // Bits 11:6
    UINT32 ViewDrvDn                               :  6;  // Bits 17:12
    UINT32 Spare                                   :  14;  // Bits 31:18
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVREF_CR_DDRRCOMPDATA_STRUCT;
typedef union {
  struct {
    UINT32 HiBWDivider                             :  2;  // Bits 1:0
    UINT32 LoBWDivider                             :  2;  // Bits 3:2
    UINT32 SampleDivider                           :  3;  // Bits 6:4
    UINT32 OpenLoop                                :  1;  // Bits 7:7
    UINT32 SlowBWError                             :  2;  // Bits 9:8
    UINT32 HiBWEnable                              :  1;  // Bits 10:10
    UINT32 VtSlope                                 :  5;  // Bits 15:11
    INT32  VtOffset                                :  5;  // Bits 20:16
    UINT32 SelCode                                 :  3;  // Bits 23:21
    UINT32 OutputCode                              :  8;  // Bits 31:24
  } Bits;
  struct {
    UINT32 HiBWDivider                             :  2;  // Bits 1:0
    UINT32 LoBWDivider                             :  2;  // Bits 3:2
    UINT32 SampleDivider                           :  3;  // Bits 6:4
    UINT32 OpenLoop                                :  1;  // Bits 7:7
    UINT32 SlowBWError                             :  2;  // Bits 9:8
    UINT32 HiBWEnable                              :  1;  // Bits 10:10
    UINT32 VtSlope                                 :  5;  // Bits 15:11
    UINT32 VtOffset                                :  5;  // Bits 20:16
    UINT32 SelCode                                 :  3;  // Bits 23:21
    UINT32 OutputCode                              :  8;  // Bits 31:24
  } A0Bits;
  struct {
    UINT32 HiBWDivider                             :  2;  // Bits 1:0
    UINT32 LoBWDivider                             :  2;  // Bits 3:2
    UINT32 SampleDivider                           :  2;  // Bits 5:4
    UINT32 OpenLoop                                :  1;  // Bits 6:6
    UINT32 SlowBWError                             :  2;  // Bits 8:7
    UINT32 HiBWEnable                              :  1;  // Bits 9:9
    UINT32 VtSlope                                 :  5;  // Bits 14:10
    INT32  VtOffset                                :  5;  // Bits 19:15
    UINT32 SelCode                                 :  4;  // Bits 23:20
    UINT32 OutputCode                              :  8;  // Bits 31:24
  } P0Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVREF_CR_DDRCRVREFCONTROL_STRUCT;
typedef union {
  struct {
    UINT32 ca0Vref                                 :  9;  // Bits 8:0
    UINT32 ca1Vref                                 :  9;  // Bits 17:9
    UINT32 rsvd0                                   :  9;  // Bits 26:18
    UINT32 enCA0Vref                               :  1;  // Bits 27:27
    UINT32 enCA1Vref                               :  1;  // Bits 28:28
    UINT32 SAGVOpenLoopEn                          :  1;  // Bits 29:29
    UINT32 SAGVLockCodeCtl                         :  1;  // Bits 30:30
    UINT32 SAGVFastBwDisable                       :  1;  // Bits 31:31
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVREF_CR_DDRCRVREFADJUST1_STRUCT;
typedef union {
  struct {
    UINT32 ca0Vref                                 :  9;  // Bits 8:0
    UINT32 ca1Vref                                 :  9;  // Bits 17:9
    UINT32 rsvd0                                   :  9;  // Bits 26:18
    UINT32 enCA0Vref                               :  1;  // Bits 27:27
    UINT32 enCA1Vref                               :  1;  // Bits 28:28
    UINT32 SAGVOpenLoopEn                          :  1;  // Bits 29:29
    UINT32 SAGVLockCodeCtl                         :  1;  // Bits 30:30
    UINT32 SAGVFastBwDisable                       :  1;  // Bits 31:31
  } P0Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVREF_CR_DDRCRVREFCH0_P0_STRUCT;
typedef union {
  struct {
    UINT32 HiZTimerCtrl                            :  2;  // Bits 1:0
    UINT32 ca0SlowBW                               :  1;  // Bits 2:2
    UINT32 ca1SlowBW                               :  1;  // Bits 3:3
    UINT32 LockOvrd                                :  2;  // Bits 5:4
    UINT32 LockTimer                               :  3;  // Bits 8:6
    UINT32 VtSlopeSAGV                             :  5;  // Bits 13:9
    INT32  VtOffsetSAGV                            :  5;  // Bits 18:14
    UINT32 GateICinDVFS                            :  1;  // Bits 19:19
    UINT32 rsvd0                                   :  2;  // Bits 21:20
    UINT32 SagvVtCtl                               :  1;  // Bits 22:22
    UINT32 vtcompovrden                            :  1;  // Bits 23:23
    UINT32 vtcompovrd                              :  8;  // Bits 31:24
  } Bits;
  struct {
    UINT32 HiZTimerCtrl                            :  2;  // Bits 1:0
    UINT32 ca0SlowBW                               :  1;  // Bits 2:2
    UINT32 ca1SlowBW                               :  1;  // Bits 3:3
    UINT32 LockOvrd                                :  2;  // Bits 5:4
    UINT32 LockTimer                               :  3;  // Bits 8:6
    UINT32 VtSlopeSAGV                             :  5;  // Bits 13:9
    UINT32 VtOffsetSAGV                            :  5;  // Bits 18:14
    UINT32 GateICinDVFS                            :  1;  // Bits 19:19
    UINT32 rsvd0                                   :  2;  // Bits 21:20
    UINT32 SagvVtCtl                               :  1;  // Bits 22:22
    UINT32 vtcompovrden                            :  1;  // Bits 23:23
    UINT32 vtcompovrd                              :  8;  // Bits 31:24
  } A0Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVREF_CR_DDRCRVREFADJUST2_STRUCT;

typedef DDRVREF_CR_DDRCRVREFCH0_P0_STRUCT DDRVREF_CR_DDRCRVREFCH1_P0_STRUCT;
typedef union {
  struct {
    UINT32 HiZTimerCtrl                            :  2;  // Bits 1:0
    UINT32 ca00SlowBW                              :  1;  // Bits 2:2
    UINT32 ca01SlowBW                              :  1;  // Bits 3:3
    UINT32 LockOvrd                                :  2;  // Bits 5:4
    UINT32 LockTimer                               :  3;  // Bits 8:6
    UINT32 VtSlopeSAGV                             :  5;  // Bits 13:9
    INT32  VtOffsetSAGV                            :  5;  // Bits 18:14
    UINT32 GateICinDVFS                            :  1;  // Bits 19:19
    UINT32 ca10SlowBW                              :  1;  // Bits 20:20
    UINT32 ca11SlowBW                              :  1;  // Bits 21:21
    UINT32 SagvVtCtl                               :  1;  // Bits 22:22
    UINT32 vtcompovrden                            :  1;  // Bits 23:23
    UINT32 vtcompovrd                              :  8;  // Bits 31:24
  } P0Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVREF_CR_DDRCRVREFADJUST2_P0_STRUCT;
typedef union {
  struct {
    UINT32 PanicDrvDn                              :  10;  // Bits 9:0
    UINT32 PanicDrvUp                              :  10;  // Bits 19:10
    UINT32 CodeVtn                                 :  6;  // Bits 25:20
    UINT32 spare                                   :  6;  // Bits 31:26
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVSSHIAFEA_CR_DDRRCOMPDATA_STRUCT;
typedef union {
  struct {
    UINT32 Target                                  :  7;  // Bits 6:0
    UINT32 HiBWDivider                             :  2;  // Bits 8:7
    UINT32 LoBWDivider                             :  2;  // Bits 10:9
    UINT32 Spare1                                  :  1;  // Bits 11:11
    UINT32 SampleDivider                           :  2;  // Bits 13:12
    UINT32 OpenLoop                                :  1;  // Bits 14:14
    UINT32 BWError                                 :  2;  // Bits 16:15
    UINT32 PanicEn                                 :  1;  // Bits 17:17
    UINT32 EnDacPM                                 :  2;  // Bits 19:18
    UINT32 EnCkePanic                              :  1;  // Bits 20:20
    UINT32 GainBoost                               :  1;  // Bits 21:21
    UINT32 SelCode                                 :  1;  // Bits 22:22
    UINT32 UseMax                                  :  1;  // Bits 23:23
    UINT32 OutputCode                              :  8;  // Bits 31:24
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVSSHIAFEA_CR_DDRCRVSSHICONTROL_STRUCT;
typedef union {
  struct {
    UINT32 Target                                  :  7;  // Bits 6:0
    UINT32 Panic                                   :  5;  // Bits 11:7
    UINT32 VsxHiFbSelect                           :  1;  // Bits 12:12
    UINT32 DisOfst                                 :  1;  // Bits 13:13
    UINT32 Spare3                                  :  1;  // Bits 14:14
    UINT32 LoBWSGatedMode                          :  2;  // Bits 16:15
    UINT32 Spare2                                  :  1;  // Bits 17:17
    UINT32 PanicLoUsePmos                          :  1;  // Bits 18:18
    UINT32 VssHiTargetUsePmos                      :  1;  // Bits 19:19
    UINT32 PanicHiUsePmos                          :  1;  // Bits 20:20
    UINT32 WakeUpDelay                             :  3;  // Bits 23:21
    UINT32 DdrVssHiGndSelQnnnH                     :  1;  // Bits 24:24
    UINT32 Spare4                                  :  1;  // Bits 25:25
    UINT32 LockTimer                               :  2;  // Bits 27:26
    UINT32 AckOffset                               :  1;  // Bits 28:28
    UINT32 Spare5                                  :  3;  // Bits 31:29
  } Bits;
  struct {
    UINT32 Target                                  :  7;  // Bits 6:0
    UINT32 Panic                                   :  5;  // Bits 11:7
    UINT32 Spare1                                  :  1;  // Bits 12:12
    UINT32 DisOfst                                 :  1;  // Bits 13:13
    UINT32 Spare3                                  :  1;  // Bits 14:14
    UINT32 LoBWSGatedMode                          :  2;  // Bits 16:15
    UINT32 Spare2                                  :  1;  // Bits 17:17
    UINT32 PanicLoUsePmos                          :  1;  // Bits 18:18
    UINT32 VssHiTargetUsePmos                      :  1;  // Bits 19:19
    UINT32 PanicHiUsePmos                          :  1;  // Bits 20:20
    UINT32 WakeUpDelay                             :  3;  // Bits 23:21
    UINT32 DdrVssHiGndSelQnnnH                     :  1;  // Bits 24:24
    UINT32 Spare4                                  :  1;  // Bits 25:25
    UINT32 LockTimer                               :  2;  // Bits 27:26
    UINT32 AckOffset                               :  1;  // Bits 28:28
    UINT32 Spare5                                  :  3;  // Bits 31:29
  } A0Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVSSHIAFEA_CR_DDRCRVSSHISAMPLER_STRUCT;
typedef union {
  struct {
    UINT32 SparePmosCompOfst                       :  6;  // Bits 5:0
    UINT32 SpareNmosCompOfst                       :  6;  // Bits 11:6
    UINT32 VsshiTargetCompOfst                     :  6;  // Bits 17:12
    UINT32 PanicLoCompOfst                         :  6;  // Bits 23:18
    UINT32 PanicHiCompOfst                         :  6;  // Bits 29:24
    UINT32 spare                                   :  2;  // Bits 31:30
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRVSSHIAFEA_CR_DDRCRVSSHICOMPOFFSET_STRUCT;

typedef DATA0CH0_CR_RCOMPDATA0_STRUCT DDRPHY_COMP_CR_DDRCRDATACOMP0_STRUCT;

typedef DATA0CH0_CR_RCOMPDATA1_STRUCT DDRPHY_COMP_CR_DDRCRDATACOMP1_STRUCT;
typedef union {
  struct {
    UINT32 Scomp                                   :  6;  // Bits 5:0
    UINT32 TcoComp                                 :  6;  // Bits 11:6
    UINT32 RcompDrvUp                              :  6;  // Bits 17:12
    UINT32 RcompDrvDown                            :  6;  // Bits 23:18
    UINT32 VssHiFF                                 :  6;  // Bits 29:24
    UINT32 Spare                                   :  2;  // Bits 31:30
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_DDRCRCACOMP_STRUCT;

typedef DDRPHY_COMP_CR_DDRCRCACOMP_STRUCT DDRPHY_COMP_CR_DDRCRCTLCOMP_STRUCT;

typedef DDRPHY_COMP_CR_DDRCRCACOMP_STRUCT DDRPHY_COMP_CR_DDRCRCLKCOMP_STRUCT;
typedef union {
  struct {
    UINT32 EnVddqOdt                               :  1;  // Bits 0:0
    UINT32 EnVttOdt                                :  1;  // Bits 1:1
    UINT32 DisableFallingPD                        :  1;  // Bits 2:2
    UINT32 sinstepadvbin                           :  1;  // Bits 3:3
    UINT32 sinstepbin                              :  1;  // Bits 4:4
    UINT32 CaVoltageSelect                         :  1;  // Bits 5:5
    UINT32 CtlVoltageSelect                        :  1;  // Bits 6:6
    UINT32 ClkVoltageSelect                        :  1;  // Bits 7:7
    UINT32 CCCPredrvUseVcciog                      :  1;  // Bits 8:8
    UINT32 CCCVssHiBypassVddqMode                  :  1;  // Bits 9:9
    UINT32 CCCVssHiBypassVdd2Mode                  :  1;  // Bits 10:10
    UINT32 CCCStaticLegCtl                         :  1;  // Bits 11:11
    UINT32 DisVddqPathWithVddq                     :  1;  // Bits 12:12
    UINT32 DQPredrvUseVcciog                       :  1;  // Bits 13:13
    UINT32 DQVssHiBypassVddqMode                   :  1;  // Bits 14:14
    UINT32 nbiasdisablevsshi                       :  1;  // Bits 15:15
    UINT32 DqOdtVrefDn                             :  8;  // Bits 23:16
    UINT32 DqOdtVrefUp                             :  8;  // Bits 31:24
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_DDRCRCOMPCTL0_STRUCT;
typedef union {
  struct {
    UINT32 DqScompCells                            :  4;  // Bits 3:0
    UINT32 DqScompPC                               :  1;  // Bits 4:4
    UINT32 CmdScompCells                           :  4;  // Bits 8:5
    UINT32 CmdScompPC                              :  1;  // Bits 9:9
    UINT32 CtlScompCells                           :  4;  // Bits 13:10
    UINT32 CtlScompPC                              :  1;  // Bits 14:14
    UINT32 ClkScompCells                           :  4;  // Bits 18:15
    UINT32 ClkScompPC                              :  1;  // Bits 19:19
    UINT32 En200ohmVsshiPncUp                      :  1;  // Bits 20:20
    UINT32 En200ohmVttPncUp                        :  1;  // Bits 21:21
    UINT32 DisableCompRotate                       :  1;  // Bits 22:22
    UINT32 DisableOdtStatic                        :  1;  // Bits 23:23
    UINT32 CompClkOn                               :  1;  // Bits 24:24
    UINT32 SelCompIntVrefSupply                    :  1;  // Bits 25:25
    UINT32 spare2                                  :  3;  // Bits 28:26
    UINT32 DisableQuickComp                        :  1;  // Bits 29:29
    UINT32 SinStep                                 :  1;  // Bits 30:30
    UINT32 SinStepAdv                              :  1;  // Bits 31:31
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_DDRCRCOMPCTL1_STRUCT;
typedef union {
  struct {
    UINT32 CmdDrvVrefUp                            :  8;  // Bits 7:0
    UINT32 CtlDrvVrefUp                            :  8;  // Bits 15:8
    UINT32 ClkDrvVrefUp                            :  8;  // Bits 23:16
    UINT32 Cmd200VrefDn                            :  8;  // Bits 31:24
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_DDRCRCOMPCTL2_STRUCT;
typedef union {
  struct {
    UINT32 DqDrvU                                  :  1;  // Bits 0:0
    UINT32 DqDrvD                                  :  1;  // Bits 1:1
    UINT32 DqOdtU                                  :  1;  // Bits 2:2
    UINT32 DqOdtD                                  :  1;  // Bits 3:3
    UINT32 CmdDrvU                                 :  1;  // Bits 4:4
    UINT32 CmdDrvD                                 :  1;  // Bits 5:5
    UINT32 CtlDrvU                                 :  1;  // Bits 6:6
    UINT32 CtlDrvD                                 :  1;  // Bits 7:7
    UINT32 ClkDrvU                                 :  1;  // Bits 8:8
    UINT32 ClkDrvD                                 :  1;  // Bits 9:9
    UINT32 DqSR                                    :  1;  // Bits 10:10
    UINT32 CmdSR                                   :  1;  // Bits 11:11
    UINT32 CtlSR                                   :  1;  // Bits 12:12
    UINT32 ClkSR                                   :  1;  // Bits 13:13
    UINT32 RloadComp                               :  1;  // Bits 14:14
    UINT32 VTNComp                                 :  1;  // Bits 15:15
    UINT32 CmdDn200                                :  1;  // Bits 16:16
    UINT32 PanicDrvUp                              :  1;  // Bits 17:17
    UINT32 PanicDrvDn                              :  1;  // Bits 18:18
    UINT32 VTPComp                                 :  1;  // Bits 19:19
    UINT32 PanicVttDn                              :  1;  // Bits 20:20
    UINT32 PanicVttUp                              :  1;  // Bits 21:21
    UINT32 viewdrvu                                :  1;  // Bits 22:22
    UINT32 viewdrvd                                :  1;  // Bits 23:23
    UINT32 Spare1ABin2                             :  1;  // Bits 24:24
    UINT32 Spare1ABin4                             :  1;  // Bits 25:25
    UINT32 Leak2VsxHiFF                            :  1;  // Bits 26:26
    UINT32 LeakQVsxHiFF                            :  1;  // Bits 27:27
    UINT32 spare                                   :  1;  // Bits 28:28
    UINT32 RcompCheckEn                            :  1;  // Bits 29:29
    UINT32 RcompSwapEn                             :  1;  // Bits 30:30
    UINT32 VtDmVrefFsm                             :  1;  // Bits 31:31
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_DDRCRCOMPOVR0_STRUCT;

typedef DATA0CH0_CR_DATACOMPVTT_STRUCT DDRPHY_COMP_CR_DDRCRDATACOMPVTT_STRUCT;

typedef DDRVSSHIAFEA_CR_DDRRCOMPDATA_STRUCT DDRPHY_COMP_CR_DDRCRVSXHICOMPDATA_STRUCT;
typedef union {
  struct {
    UINT32 CmdDrvVrefDn                            :  8;  // Bits 7:0
    UINT32 CtlDrvVrefDn                            :  8;  // Bits 15:8
    UINT32 ClkDrvVrefDn                            :  8;  // Bits 23:16
    UINT32 DqDrvVrefDn                             :  8;  // Bits 31:24
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_DDRCRCOMPCTL3_STRUCT;
typedef union {
  struct {
    UINT32 RcompCmdDn200                           :  6;  // Bits 5:0
    UINT32 FFCodeLeak                              :  7;  // Bits 12:6
    UINT32 FFCodeDqsDelay                          :  6;  // Bits 18:13
    UINT32 VsxHiFFLeakQ                            :  6;  // Bits 24:19
    UINT32 VsxHiFFLeak2                            :  6;  // Bits 30:25
    UINT32 spare                                   :  1;  // Bits 31:31
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_DDRCRCOMPTEMP_STRUCT;

typedef DDRVREF_CR_DDRRCOMPDATA_STRUCT DDRPHY_COMP_CR_DDRCOMPDATA_STRUCT;
typedef union {
  struct {
    UINT32 DqDrvVrefUp                             :  8;  // Bits 7:0
    UINT32 CompInitDelay                           :  3;  // Bits 10:8
    UINT32 CompStage2Switch                        :  3;  // Bits 13:11
    UINT32 CompStage3Switch                        :  3;  // Bits 16:14
    UINT32 CompStage4Switch                        :  3;  // Bits 19:17
    UINT32 CompStage5Switch                        :  3;  // Bits 22:20
    UINT32 CompCodeSwitch                          :  3;  // Bits 25:23
    UINT32 CaPDPreDrvCVccddq                       :  1;  // Bits 26:26
    UINT32 CtlPDPreDrvCVccddq                      :  1;  // Bits 27:27
    UINT32 ClkPDPreDrvCVccddq                      :  1;  // Bits 28:28
    UINT32 DqPDPreDrvCVccddq                       :  1;  // Bits 29:29
    UINT32 SWCapUseVdd2                            :  1;  // Bits 30:30
    UINT32 ObeyDDQBypass                           :  1;  // Bits 31:31
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_DDRCRCOMPCTL4_STRUCT;
typedef union {
  struct {
    UINT32 CompVTarget                             :  7;  // Bits 6:0
    UINT32 ForceCompAmpOn                          :  1;  // Bits 7:7
    UINT32 RstCount                                :  1;  // Bits 8:8
    UINT32 CountMSB                                :  4;  // Bits 12:9
    UINT32 SelectVssHiRail                         :  3;  // Bits 15:13
    UINT32 Spare1                                  :  1;  // Bits 16:16
    UINT32 DataPattern                             :  2;  // Bits 18:17
    UINT32 EnPeriodicComp                          :  1;  // Bits 19:19
    UINT32 vtnslope                                :  5;  // Bits 24:20
    INT32  vtnoffset                               :  6;  // Bits 30:25
    UINT32 rsvd                                    :  1;  // Bits 31:31
  } Bits;
  struct {
    UINT32 CompVTarget                             :  7;  // Bits 6:0
    UINT32 ForceCompAmpOn                          :  1;  // Bits 7:7
    UINT32 RstCount                                :  1;  // Bits 8:8
    UINT32 CountMSB                                :  4;  // Bits 12:9
    UINT32 SelectVssHiRail                         :  3;  // Bits 15:13
    UINT32 Spare1                                  :  1;  // Bits 16:16
    UINT32 DataPattern                             :  2;  // Bits 18:17
    UINT32 EnPeriodicComp                          :  1;  // Bits 19:19
    UINT32 vtnslope                                :  5;  // Bits 24:20
    UINT32 vtnoffset                               :  6;  // Bits 30:25
    UINT32 rsvd                                    :  1;  // Bits 31:31
  } A0Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_VSSHITARGET_STRUCT;
typedef union {
  struct {
    UINT32 AlertVref                               :  8;  // Bits 7:0
    UINT32 AlertEn                                 :  1;  // Bits 8:8
    UINT32 AlertCMCap                              :  3;  // Bits 11:9
    UINT32 Spare                                   :  20;  // Bits 31:12
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_DDRCRALERT_STRUCT;
typedef union {
  struct {
    UINT32 DqVsxHiFF                               :  1;  // Bits 0:0
    UINT32 CmdVsxHiFF                              :  1;  // Bits 1:1
    UINT32 CtlVsxHiFF                              :  1;  // Bits 2:2
    UINT32 ClkVsxHiFF                              :  1;  // Bits 3:3
    UINT32 FFCodeCCCDist                           :  1;  // Bits 4:4
    UINT32 FFCodePBD                               :  1;  // Bits 5:5
    UINT32 FFCodeRead                              :  1;  // Bits 6:6
    UINT32 FFCodeWrite                             :  1;  // Bits 7:7
    UINT32 FFCodeWeak                              :  1;  // Bits 8:8
    UINT32 FFCodeIdle                              :  1;  // Bits 9:9
    UINT32 FFCodePi                                :  1;  // Bits 10:10
    UINT32 CodeVtp                                 :  1;  // Bits 11:11
    UINT32 DqsPFwdClk                              :  1;  // Bits 12:12
    UINT32 DqsNFwdClk                              :  1;  // Bits 13:13
    UINT32 FFCodeDqsDly                            :  1;  // Bits 14:14
    UINT32 FFCodeLeak                              :  1;  // Bits 15:15
    UINT32 Spare                                   :  16;  // Bits 31:16
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_DDRCRCOMPOVR1_STRUCT;
typedef union {
  struct {
    UINT32 CompVTarget                             :  7;  // Bits 6:0
    UINT32 ForceCompAmpOn                          :  1;  // Bits 7:7
    UINT32 RstCount                                :  1;  // Bits 8:8
    UINT32 CountMSB                                :  4;  // Bits 12:9
    UINT32 SelectVccDllRail                        :  3;  // Bits 15:13
    UINT32 OffsetBinSearch                         :  2;  // Bits 17:16
    UINT32 CodeLeakSearch                          :  1;  // Bits 18:18
    UINT32 VtpSlope                                :  5;  // Bits 23:19
    INT32  VtpOffset                               :  6;  // Bits 29:24
    UINT32 rsvd                                    :  2;  // Bits 31:30
  } Bits;
  struct {
    UINT32 CompVTarget                             :  7;  // Bits 6:0
    UINT32 ForceCompAmpOn                          :  1;  // Bits 7:7
    UINT32 RstCount                                :  1;  // Bits 8:8
    UINT32 CountMSB                                :  4;  // Bits 12:9
    UINT32 SelectVccDllRail                        :  3;  // Bits 15:13
    UINT32 OffsetBinSearch                         :  2;  // Bits 17:16
    UINT32 CodeLeakSearch                          :  1;  // Bits 18:18
    UINT32 VtpSlope                                :  5;  // Bits 23:19
    UINT32 VtpOffset                               :  6;  // Bits 29:24
    UINT32 rsvd                                    :  2;  // Bits 31:30
  } A0Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_VCCDLLTARGET_STRUCT;
typedef union {
  struct {
    UINT32 TxPBDCode                               :  6;  // Bits 5:0
    UINT32 RxPBDCode                               :  6;  // Bits 11:6
    UINT32 SlaveRxPiCodeP                          :  8;  // Bits 19:12
    UINT32 SlaveRxPiCodeN                          :  8;  // Bits 27:20
    UINT32 SdllSegmentDisable                      :  4;  // Bits 31:28
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_VCCDLLREPLICACTRL0_STRUCT;
typedef union {
  struct {
    UINT32 CCCPBDCode                              :  6;  // Bits 5:0
    UINT32 DisableDataPBDDLGating                  :  1;  // Bits 6:6
    UINT32 DisableCCCPBDDLGating                   :  1;  // Bits 7:7
    INT32  ScaleIdle2Weak                          :  4;  // Bits 11:8
    UINT32 MatchedPath                             :  1;  // Bits 12:12
    UINT32 LocalVsxHiBypass                        :  1;  // Bits 13:13
    UINT32 RloadVref                               :  8;  // Bits 21:14
    UINT32 RloadInstances                          :  6;  // Bits 27:22
    UINT32 RxBiasVref                              :  3;  // Bits 30:28
    UINT32 RxDqsSelIOG                             :  1;  // Bits 31:31
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_VCCDLLREPLICACTRL1_STRUCT;
typedef union {
  struct {
    UINT32 TxDeskewCal                             :  2;  // Bits 1:0
    UINT32 RxDeskewCal                             :  2;  // Bits 3:2
    UINT32 CCCDeskewCal                            :  2;  // Bits 5:4
    UINT32 PbiasCalibration                        :  3;  // Bits 8:6
    UINT32 SdllBwCtrl                              :  4;  // Bits 12:9
    UINT32 SdllPiCB                                :  4;  // Bits 16:13
    UINT32 DisableTxDqs                            :  1;  // Bits 17:17
    UINT32 RxD0PiCB                                :  4;  // Bits 21:18
    UINT32 RxD0BWCtrl                              :  4;  // Bits 25:22
    UINT32 LeakScale                               :  3;  // Bits 28:26
    UINT32 RxPwrMuxSelVdd2                         :  1;  // Bits 29:29
    UINT32 Spare1                                  :  2;  // Bits 31:30
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_VCCDLLREPLICACTRL2_STRUCT;
typedef union {
  struct {
    UINT32 FFCodeWeak                              :  6;  // Bits 5:0
    UINT32 FFCodeIdle                              :  6;  // Bits 11:6
    UINT32 FFCodePi                                :  6;  // Bits 17:12
    UINT32 CodeVtp                                 :  6;  // Bits 23:18
    UINT32 RloadDqs                                :  6;  // Bits 29:24
    UINT32 Spare                                   :  2;  // Bits 31:30
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_VCCDLLCOMPDLL_STRUCT;
typedef union {
  struct {
    UINT32 FFCodeCCCDist                           :  6;  // Bits 5:0
    UINT32 FFCodePBD                               :  6;  // Bits 11:6
    UINT32 FFCodeRead                              :  6;  // Bits 17:12
    UINT32 FFCodeWrite                             :  6;  // Bits 23:18
    UINT32 PanicVttDnLp                            :  8;  // Bits 31:24
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_VCCDLLCOMPDATACCC_STRUCT;
typedef union {
  struct {
    UINT32 DriftLimitLocal                         :  4;  // Bits 3:0
    UINT32 DriftLimitGlobal                        :  8;  // Bits 11:4
    UINT32 TrainTargetOffsetUI                     :  1;  // Bits 12:12
    UINT32 Gear1                                   :  1;  // Bits 13:13
    UINT32 RxPBDCode                               :  6;  // Bits 19:14
    UINT32 RxDqsVref                               :  3;  // Bits 22:20
    UINT32 RxDqsACCap                              :  2;  // Bits 24:23
    UINT32 RxDqsSlope                              :  2;  // Bits 26:25
    UINT32 RxDqsOffsetComp                         :  1;  // Bits 27:27
    UINT32 RxClkDisRep                             :  3;  // Bits 30:28
    UINT32 Spare                                   :  1;  // Bits 31:31
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_VCCDLLDQSDELAY_STRUCT;
typedef union {
  struct {
    UINT32 CCC2FFRefBit3                           :  3;  // Bits 2:0
    UINT32 CCC2FFRefBit4                           :  3;  // Bits 5:3
    UINT32 CCC2FFRefBit5                           :  4;  // Bits 9:6
    UINT32 CCCQFFRefStatic                         :  4;  // Bits 13:10
    UINT32 CCCQFFRefLSB                            :  3;  // Bits 16:14
    UINT32 CCCQFFRefBit2                           :  3;  // Bits 19:17
    UINT32 CCCQFFRefBit3                           :  3;  // Bits 22:20
    UINT32 CCCQFFRefBit4                           :  3;  // Bits 25:23
    UINT32 CCCQFFRefBit5                           :  4;  // Bits 29:26
    UINT32 Rsvd                                    :  2;  // Bits 31:30
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_VSXHIFFCOMPREF0_STRUCT;
typedef union {
  struct {
    UINT32 DQFFRefStatic                           :  4;  // Bits 3:0
    UINT32 DQFFRefLsb                              :  3;  // Bits 6:4
    UINT32 DQFFRefBit2                             :  3;  // Bits 9:7
    UINT32 DQFFRefBit3                             :  3;  // Bits 12:10
    UINT32 DQFFRefBit4                             :  3;  // Bits 15:13
    UINT32 DQFFRefBit5                             :  4;  // Bits 19:16
    UINT32 CCC2FFRefStatic                         :  4;  // Bits 23:20
    UINT32 CCC2FFRefLSB                            :  3;  // Bits 26:24
    UINT32 CCC2FFRefBit2                           :  3;  // Bits 29:27
    UINT32 Rsvd                                    :  2;  // Bits 31:30
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_VSXHIFFCOMPREF1_STRUCT;
typedef union {
  struct {
    UINT32 VsxHiLVRTargetDvfs                      :  7;  // Bits 6:0
    UINT32 VsxHiLVRTargetNormal                    :  7;  // Bits 13:7
    UINT32 VsxHiLVRBias                            :  6;  // Bits 19:14
    UINT32 DvfsRcompNormalOp                       :  1;  // Bits 20:20
    UINT32 DisableVsxHiLVR                         :  1;  // Bits 21:21
    UINT32 Spare                                   :  10;  // Bits 31:22
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_DDRCRCOMPDVFSRLOAD_STRUCT;
typedef union {
  struct {
    UINT32 VsxHiPanicUpVref                        :  7;  // Bits 6:0
    UINT32 VsxHiPanicDnVref                        :  8;  // Bits 14:7
    UINT32 VsxHiPanicCompUpMult                    :  6;  // Bits 20:15
    UINT32 VsxHiPanicCompDnMult                    :  6;  // Bits 26:21
    UINT32 PanicCCCPU                              :  2;  // Bits 28:27
    UINT32 PanicPDn2xStep                          :  1;  // Bits 29:29
    UINT32 PanicCCCPUVssHiBypass                   :  1;  // Bits 30:30
    UINT32 Reserved                                :  1;  // Bits 31:31
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_VSSHIPANIC_STRUCT;
typedef union {
  struct {
    UINT32 VttPanicUpVref                          :  8;  // Bits 7:0
    UINT32 VttPanicDnVref                          :  8;  // Bits 15:8
    UINT32 VttPanicCompUp0Mult                     :  4;  // Bits 19:16
    UINT32 VttPanicCompUp1Mult                     :  4;  // Bits 23:20
    UINT32 VttPanicCompDn0Mult                     :  4;  // Bits 27:24
    UINT32 VttPanicCompDn1Mult                     :  4;  // Bits 31:28
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_DDRCRCOMPVTTPANIC_STRUCT;
typedef union {
  struct {
    UINT32 VttPanicCompDnLpMult                    :  4;  // Bits 3:0
    UINT32 PanicCCCPU                              :  2;  // Bits 5:4
    UINT32 PanicPDn2xStep                          :  1;  // Bits 6:6
    UINT32 Spare                                   :  25;  // Bits 31:7
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_DDRCRCOMPVTTPANIC2_STRUCT;
typedef union {
  struct {
    UINT32 EqDelay                                 :  6;  // Bits 5:0
    UINT32 EqCoeff                                 :  3;  // Bits 8:6
    UINT32 TcoComp0                                :  6;  // Bits 14:9
    UINT32 TcoComp1                                :  6;  // Bits 20:15
    UINT32 WrEnViewDrv                             :  1;  // Bits 21:21
    UINT32 drven                                   :  1;  // Bits 22:22
    UINT32 spare                                   :  9;  // Bits 31:23
  } Bits;
  struct {
    UINT32 EqDelay                                 :  6;  // Bits 5:0
    UINT32 EqCoeff                                 :  3;  // Bits 8:6
    UINT32 TcoComp0                                :  6;  // Bits 14:9
    UINT32 TcoComp1                                :  6;  // Bits 20:15
    UINT32 WrEnViewDrv                             :  1;  // Bits 21:21
    UINT32 HiZ                                     :  1;  // Bits 22:22
    UINT32 spare                                   :  9;  // Bits 31:23
  } A0Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_DDRCRVIEWCTL_STRUCT;
typedef union {
  struct {
    UINT32 FLLCalEnSrc                             :  1;  // Bits 0:0
    UINT32 FLLCalRatioSrc                          :  1;  // Bits 1:1
    UINT32 ForceClkReq                             :  1;  // Bits 2:2
    UINT32 spare1                                  :  2;  // Bits 4:3
    UINT32 FllWireRatio                            :  8;  // Bits 12:5
    UINT32 FllWireCalCode                          :  16;  // Bits 28:13
    UINT32 FllWireCodeVld                          :  1;  // Bits 29:29
    UINT32 Spare                                   :  2;  // Bits 31:30
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_DDRCRFLLWIRED_STRUCT;
typedef union {
  struct {
    INT32  RcompDvfsODTRef                         :  6;  // Bits 5:0
    INT32  RcompDvfsDQRef                          :  6;  // Bits 11:6
    INT32  RcompDvfsCLKRef                         :  6;  // Bits 17:12
    INT32  RcompDvfsCTLRef                         :  6;  // Bits 23:18
    INT32  RcompDvfsCARef                          :  6;  // Bits 29:24
    UINT32 Spare                                   :  2;  // Bits 31:30
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DDRPHY_COMP_CR_DDRCRCOMPDVFSRCOMP_STRUCT;
typedef union {
  struct {
    UINT32 LockThresh                              :  3;  // Bits 2:0
    UINT32 LockCtr                                 :  2;  // Bits 4:3
    UINT32 VctrlDischRate                          :  2;  // Bits 6:5
    UINT32 SelVctrlHi                              :  1;  // Bits 7:7
    UINT32 StartupCntSel                           :  1;  // Bits 8:8
    UINT32 LockSel                                 :  2;  // Bits 10:9
    UINT32 RstOvrd                                 :  1;  // Bits 11:11
    UINT32 SelRstOvrd                              :  1;  // Bits 12:12
    UINT32 TimeOutOvrd                             :  1;  // Bits 13:13
    UINT32 SelTimeOutOvrd                          :  1;  // Bits 14:14
    UINT32 ClkGateOvrd                             :  1;  // Bits 15:15
    UINT32 LockOvrd                                :  1;  // Bits 16:16
    UINT32 SelLockOvrd                             :  1;  // Bits 17:17
    UINT32 OpenLoopOvrd                            :  1;  // Bits 18:18
    UINT32 SelOpenLoopOvrd                         :  1;  // Bits 19:19
    UINT32 WkLockEnOvrd                            :  1;  // Bits 20:20
    UINT32 SelWkLockEnOvrd                         :  1;  // Bits 21:21
    UINT32 CfdlDis                                 :  1;  // Bits 22:22
    UINT32 DftEn                                   :  1;  // Bits 23:23
    UINT32 EnablePiWhenOff                         :  1;  // Bits 24:24
    UINT32 ParkToggle                              :  1;  // Bits 25:25
    UINT32 spare0                                  :  6;  // Bits 31:26
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DLLDDRDATA0_CR_MASTERDLLCFG_STRUCT;
typedef union {
  struct {
    UINT32 DllBWEn                                 :  32;  // Bits 31:0
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DLLDDRDATA0_CR_CBTUNE0_STRUCT;
typedef union {
  struct {
    UINT32 PiCbEn                                  :  24;  // Bits 23:0
    UINT32 CbEnRsvd                                :  3;  // Bits 26:24
    UINT32 CbEnDllFuse                             :  3;  // Bits 29:27
    UINT32 Spare                                   :  2;  // Bits 31:30
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DLLDDRDATA0_CR_CBTUNE1_STRUCT;
typedef union {
  struct {
    UINT32 ADC_frz                                 :  1;  // Bits 0:0
    UINT32 ADC_en                                  :  1;  // Bits 1:1
    UINT32 ADCclkdiv                               :  2;  // Bits 3:2
    UINT32 ADCstartcount                           :  2;  // Bits 5:4
    UINT32 ADCChopEn                               :  1;  // Bits 6:6
    UINT32 Spare                                   :  25;  // Bits 31:7
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DLLDDRDATA0_CR_ADCCFG_STRUCT;
typedef union {
  struct {
    UINT32 DllCbEn                                 :  16;  // Bits 15:0
    UINT32 PbiasLeak0                              :  4;  // Bits 19:16
    UINT32 PbiasLeak1                              :  4;  // Bits 23:20
    UINT32 Spare                                   :  8;  // Bits 31:24
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DLLDDRDATA0_CR_CBTUNE2_STRUCT;
typedef union {
  struct {
    UINT32 PiDftDelay                              :  7;  // Bits 6:0
    UINT32 Ch0PiEnOvrd                             :  1;  // Bits 7:7
    UINT32 Ch1PiEnOvrd                             :  1;  // Bits 8:8
    UINT32 Ch0PiDFTEn                              :  1;  // Bits 9:9
    UINT32 Ch1PiDFTEn                              :  1;  // Bits 10:10
    UINT32 Spare                                   :  4;  // Bits 14:11
    UINT32 RefPiOvrd                               :  1;  // Bits 15:15
    UINT32 Rsvd                                    :  16;  // Bits 31:16
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DLLDDRDATA0_CR_PIDFTDLY_STRUCT;
typedef union {
  struct {
    UINT32 RunTest                                 :  1;  // Bits 0:0
    UINT32 Load                                    :  1;  // Bits 1:1
    UINT32 ModeHVM                                 :  1;  // Bits 2:2
    UINT32 ModeDV                                  :  1;  // Bits 3:3
    UINT32 CalCfdl                                 :  1;  // Bits 4:4
    UINT32 LoadCount                               :  10;  // Bits 14:5
    UINT32 CountStatus                             :  10;  // Bits 24:15
    UINT32 ModeADC                                 :  1;  // Bits 25:25
    UINT32 ADCClkDiv                               :  2;  // Bits 27:26
    UINT32 ADCDdrChanSel                           :  1;  // Bits 28:28
    UINT32 ADCChopEn                               :  1;  // Bits 29:29
    UINT32 ADCDone                                 :  1;  // Bits 30:30
    UINT32 PhaseDrvPwrSavOn                        :  1;  // Bits 31:31
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DLLDDRDATA0_CR_DLLPITESTANDADC_STRUCT;
typedef union {
  struct {
    UINT32 DetrmLockStat                           :  1;  // Bits 0:0
    UINT32 FuncLockStat                            :  1;  // Bits 1:1
    UINT32 Lock                                    :  1;  // Bits 2:2
    UINT32 Timeout                                 :  1;  // Bits 3:3
    UINT32 DllReset                                :  1;  // Bits 4:4
    UINT32 LongLockStat                            :  1;  // Bits 5:5
    UINT32 EarlyLockStat                           :  1;  // Bits 6:6
    UINT32 NormalMode_NotWkLock                    :  1;  // Bits 7:7
    UINT32 ADCout                                  :  10;  // Bits 17:8
    UINT32 ADCStatus                               :  1;  // Bits 18:18
    UINT32 pilags                                  :  1;  // Bits 19:19
    UINT32 spare                                   :  12;  // Bits 31:20
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DLLDDRDATA0_CR_DLLSTATUS_STRUCT;
typedef union {
  struct {
    UINT32 wl_wakecycles                           :  2;  // Bits 1:0
    UINT32 WL_SleepCyclesAct                       :  3;  // Bits 4:2
    UINT32 WL_SleepCyclesLP                        :  3;  // Bits 7:5
    UINT32 DllWeakLock0                            :  1;  // Bits 8:8
    UINT32 DLLMask0                                :  2;  // Bits 10:9
    UINT32 DllWeakLock1                            :  1;  // Bits 11:11
    UINT32 DLLMask1                                :  2;  // Bits 13:12
    INT32  RefPi0                                  :  4;  // Bits 17:14
    INT32  RefPi1                                  :  4;  // Bits 21:18
    UINT32 Spare                                   :  10;  // Bits 31:22
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DLLDDRDATA0_CR_DLLWEAKLOCK_STRUCT;
typedef union {
  struct {
    UINT32 Spare                                   :  2;  // Bits 1:0
    UINT32 Bypass                                  :  1;  // Bits 2:2
    UINT32 LocalVsxHiBypass                        :  1;  // Bits 3:3
    UINT32 FFRcvEnPre                              :  3;  // Bits 6:4
    UINT32 FFRcvEnPi                               :  3;  // Bits 9:7
    UINT32 FFIdleStagger                           :  1;  // Bits 10:10
    UINT32 FFWriteStagger                          :  1;  // Bits 11:11
    UINT32 Spare1                                  :  2;  // Bits 13:12
    UINT32 VccdllPwrMuxSel                         :  1;  // Bits 14:14
    UINT32 VccdllMdllPwrSave                       :  1;  // Bits 15:15
    UINT32 VccdllPiPwrSave                         :  1;  // Bits 16:16
    UINT32 VccdllWritePwrSave                      :  2;  // Bits 18:17
    UINT32 VccdllReadPwrSave                       :  3;  // Bits 21:19
    UINT32 VccdllPbdPwrSave                        :  1;  // Bits 22:22
    UINT32 Spare2                                  :  9;  // Bits 31:23
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DLLDDRDATA0_CR_DDRCRVCCDLLFFCONTROL_STRUCT;
typedef union {
  struct {
    UINT32 NbTarget                                :  7;  // Bits 6:0
    UINT32 NbiasLoad                               :  7;  // Bits 13:7
    UINT32 NbiasFastStartup                        :  1;  // Bits 14:14
    UINT32 NbiasTimer0                             :  2;  // Bits 16:15
    UINT32 NbiasTimer1                             :  2;  // Bits 18:17
    UINT32 NbiasCPVccIOG                           :  1;  // Bits 19:19
    UINT32 NbiasEnLeaker                           :  2;  // Bits 21:20
    UINT32 SideClkPulse                            :  4;  // Bits 25:22
    UINT32 UseFLLDuringDVFS                        :  1;  // Bits 26:26
    UINT32 Spare                                   :  5;  // Bits 31:27
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DLLDDRDATA0_CR_DDRCRVCCDLLFFNBIAS_STRUCT;

typedef DDRVCCDLL0_CR_DDRCRVCCDLLCOMPDLL_STRUCT DLLDDRDATA0_CR_DDRCRVCCDLLCOMPDLL_STRUCT;

typedef DDRPHY_COMP_CR_VCCDLLCOMPDATACCC_STRUCT DLLDDRDATA0_CR_DDRCRVCCDLLCOMPDATACCC_STRUCT;
typedef union {
  struct {
    INT32  FFCodeCCCDistOffset                     :  4;  // Bits 3:0
    INT32  FFCodePBDOffset                         :  5;  // Bits 8:4
    INT32  FFCodeReadOffset                        :  5;  // Bits 13:9
    INT32  FFCodeWriteOffset                       :  5;  // Bits 18:14
    INT32  FFCodeWeakOffset                        :  4;  // Bits 22:19
    INT32  FFCodeIdleOffset                        :  5;  // Bits 27:23
    INT32  FFCodePIOffset                          :  4;  // Bits 31:28
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DLLDDRDATA0_CR_DDRCRVCCDLLCOMPOFFSET_STRUCT;
typedef union {
  struct {
    UINT32 VsxHiFFCodePBD                          :  5;  // Bits 4:0
    UINT32 VsxHiFFCodeRead                         :  7;  // Bits 11:5
    UINT32 VsxHiFFCodeWrite                        :  7;  // Bits 18:12
    UINT32 VsxHiFFCodePi                           :  3;  // Bits 21:19
    UINT32 VsxHiFFCodeIdle                         :  5;  // Bits 26:22
    UINT32 Spare                                   :  5;  // Bits 31:27
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DLLDDRDATA0_CR_DDRCRVCCDLLVSXHIFF_STRUCT;
typedef union {
  struct {
    UINT32 CapCancelCodePBD                        :  3;  // Bits 2:0
    UINT32 CapCancelCodeRead                       :  5;  // Bits 7:3
    UINT32 CapCancelCodeWrite                      :  5;  // Bits 12:8
    UINT32 CapCancelCodePi                         :  3;  // Bits 15:13
    UINT32 CapCancelCodeIdle                       :  5;  // Bits 20:16
    UINT32 Spare                                   :  11;  // Bits 31:21
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DLLDDRDATA0_CR_DDRCRVCCDLLCOUPLINGCAP_STRUCT;
typedef union {
  struct {
    UINT32 PiCbEn                                  :  4;  // Bits 3:0
    UINT32 Spare                                   :  28;  // Bits 31:4
  } Bits;
  UINT32 Data;
  UINT16 Data16[2];
  UINT8  Data8[4];
} DLLDDRDATA0_CR_PITUNE_STRUCT;

typedef DLLDDRDATA0_CR_MASTERDLLCFG_STRUCT DLLDDRDATA1_CR_MASTERDLLCFG_STRUCT;

typedef DLLDDRDATA0_CR_CBTUNE0_STRUCT DLLDDRDATA1_CR_CBTUNE0_STRUCT;

typedef DLLDDRDATA0_CR_CBTUNE1_STRUCT DLLDDRDATA1_CR_CBTUNE1_STRUCT;

typedef DLLDDRDATA0_CR_ADCCFG_STRUCT DLLDDRDATA1_CR_ADCCFG_STRUCT;

typedef DLLDDRDATA0_CR_CBTUNE2_STRUCT DLLDDRDATA1_CR_CBTUNE2_STRUCT;

typedef DLLDDRDATA0_CR_PIDFTDLY_STRUCT DLLDDRDATA1_CR_PIDFTDLY_STRUCT;

typedef DLLDDRDATA0_CR_DLLPITESTANDADC_STRUCT DLLDDRDATA1_CR_DLLPITESTANDADC_STRUCT;

typedef DLLDDRDATA0_CR_DLLSTATUS_STRUCT DLLDDRDATA1_CR_DLLSTATUS_STRUCT;

typedef DLLDDRDATA0_CR_DLLWEAKLOCK_STRUCT DLLDDRDATA1_CR_DLLWEAKLOCK_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLFFCONTROL_STRUCT DLLDDRDATA1_CR_DDRCRVCCDLLFFCONTROL_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLFFNBIAS_STRUCT DLLDDRDATA1_CR_DDRCRVCCDLLFFNBIAS_STRUCT;

typedef DDRVCCDLL0_CR_DDRCRVCCDLLCOMPDLL_STRUCT DLLDDRDATA1_CR_DDRCRVCCDLLCOMPDLL_STRUCT;

typedef DDRPHY_COMP_CR_VCCDLLCOMPDATACCC_STRUCT DLLDDRDATA1_CR_DDRCRVCCDLLCOMPDATACCC_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLCOMPOFFSET_STRUCT DLLDDRDATA1_CR_DDRCRVCCDLLCOMPOFFSET_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLVSXHIFF_STRUCT DLLDDRDATA1_CR_DDRCRVCCDLLVSXHIFF_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLCOUPLINGCAP_STRUCT DLLDDRDATA1_CR_DDRCRVCCDLLCOUPLINGCAP_STRUCT;

typedef DLLDDRDATA0_CR_PITUNE_STRUCT DLLDDRDATA1_CR_PITUNE_STRUCT;

typedef DLLDDRDATA0_CR_MASTERDLLCFG_STRUCT DLLDDRDATA2_CR_MASTERDLLCFG_STRUCT;

typedef DLLDDRDATA0_CR_CBTUNE0_STRUCT DLLDDRDATA2_CR_CBTUNE0_STRUCT;

typedef DLLDDRDATA0_CR_CBTUNE1_STRUCT DLLDDRDATA2_CR_CBTUNE1_STRUCT;

typedef DLLDDRDATA0_CR_ADCCFG_STRUCT DLLDDRDATA2_CR_ADCCFG_STRUCT;

typedef DLLDDRDATA0_CR_CBTUNE2_STRUCT DLLDDRDATA2_CR_CBTUNE2_STRUCT;

typedef DLLDDRDATA0_CR_PIDFTDLY_STRUCT DLLDDRDATA2_CR_PIDFTDLY_STRUCT;

typedef DLLDDRDATA0_CR_DLLPITESTANDADC_STRUCT DLLDDRDATA2_CR_DLLPITESTANDADC_STRUCT;

typedef DLLDDRDATA0_CR_DLLSTATUS_STRUCT DLLDDRDATA2_CR_DLLSTATUS_STRUCT;

typedef DLLDDRDATA0_CR_DLLWEAKLOCK_STRUCT DLLDDRDATA2_CR_DLLWEAKLOCK_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLFFCONTROL_STRUCT DLLDDRDATA2_CR_DDRCRVCCDLLFFCONTROL_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLFFNBIAS_STRUCT DLLDDRDATA2_CR_DDRCRVCCDLLFFNBIAS_STRUCT;

typedef DDRVCCDLL0_CR_DDRCRVCCDLLCOMPDLL_STRUCT DLLDDRDATA2_CR_DDRCRVCCDLLCOMPDLL_STRUCT;

typedef DDRPHY_COMP_CR_VCCDLLCOMPDATACCC_STRUCT DLLDDRDATA2_CR_DDRCRVCCDLLCOMPDATACCC_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLCOMPOFFSET_STRUCT DLLDDRDATA2_CR_DDRCRVCCDLLCOMPOFFSET_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLVSXHIFF_STRUCT DLLDDRDATA2_CR_DDRCRVCCDLLVSXHIFF_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLCOUPLINGCAP_STRUCT DLLDDRDATA2_CR_DDRCRVCCDLLCOUPLINGCAP_STRUCT;

typedef DLLDDRDATA0_CR_PITUNE_STRUCT DLLDDRDATA2_CR_PITUNE_STRUCT;

typedef DLLDDRDATA0_CR_MASTERDLLCFG_STRUCT DLLDDRDATA3_CR_MASTERDLLCFG_STRUCT;

typedef DLLDDRDATA0_CR_CBTUNE0_STRUCT DLLDDRDATA3_CR_CBTUNE0_STRUCT;

typedef DLLDDRDATA0_CR_CBTUNE1_STRUCT DLLDDRDATA3_CR_CBTUNE1_STRUCT;

typedef DLLDDRDATA0_CR_ADCCFG_STRUCT DLLDDRDATA3_CR_ADCCFG_STRUCT;

typedef DLLDDRDATA0_CR_CBTUNE2_STRUCT DLLDDRDATA3_CR_CBTUNE2_STRUCT;

typedef DLLDDRDATA0_CR_PIDFTDLY_STRUCT DLLDDRDATA3_CR_PIDFTDLY_STRUCT;

typedef DLLDDRDATA0_CR_DLLPITESTANDADC_STRUCT DLLDDRDATA3_CR_DLLPITESTANDADC_STRUCT;

typedef DLLDDRDATA0_CR_DLLSTATUS_STRUCT DLLDDRDATA3_CR_DLLSTATUS_STRUCT;

typedef DLLDDRDATA0_CR_DLLWEAKLOCK_STRUCT DLLDDRDATA3_CR_DLLWEAKLOCK_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLFFCONTROL_STRUCT DLLDDRDATA3_CR_DDRCRVCCDLLFFCONTROL_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLFFNBIAS_STRUCT DLLDDRDATA3_CR_DDRCRVCCDLLFFNBIAS_STRUCT;

typedef DDRVCCDLL0_CR_DDRCRVCCDLLCOMPDLL_STRUCT DLLDDRDATA3_CR_DDRCRVCCDLLCOMPDLL_STRUCT;

typedef DDRPHY_COMP_CR_VCCDLLCOMPDATACCC_STRUCT DLLDDRDATA3_CR_DDRCRVCCDLLCOMPDATACCC_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLCOMPOFFSET_STRUCT DLLDDRDATA3_CR_DDRCRVCCDLLCOMPOFFSET_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLVSXHIFF_STRUCT DLLDDRDATA3_CR_DDRCRVCCDLLVSXHIFF_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLCOUPLINGCAP_STRUCT DLLDDRDATA3_CR_DDRCRVCCDLLCOUPLINGCAP_STRUCT;

typedef DLLDDRDATA0_CR_PITUNE_STRUCT DLLDDRDATA3_CR_PITUNE_STRUCT;

typedef DLLDDRDATA0_CR_MASTERDLLCFG_STRUCT DLLDDRDATA4_CR_MASTERDLLCFG_STRUCT;

typedef DLLDDRDATA0_CR_CBTUNE0_STRUCT DLLDDRDATA4_CR_CBTUNE0_STRUCT;

typedef DLLDDRDATA0_CR_CBTUNE1_STRUCT DLLDDRDATA4_CR_CBTUNE1_STRUCT;

typedef DLLDDRDATA0_CR_ADCCFG_STRUCT DLLDDRDATA4_CR_ADCCFG_STRUCT;

typedef DLLDDRDATA0_CR_CBTUNE2_STRUCT DLLDDRDATA4_CR_CBTUNE2_STRUCT;

typedef DLLDDRDATA0_CR_PIDFTDLY_STRUCT DLLDDRDATA4_CR_PIDFTDLY_STRUCT;

typedef DLLDDRDATA0_CR_DLLPITESTANDADC_STRUCT DLLDDRDATA4_CR_DLLPITESTANDADC_STRUCT;

typedef DLLDDRDATA0_CR_DLLSTATUS_STRUCT DLLDDRDATA4_CR_DLLSTATUS_STRUCT;

typedef DLLDDRDATA0_CR_DLLWEAKLOCK_STRUCT DLLDDRDATA4_CR_DLLWEAKLOCK_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLFFCONTROL_STRUCT DLLDDRDATA4_CR_DDRCRVCCDLLFFCONTROL_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLFFNBIAS_STRUCT DLLDDRDATA4_CR_DDRCRVCCDLLFFNBIAS_STRUCT;

typedef DDRVCCDLL0_CR_DDRCRVCCDLLCOMPDLL_STRUCT DLLDDRDATA4_CR_DDRCRVCCDLLCOMPDLL_STRUCT;

typedef DDRPHY_COMP_CR_VCCDLLCOMPDATACCC_STRUCT DLLDDRDATA4_CR_DDRCRVCCDLLCOMPDATACCC_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLCOMPOFFSET_STRUCT DLLDDRDATA4_CR_DDRCRVCCDLLCOMPOFFSET_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLVSXHIFF_STRUCT DLLDDRDATA4_CR_DDRCRVCCDLLVSXHIFF_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLCOUPLINGCAP_STRUCT DLLDDRDATA4_CR_DDRCRVCCDLLCOUPLINGCAP_STRUCT;

typedef DLLDDRDATA0_CR_PITUNE_STRUCT DLLDDRDATA4_CR_PITUNE_STRUCT;

typedef DLLDDRDATA0_CR_MASTERDLLCFG_STRUCT DLLDDRDATA5_CR_MASTERDLLCFG_STRUCT;

typedef DLLDDRDATA0_CR_CBTUNE0_STRUCT DLLDDRDATA5_CR_CBTUNE0_STRUCT;

typedef DLLDDRDATA0_CR_CBTUNE1_STRUCT DLLDDRDATA5_CR_CBTUNE1_STRUCT;

typedef DLLDDRDATA0_CR_ADCCFG_STRUCT DLLDDRDATA5_CR_ADCCFG_STRUCT;

typedef DLLDDRDATA0_CR_CBTUNE2_STRUCT DLLDDRDATA5_CR_CBTUNE2_STRUCT;

typedef DLLDDRDATA0_CR_PIDFTDLY_STRUCT DLLDDRDATA5_CR_PIDFTDLY_STRUCT;

typedef DLLDDRDATA0_CR_DLLPITESTANDADC_STRUCT DLLDDRDATA5_CR_DLLPITESTANDADC_STRUCT;

typedef DLLDDRDATA0_CR_DLLSTATUS_STRUCT DLLDDRDATA5_CR_DLLSTATUS_STRUCT;

typedef DLLDDRDATA0_CR_DLLWEAKLOCK_STRUCT DLLDDRDATA5_CR_DLLWEAKLOCK_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLFFCONTROL_STRUCT DLLDDRDATA5_CR_DDRCRVCCDLLFFCONTROL_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLFFNBIAS_STRUCT DLLDDRDATA5_CR_DDRCRVCCDLLFFNBIAS_STRUCT;

typedef DDRVCCDLL0_CR_DDRCRVCCDLLCOMPDLL_STRUCT DLLDDRDATA5_CR_DDRCRVCCDLLCOMPDLL_STRUCT;

typedef DDRPHY_COMP_CR_VCCDLLCOMPDATACCC_STRUCT DLLDDRDATA5_CR_DDRCRVCCDLLCOMPDATACCC_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLCOMPOFFSET_STRUCT DLLDDRDATA5_CR_DDRCRVCCDLLCOMPOFFSET_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLVSXHIFF_STRUCT DLLDDRDATA5_CR_DDRCRVCCDLLVSXHIFF_STRUCT;

typedef DLLDDRDATA0_CR_DDRCRVCCDLLCOUPLINGCAP_STRUCT DLLDDRDATA5_CR_DDRCRVCCDLLCOUPLINGCAP_STRUCT;

typedef DLLDDRDATA0_CR_PITUNE_STRUCT DLLDDRDATA5_CR_PITUNE_STRUCT;

#pragma pack(pop)
#endif
