#ifndef __MrcMcRegisterIcl1xxx_h__
#define __MrcMcRegisterIcl1xxx_h__
/** @file
  This file was automatically generated. Modify at your own risk.
  Note that no error checking is done in these functions so ensure that the correct values are passed.

@copyright
  Copyright (c) 2010 - 2019 Intel Corporation. All rights reserved
  This software and associated documentation (if any) is furnished
  under a license and may only be used or copied in accordance
  with the terms of the license. Except as permitted by the
  license, no part of this software or documentation may be
  reproduced, stored in a retrieval system, or transmitted in any
  form or by any means without the express written consent of
  Intel Corporation.
  This file contains an 'Intel Peripheral Driver' and is uniquely
  identified as "Intel Reference Module" and is licensed for Intel
  CPUs and chipsets under the terms of your license agreement with
  Intel or your vendor. This file may be modified by the user, subject
  to additional terms of the license agreement.

@par Specification Reference:
**/

#pragma pack(push, 1)


#define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_REG                        (0x00001000)

  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06001000)

  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06061000)

  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C1000)

  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06121000)

  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07181000)

  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F1000)

#define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00001004)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06001004)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06061004)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C1004)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06121004)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06181004)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E1004)

#define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00001008)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06001008)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06061008)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C1008)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06121008)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06181008)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E1008)

#define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_REG                       (0x0000100C)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x0600100C)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x0606100C)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C100C)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x0612100C)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x0618100C)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E100C)

#define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00001010)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06001010)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06061010)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C1010)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06121010)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06181010)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E1010)

#define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00001014)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06001014)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06061014)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C1014)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06121014)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06181014)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E1014)

#define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00001018)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06001018)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06061018)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C1018)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06121018)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02181018)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A1018)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D1018)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E1018)

#define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_REG                       (0x0000101C)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x0600101C)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x0606101C)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C101C)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x0612101C)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x0618101C)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E101C)

#define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_REG                       (0x00001020)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x06001020)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x06061020)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C1020)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x06121020)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x06181020)

  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA5CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E1020)

#define DDRDATA5CH0_CR_DCCDATADCCPILUT0_REG                            (0x00001024)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x06001024)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x06061024)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C1024)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x06121024)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x06181024)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E1024)

#define DDRDATA5CH0_CR_DCCDATADCCPILUT1_REG                            (0x00001028)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x06001028)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x06061028)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C1028)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x06121028)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x06181028)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E1028)

#define DDRDATA5CH0_CR_DCCDATADCCPILUT2_REG                            (0x0000102C)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x0600102C)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x0606102C)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C102C)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x0612102C)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x0618102C)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E102C)

#define DDRDATA5CH0_CR_DCCDATADCCPILUT3_REG                            (0x00001030)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x06001030)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x06061030)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C1030)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x06121030)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x06181030)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E1030)

#define DDRDATA5CH0_CR_DCCDATADCCPILUT4_REG                            (0x00001034)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x06001034)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x06061034)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C1034)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x06121034)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x06181034)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E1034)

#define DDRDATA5CH0_CR_DCCDATADCCPILUT5_REG                            (0x00001038)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x06001038)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x06061038)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C1038)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x06121038)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x06181038)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E1038)

#define DDRDATA5CH0_CR_DCCDATADCCPILUT6_REG                            (0x0000103C)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x0600103C)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x0606103C)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C103C)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x0612103C)

  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x0818103C)

#define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_REG                        (0x00001040)

  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x06001040)

  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x06061040)

  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C1040)

  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x06121040)

  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x06181040)

  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E1040)

#define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_REG                        (0x00001044)

  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x06001044)

  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x06061044)

  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C1044)

  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x06121044)

  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x06181044)

  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E1044)

#define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x00001048)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x06001048)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x06061048)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C1048)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x06121048)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x02181048)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A1048)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C1048)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E1048)

#define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x0000104C)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x0600104C)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x0606104C)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C104C)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x0612104C)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x0818104C)

#define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x00001050)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x06001050)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x06061050)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C1050)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x06121050)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x06181050)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E1050)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F1050)

#define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x00001054)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x06001054)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x06061054)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C1054)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x06121054)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x06181054)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E1054)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F1054)

#define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x00001058)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x06001058)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x06061058)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C1058)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x06121058)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x06181058)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E1058)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F1058)

#define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x0000105C)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x0600105C)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x0606105C)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C105C)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x0612105C)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x0618105C)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E105C)

  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F105C)

#define DDRDATA5CH1_CR_RXCONTROL0RANK0_REG                             (0x00001080)

  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B001080)

  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B1080)

  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07121080)

  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07191080)

#define DDRDATA5CH1_CR_RXCONTROL0RANK1_REG                             (0x00001084)

  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B001084)

  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B1084)

  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07121084)

  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07191084)

#define DDRDATA5CH1_CR_RXCONTROL0RANK2_REG                             (0x00001088)

  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B001088)

  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B1088)

  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07121088)

  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07191088)

#define DDRDATA5CH1_CR_RXCONTROL0RANK3_REG                             (0x0000108C)

  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B00108C)

  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B108C)

  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x0712108C)

  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x0719108C)

#define DDRDATA5CH1_CR_RXCONTROL1RANK0_REG                             (0x00001090)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06001090)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06061090)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C1090)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06121090)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02181090)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A1090)

#define DDRDATA5CH1_CR_RXCONTROL1RANK1_REG                             (0x00001094)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06001094)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06061094)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C1094)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06121094)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02181094)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A1094)

#define DDRDATA5CH1_CR_RXCONTROL1RANK2_REG                             (0x00001098)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06001098)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06061098)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C1098)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06121098)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02181098)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A1098)

#define DDRDATA5CH1_CR_RXCONTROL1RANK3_REG                             (0x0000109C)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x0600109C)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x0606109C)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C109C)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x0612109C)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x0218109C)

  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A109C)

#define DDRDATA5CH1_CR_TXTRAINRANK0_REG                                (0x000010A0)

  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A0010A0)

  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A10A0)

  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxEqualization_HSH               (0x061410A0)

  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A10A0)

  #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E10A0)

#define DDRDATA5CH1_CR_TXTRAINRANK1_REG                                (0x000010A4)

  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A0010A4)

  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A10A4)

  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxEqualization_HSH               (0x061410A4)

  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A10A4)

  #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C10A4)

#define DDRDATA5CH1_CR_TXTRAINRANK2_REG                                (0x000010A8)

  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A0010A8)

  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A10A8)

  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_TxEqualization_HSH               (0x061410A8)

  #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A10A8)

#define DDRDATA5CH1_CR_TXTRAINRANK3_REG                                (0x000010AC)

  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A0010AC)

  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A10AC)

  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_TxEqualization_HSH               (0x061410AC)

  #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA5CH1_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A10AC)

#define DDRDATA5CH1_CR_TXPERBITLOWRANK0_REG                            (0x000010B0)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x060010B0)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x060610B0)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C10B0)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x061210B0)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x081810B0)

#define DDRDATA5CH1_CR_TXPERBITLOWRANK1_REG                            (0x000010B4)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x060010B4)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x060610B4)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C10B4)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x061210B4)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x081810B4)

#define DDRDATA5CH1_CR_TXPERBITLOWRANK2_REG                            (0x000010B8)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x060010B8)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x060610B8)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C10B8)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x061210B8)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x081810B8)

#define DDRDATA5CH1_CR_TXPERBITLOWRANK3_REG                            (0x000010BC)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x060010BC)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x060610BC)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C10BC)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x061210BC)

  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x081810BC)

#define DDRDATA5CH1_CR_RCOMPDATA0_REG                                  (0x000010C0)

  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x060010C0)

  #define DDRDATA5CH1_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA5CH1_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA5CH1_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA5CH1_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA5CH1_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA5CH1_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA5CH1_CR_RCOMPDATA0_Rsvd_HSH                           (0x080610C0)

  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA5CH1_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E10C0)

  #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA5CH1_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x051410C0)

  #define DDRDATA5CH1_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA5CH1_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA5CH1_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA5CH1_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA5CH1_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA5CH1_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA5CH1_CR_RCOMPDATA0_Spare_HSH                          (0x071910C0)

#define DDRDATA5CH1_CR_RCOMPDATA1_REG                                  (0x000010C4)

  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x060010C4)

  #define DDRDATA5CH1_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA5CH1_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA5CH1_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA5CH1_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA5CH1_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA5CH1_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA5CH1_CR_RCOMPDATA1_spare_HSH                          (0x140610C4)

  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA5CH1_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A10C4)

#define DDRDATA5CH1_CR_DDRCRDATACONTROL8_REG                           (0x000010C8)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x020010C8)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x020210C8)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x020410C8)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x020610C8)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x010810C8)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL8_spare_HSH                   (0x170910C8)

#define DDRDATA5CH1_CR_RCOMPDATA2_REG                                  (0x000010CC)

  #define DDRDATA5CH1_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA5CH1_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA5CH1_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA5CH1_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA5CH1_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA5CH1_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x080010CC)

  #define DDRDATA5CH1_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA5CH1_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA5CH1_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA5CH1_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA5CH1_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA5CH1_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x080810CC)

  #define DDRDATA5CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA5CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA5CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA5CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA5CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA5CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x061010CC)

  #define DDRDATA5CH1_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA5CH1_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA5CH1_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA5CH1_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA5CH1_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA5CH1_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA5CH1_CR_RCOMPDATA2_Spare_HSH                          (0x0A1610CC)

#define DDRDATA5CH1_CR_RXCONTROL2RANK0_REG                             (0x000010D0)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x060010D0)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x060610D0)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C10D0)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x051110D0)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x051610D0)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B10D0)

#define DDRDATA5CH1_CR_RXCONTROL2RANK1_REG                             (0x000010D4)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x060010D4)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x060610D4)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C10D4)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x051110D4)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x051610D4)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B10D4)

#define DDRDATA5CH1_CR_RXCONTROL2RANK2_REG                             (0x000010D8)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x060010D8)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x060610D8)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C10D8)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x051110D8)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x051610D8)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B10D8)

#define DDRDATA5CH1_CR_RXCONTROL2RANK3_REG                             (0x000010DC)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x060010DC)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x060610DC)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C10DC)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x051110DC)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x051610DC)

  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B10DC)

#define DDRDATA5CH1_CR_DATATRAINFEEDBACK_REG                           (0x000010E0)

  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x090010E0)

  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA5CH1_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x170910E0)

#define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_REG                         (0x000010E8)

  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x860010E8)

  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x860610E8)

  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C10E8)

  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x851110E8)

  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x051610E8)

  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B10E8)

#define DDRDATA5CH1_CR_DDRCRDATACONTROL1_REG                           (0x000010EC)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x840010EC)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x020410EC)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x010610EC)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x030710EC)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A10EC)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E10EC)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x031310EC)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x851610EC)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B10EC)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E10EC)

#define DDRDATA5CH1_CR_DDRCRDATACONTROL2_REG                           (0x000010F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x050010F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x010510F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x010610F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x010710F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x010810F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x040910F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D10F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x011210F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x011310F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x011410F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x011510F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x011610F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x011710F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x011810F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x011910F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A10F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D10F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E10F0)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F10F0)

#define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x000010FC)

  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x860010FC)

  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x870610FC)

  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D10FC)

  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x861310FC)

  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x871910FC)

#define DDRDATA5CH1_CR_DDRCRDATACONTROL0_REG                           (0x00001100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01001100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01011100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01021100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01031100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01041100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01051100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01061100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01071100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01081100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01091100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A1100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B1100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C1100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D1100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F1100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02131100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01151100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01161100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01171100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01181100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01191100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A1100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B1100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C1100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D1100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E1100)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F1100)

#define DDRDATA5CH1_CR_DDRCRDATACONTROL3_REG                           (0x00001108)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04001108)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02041108)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01061108)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01071108)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86081108)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E1108)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F1108)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03101108)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01131108)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03141108)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01171108)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01181108)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01191108)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A1108)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E1108)

#define DDRDATA5CH1_CR_DDRCRDATACONTROL4_REG                           (0x0000110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x0100110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x0101110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x0302110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x0105110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x0106110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x0107110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x0108110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x0209110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x0110110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x0111110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x0112110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x0513110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x0518110C)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_spare2_OFF                  (29)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_spare2_WID                  ( 3)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_spare2_MSK                  (0xE0000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_spare2_MIN                  (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_spare2_MAX                  (7) // 0x00000007
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_spare2_DEF                  (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL4_spare2_HSH                  (0x031D110C)

#define DDRDATA5CH1_CR_DDRCRDATACONTROL5_REG                           (0x00001110)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08001110)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01081110)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02091110)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B1110)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F1110)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08101110)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08181110)

#define DDRDATA5CH1_CR_DDRCRDATACONTROL6_REG                           (0x00001114)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01001114)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02011114)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01031114)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05041114)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01091114)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A1114)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B1114)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C1114)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E1114)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F1114)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08101114)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01181114)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01191114)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A1114)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D1114)

#define DDRDATA5CH1_CR_DDRCRDATACONTROL7_REG                           (0x00001118)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06001118)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06061118)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C1118)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06121118)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04181118)

  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA5CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C1118)

#define DDRDATA5CH1_CR_DELTADQSRANK0_REG                               (0x0000111C)

  #define DDRDATA5CH1_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA5CH1_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA5CH1_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA5CH1_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA5CH1_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA5CH1_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A00111C)

  #define DDRDATA5CH1_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA5CH1_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA5CH1_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA5CH1_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA5CH1_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA5CH1_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA5CH1_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A111C)

#define DDRDATA5CH1_CR_DELTADQSRANK1_REG                               (0x00001120)

  #define DDRDATA5CH1_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA5CH1_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA5CH1_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA5CH1_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA5CH1_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA5CH1_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A001120)

  #define DDRDATA5CH1_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA5CH1_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA5CH1_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA5CH1_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA5CH1_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA5CH1_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA5CH1_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A1120)

#define DDRDATA5CH1_CR_DELTADQSRANK2_REG                               (0x00001124)

  #define DDRDATA5CH1_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA5CH1_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA5CH1_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA5CH1_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA5CH1_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA5CH1_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A001124)

  #define DDRDATA5CH1_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA5CH1_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA5CH1_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA5CH1_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA5CH1_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA5CH1_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA5CH1_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A1124)

#define DDRDATA5CH1_CR_DELTADQSRANK3_REG                               (0x00001128)

  #define DDRDATA5CH1_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA5CH1_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA5CH1_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA5CH1_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA5CH1_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA5CH1_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A001128)

  #define DDRDATA5CH1_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA5CH1_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA5CH1_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA5CH1_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA5CH1_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA5CH1_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA5CH1_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A1128)

#define DDRDATA5CH1_CR_RXCONTROL3RANK0_REG                             (0x0000112C)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x0600112C)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x0606112C)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C112C)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x0511112C)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x0516112C)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B112C)

#define DDRDATA5CH1_CR_RXCONTROL3RANK1_REG                             (0x00001130)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x06001130)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x06061130)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C1130)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x05111130)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x05161130)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B1130)

#define DDRDATA5CH1_CR_RXCONTROL3RANK2_REG                             (0x00001134)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x06001134)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x06061134)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C1134)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x05111134)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x05161134)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B1134)

#define DDRDATA5CH1_CR_RXCONTROL3RANK3_REG                             (0x00001138)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x06001138)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x06061138)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C1138)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x05111138)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x05161138)

  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B1138)

#define DDRDATA5CH1_CR_TXPERBITHIRANK0_REG                             (0x0000113C)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x0600113C)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x0606113C)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C113C)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x0612113C)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK0_Spare_HSH                     (0x0818113C)

#define DDRDATA5CH1_CR_TXPERBITHIRANK1_REG                             (0x00001140)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x06001140)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x06061140)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C1140)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x06121140)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK1_Spare_HSH                     (0x08181140)

#define DDRDATA5CH1_CR_TXPERBITHIRANK2_REG                             (0x00001144)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x06001144)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x06061144)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C1144)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x06121144)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK2_Spare_HSH                     (0x08181144)

#define DDRDATA5CH1_CR_TXPERBITHIRANK3_REG                             (0x00001148)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x06001148)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x06061148)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C1148)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x06121148)

  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_TXPERBITHIRANK3_Spare_HSH                     (0x08181148)

#define DDRDATA5CH1_CR_DCCDATACONTROL0_REG                             (0x0000114C)

  #define DDRDATA5CH1_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x0100114C)

  #define DDRDATA5CH1_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x0201114C)

  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x0103114C)

  #define DDRDATA5CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x0204114C)

  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x0706114C)

  #define DDRDATA5CH1_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D114C)

  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA5CH1_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C114C)

#define DDRDATA5CH1_CR_DCCDATACONTROL1_REG                             (0x00001150)

  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x06001150)

  #define DDRDATA5CH1_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x02061150)

  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x04081150)

  #define DDRDATA5CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C1150)

  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E1150)

  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F1150)

  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F101150)

  #define DDRDATA5CH1_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F1150)

#define DDRDATA5CH1_CR_DCCDATACONTROL2_REG                             (0x00001154)

  #define DDRDATA5CH1_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x06001154)

  #define DDRDATA5CH1_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x03061154)

  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D091154)

  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x05161154)

  #define DDRDATA5CH1_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B1154)

  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C1154)

#define DDRDATA5CH1_CR_DCCDATACONTROL3_REG                             (0x00001158)

  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B001158)

  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B1158)

  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x09141158)

  #define DDRDATA5CH1_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D1158)

#define DDRDATA5CH1_CR_DCCDATACONTROL4_REG                             (0x0000115C)

  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x0900115C)

  #define DDRDATA5CH1_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_Spare_HSH                     (0x0109115C)

  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A115C)

  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x0610115C)

  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x0616115C)

  #define DDRDATA5CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C115C)

#define DDRDATA5CH1_CR_DCCDATACONTROL5_REG                             (0x00001160)

  #define DDRDATA5CH1_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_Spare_HSH                     (0x02001160)

  #define DDRDATA5CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x01021160)

  #define DDRDATA5CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x06031160)

  #define DDRDATA5CH1_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x05091160)

  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E1160)

  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B141160)

  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F1160)

#define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_REG                         (0x00001164)

  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B001164)

  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B1164)

  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x09141164)

  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D1164)

#define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_REG                         (0x00001168)

  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x09001168)

  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x01091168)

  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A1168)

  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B1168)

  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A1168)

  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B1168)

#define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_REG                         (0x0000116C)

  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x1000116C)

  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x0710116C)

  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x0717116C)

  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E116C)

#define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x00001170)

  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B001170)

  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B1170)

  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C1170)

#define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x00001174)

  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x09001174)

  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x11091174)

  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A1174)

#define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x00001178)

  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x09001178)

  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x11091178)

  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A1178)

#define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x0000117C)

  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x0900117C)

  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x1109117C)

  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A117C)

#define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_REG                        (0x00001180)

  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06001180)

  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06061180)

  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C1180)

  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06121180)

  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07181180)

  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F1180)

#define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00001184)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06001184)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06061184)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C1184)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06121184)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06181184)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E1184)

#define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00001188)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06001188)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06061188)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C1188)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06121188)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06181188)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E1188)

#define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_REG                       (0x0000118C)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x0600118C)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x0606118C)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C118C)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x0612118C)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x0618118C)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E118C)

#define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00001190)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06001190)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06061190)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C1190)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06121190)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06181190)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E1190)

#define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00001194)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06001194)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06061194)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C1194)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06121194)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06181194)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E1194)

#define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00001198)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06001198)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06061198)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C1198)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06121198)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02181198)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A1198)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D1198)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E1198)

#define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_REG                       (0x0000119C)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x0600119C)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x0606119C)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C119C)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x0612119C)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x0618119C)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E119C)

#define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_REG                       (0x000011A0)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x060011A0)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x060611A0)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C11A0)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x061211A0)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x061811A0)

  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA5CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E11A0)

#define DDRDATA5CH1_CR_DCCDATADCCPILUT0_REG                            (0x000011A4)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x060011A4)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x060611A4)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C11A4)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x061211A4)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x061811A4)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E11A4)

#define DDRDATA5CH1_CR_DCCDATADCCPILUT1_REG                            (0x000011A8)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x060011A8)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x060611A8)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C11A8)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x061211A8)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x061811A8)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E11A8)

#define DDRDATA5CH1_CR_DCCDATADCCPILUT2_REG                            (0x000011AC)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x060011AC)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x060611AC)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C11AC)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x061211AC)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x061811AC)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E11AC)

#define DDRDATA5CH1_CR_DCCDATADCCPILUT3_REG                            (0x000011B0)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x060011B0)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x060611B0)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C11B0)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x061211B0)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x061811B0)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E11B0)

#define DDRDATA5CH1_CR_DCCDATADCCPILUT4_REG                            (0x000011B4)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x060011B4)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x060611B4)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C11B4)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x061211B4)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x061811B4)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E11B4)

#define DDRDATA5CH1_CR_DCCDATADCCPILUT5_REG                            (0x000011B8)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x060011B8)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x060611B8)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C11B8)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x061211B8)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x061811B8)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E11B8)

#define DDRDATA5CH1_CR_DCCDATADCCPILUT6_REG                            (0x000011BC)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x060011BC)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x060611BC)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C11BC)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x061211BC)

  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH1_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x081811BC)

#define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_REG                        (0x000011C0)

  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x060011C0)

  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x060611C0)

  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C11C0)

  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x061211C0)

  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x061811C0)

  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E11C0)

#define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_REG                        (0x000011C4)

  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x060011C4)

  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x060611C4)

  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C11C4)

  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x061211C4)

  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x061811C4)

  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E11C4)

#define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x000011C8)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x060011C8)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x060611C8)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C11C8)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x061211C8)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x021811C8)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A11C8)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C11C8)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E11C8)

#define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x000011CC)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x060011CC)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x060611CC)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C11CC)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x061211CC)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x081811CC)

#define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x000011D0)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x060011D0)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x060611D0)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C11D0)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x061211D0)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x061811D0)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E11D0)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F11D0)

#define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x000011D4)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x060011D4)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x060611D4)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C11D4)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x061211D4)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x061811D4)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E11D4)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F11D4)

#define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x000011D8)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x060011D8)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x060611D8)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C11D8)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x061211D8)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x061811D8)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E11D8)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F11D8)

#define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x000011DC)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x060011DC)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x060611DC)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C11DC)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x061211DC)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x061811DC)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E11DC)

  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA5CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F11DC)

#define DDRDATA6CH0_CR_RXCONTROL0RANK0_REG                             (0x00001200)

  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B001200)

  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B1200)

  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07121200)

  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07191200)

#define DDRDATA6CH0_CR_RXCONTROL0RANK1_REG                             (0x00001204)

  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B001204)

  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B1204)

  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07121204)

  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07191204)

#define DDRDATA6CH0_CR_RXCONTROL0RANK2_REG                             (0x00001208)

  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B001208)

  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B1208)

  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07121208)

  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07191208)

#define DDRDATA6CH0_CR_RXCONTROL0RANK3_REG                             (0x0000120C)

  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B00120C)

  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B120C)

  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x0712120C)

  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x0719120C)

#define DDRDATA6CH0_CR_RXCONTROL1RANK0_REG                             (0x00001210)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06001210)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06061210)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C1210)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06121210)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02181210)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A1210)

#define DDRDATA6CH0_CR_RXCONTROL1RANK1_REG                             (0x00001214)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06001214)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06061214)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C1214)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06121214)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02181214)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A1214)

#define DDRDATA6CH0_CR_RXCONTROL1RANK2_REG                             (0x00001218)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06001218)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06061218)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C1218)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06121218)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02181218)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A1218)

#define DDRDATA6CH0_CR_RXCONTROL1RANK3_REG                             (0x0000121C)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x0600121C)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x0606121C)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C121C)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x0612121C)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x0218121C)

  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A121C)

#define DDRDATA6CH0_CR_TXTRAINRANK0_REG                                (0x00001220)

  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A001220)

  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A1220)

  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxEqualization_HSH               (0x06141220)

  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A1220)

  #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E1220)

#define DDRDATA6CH0_CR_TXTRAINRANK1_REG                                (0x00001224)

  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A001224)

  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A1224)

  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxEqualization_HSH               (0x06141224)

  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A1224)

  #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C1224)

#define DDRDATA6CH0_CR_TXTRAINRANK2_REG                                (0x00001228)

  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A001228)

  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A1228)

  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_TxEqualization_HSH               (0x06141228)

  #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A1228)

#define DDRDATA6CH0_CR_TXTRAINRANK3_REG                                (0x0000122C)

  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A00122C)

  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A122C)

  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_TxEqualization_HSH               (0x0614122C)

  #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA6CH0_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A122C)

#define DDRDATA6CH0_CR_TXPERBITLOWRANK0_REG                            (0x00001230)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x06001230)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x06061230)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C1230)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x06121230)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x08181230)

#define DDRDATA6CH0_CR_TXPERBITLOWRANK1_REG                            (0x00001234)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x06001234)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x06061234)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C1234)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x06121234)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x08181234)

#define DDRDATA6CH0_CR_TXPERBITLOWRANK2_REG                            (0x00001238)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x06001238)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x06061238)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C1238)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x06121238)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x08181238)

#define DDRDATA6CH0_CR_TXPERBITLOWRANK3_REG                            (0x0000123C)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x0600123C)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x0606123C)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C123C)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x0612123C)

  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x0818123C)

#define DDRDATA6CH0_CR_RCOMPDATA0_REG                                  (0x00001240)

  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x06001240)

  #define DDRDATA6CH0_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA6CH0_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA6CH0_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA6CH0_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA6CH0_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA6CH0_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA6CH0_CR_RCOMPDATA0_Rsvd_HSH                           (0x08061240)

  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA6CH0_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E1240)

  #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA6CH0_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x05141240)

  #define DDRDATA6CH0_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA6CH0_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA6CH0_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA6CH0_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA6CH0_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA6CH0_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA6CH0_CR_RCOMPDATA0_Spare_HSH                          (0x07191240)

#define DDRDATA6CH0_CR_RCOMPDATA1_REG                                  (0x00001244)

  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x06001244)

  #define DDRDATA6CH0_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA6CH0_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA6CH0_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA6CH0_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA6CH0_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA6CH0_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA6CH0_CR_RCOMPDATA1_spare_HSH                          (0x14061244)

  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA6CH0_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A1244)

#define DDRDATA6CH0_CR_DDRCRDATACONTROL8_REG                           (0x00001248)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x02001248)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x02021248)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x02041248)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x02061248)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x01081248)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL8_spare_HSH                   (0x17091248)

#define DDRDATA6CH0_CR_RCOMPDATA2_REG                                  (0x0000124C)

  #define DDRDATA6CH0_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA6CH0_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA6CH0_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA6CH0_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA6CH0_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA6CH0_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x0800124C)

  #define DDRDATA6CH0_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA6CH0_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA6CH0_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA6CH0_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA6CH0_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA6CH0_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x0808124C)

  #define DDRDATA6CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA6CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA6CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA6CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA6CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA6CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x0610124C)

  #define DDRDATA6CH0_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA6CH0_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA6CH0_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA6CH0_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA6CH0_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA6CH0_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA6CH0_CR_RCOMPDATA2_Spare_HSH                          (0x0A16124C)

#define DDRDATA6CH0_CR_RXCONTROL2RANK0_REG                             (0x00001250)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x06001250)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x06061250)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C1250)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x05111250)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x05161250)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B1250)

#define DDRDATA6CH0_CR_RXCONTROL2RANK1_REG                             (0x00001254)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x06001254)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x06061254)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C1254)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x05111254)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x05161254)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B1254)

#define DDRDATA6CH0_CR_RXCONTROL2RANK2_REG                             (0x00001258)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x06001258)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x06061258)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C1258)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x05111258)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x05161258)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B1258)

#define DDRDATA6CH0_CR_RXCONTROL2RANK3_REG                             (0x0000125C)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x0600125C)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x0606125C)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C125C)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x0511125C)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x0516125C)

  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B125C)

#define DDRDATA6CH0_CR_DATATRAINFEEDBACK_REG                           (0x00001260)

  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x09001260)

  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA6CH0_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x17091260)

#define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_REG                         (0x00001268)

  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x86001268)

  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x86061268)

  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C1268)

  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x85111268)

  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x05161268)

  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B1268)

#define DDRDATA6CH0_CR_DDRCRDATACONTROL1_REG                           (0x0000126C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x8400126C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x0204126C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x0106126C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x0307126C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A126C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E126C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x0313126C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x8516126C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B126C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E126C)

#define DDRDATA6CH0_CR_DDRCRDATACONTROL2_REG                           (0x00001270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x05001270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x01051270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x01061270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x01071270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x01081270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x04091270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D1270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x01121270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x01131270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x01141270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x01151270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x01161270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x01171270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x01181270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x01191270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A1270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D1270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E1270)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F1270)

#define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x0000127C)

  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x8600127C)

  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x8706127C)

  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D127C)

  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x8613127C)

  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x8719127C)

#define DDRDATA6CH0_CR_DDRCRDATACONTROL0_REG                           (0x00001280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01001280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01011280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01021280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01031280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01041280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01051280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01061280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01071280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01081280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01091280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A1280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B1280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C1280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D1280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F1280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02131280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01151280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01161280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01171280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01181280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01191280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A1280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B1280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C1280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D1280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E1280)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F1280)

#define DDRDATA6CH0_CR_DDRCRDATACONTROL3_REG                           (0x00001288)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04001288)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02041288)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01061288)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01071288)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86081288)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E1288)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F1288)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03101288)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01131288)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03141288)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01171288)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01181288)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01191288)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A1288)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E1288)

#define DDRDATA6CH0_CR_DDRCRDATACONTROL4_REG                           (0x0000128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x0100128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x0101128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x0302128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x0105128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x0106128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x0107128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x0108128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x0209128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x0110128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x0111128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x0112128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x0513128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x0518128C)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_spare2_OFF                  (29)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_spare2_WID                  ( 3)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_spare2_MSK                  (0xE0000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_spare2_MIN                  (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_spare2_MAX                  (7) // 0x00000007
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_spare2_DEF                  (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL4_spare2_HSH                  (0x031D128C)

#define DDRDATA6CH0_CR_DDRCRDATACONTROL5_REG                           (0x00001290)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08001290)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01081290)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02091290)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B1290)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F1290)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08101290)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08181290)

#define DDRDATA6CH0_CR_DDRCRDATACONTROL6_REG                           (0x00001294)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01001294)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02011294)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01031294)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05041294)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01091294)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A1294)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B1294)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C1294)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E1294)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F1294)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08101294)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01181294)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01191294)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A1294)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D1294)

#define DDRDATA6CH0_CR_DDRCRDATACONTROL7_REG                           (0x00001298)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06001298)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06061298)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C1298)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06121298)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04181298)

  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA6CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C1298)

#define DDRDATA6CH0_CR_DELTADQSRANK0_REG                               (0x0000129C)

  #define DDRDATA6CH0_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA6CH0_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA6CH0_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA6CH0_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA6CH0_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA6CH0_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A00129C)

  #define DDRDATA6CH0_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA6CH0_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA6CH0_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA6CH0_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA6CH0_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA6CH0_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA6CH0_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A129C)

#define DDRDATA6CH0_CR_DELTADQSRANK1_REG                               (0x000012A0)

  #define DDRDATA6CH0_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA6CH0_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA6CH0_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA6CH0_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA6CH0_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA6CH0_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A0012A0)

  #define DDRDATA6CH0_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA6CH0_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA6CH0_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA6CH0_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA6CH0_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA6CH0_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA6CH0_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A12A0)

#define DDRDATA6CH0_CR_DELTADQSRANK2_REG                               (0x000012A4)

  #define DDRDATA6CH0_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA6CH0_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA6CH0_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA6CH0_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA6CH0_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA6CH0_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A0012A4)

  #define DDRDATA6CH0_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA6CH0_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA6CH0_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA6CH0_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA6CH0_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA6CH0_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA6CH0_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A12A4)

#define DDRDATA6CH0_CR_DELTADQSRANK3_REG                               (0x000012A8)

  #define DDRDATA6CH0_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA6CH0_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA6CH0_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA6CH0_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA6CH0_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA6CH0_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A0012A8)

  #define DDRDATA6CH0_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA6CH0_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA6CH0_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA6CH0_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA6CH0_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA6CH0_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA6CH0_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A12A8)

#define DDRDATA6CH0_CR_RXCONTROL3RANK0_REG                             (0x000012AC)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x060012AC)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x060612AC)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C12AC)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x051112AC)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x051612AC)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B12AC)

#define DDRDATA6CH0_CR_RXCONTROL3RANK1_REG                             (0x000012B0)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x060012B0)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x060612B0)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C12B0)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x051112B0)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x051612B0)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B12B0)

#define DDRDATA6CH0_CR_RXCONTROL3RANK2_REG                             (0x000012B4)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x060012B4)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x060612B4)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C12B4)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x051112B4)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x051612B4)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B12B4)

#define DDRDATA6CH0_CR_RXCONTROL3RANK3_REG                             (0x000012B8)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x060012B8)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x060612B8)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C12B8)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x051112B8)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x051612B8)

  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B12B8)

#define DDRDATA6CH0_CR_TXPERBITHIRANK0_REG                             (0x000012BC)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x060012BC)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x060612BC)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C12BC)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x061212BC)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK0_Spare_HSH                     (0x081812BC)

#define DDRDATA6CH0_CR_TXPERBITHIRANK1_REG                             (0x000012C0)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x060012C0)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x060612C0)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C12C0)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x061212C0)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK1_Spare_HSH                     (0x081812C0)

#define DDRDATA6CH0_CR_TXPERBITHIRANK2_REG                             (0x000012C4)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x060012C4)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x060612C4)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C12C4)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x061212C4)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK2_Spare_HSH                     (0x081812C4)

#define DDRDATA6CH0_CR_TXPERBITHIRANK3_REG                             (0x000012C8)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x060012C8)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x060612C8)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C12C8)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x061212C8)

  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_TXPERBITHIRANK3_Spare_HSH                     (0x081812C8)

#define DDRDATA6CH0_CR_DCCDATACONTROL0_REG                             (0x000012CC)

  #define DDRDATA6CH0_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x010012CC)

  #define DDRDATA6CH0_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x020112CC)

  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x010312CC)

  #define DDRDATA6CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x020412CC)

  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x070612CC)

  #define DDRDATA6CH0_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D12CC)

  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA6CH0_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C12CC)

#define DDRDATA6CH0_CR_DCCDATACONTROL1_REG                             (0x000012D0)

  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x060012D0)

  #define DDRDATA6CH0_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x020612D0)

  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x040812D0)

  #define DDRDATA6CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C12D0)

  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E12D0)

  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F12D0)

  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F1012D0)

  #define DDRDATA6CH0_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F12D0)

#define DDRDATA6CH0_CR_DCCDATACONTROL2_REG                             (0x000012D4)

  #define DDRDATA6CH0_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x060012D4)

  #define DDRDATA6CH0_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x030612D4)

  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D0912D4)

  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x051612D4)

  #define DDRDATA6CH0_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B12D4)

  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C12D4)

#define DDRDATA6CH0_CR_DCCDATACONTROL3_REG                             (0x000012D8)

  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B0012D8)

  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B12D8)

  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x091412D8)

  #define DDRDATA6CH0_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D12D8)

#define DDRDATA6CH0_CR_DCCDATACONTROL4_REG                             (0x000012DC)

  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x090012DC)

  #define DDRDATA6CH0_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_Spare_HSH                     (0x010912DC)

  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A12DC)

  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x061012DC)

  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x061612DC)

  #define DDRDATA6CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C12DC)

#define DDRDATA6CH0_CR_DCCDATACONTROL5_REG                             (0x000012E0)

  #define DDRDATA6CH0_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_Spare_HSH                     (0x020012E0)

  #define DDRDATA6CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x010212E0)

  #define DDRDATA6CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x060312E0)

  #define DDRDATA6CH0_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x050912E0)

  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E12E0)

  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B1412E0)

  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F12E0)

#define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_REG                         (0x000012E4)

  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B0012E4)

  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B12E4)

  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x091412E4)

  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D12E4)

#define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_REG                         (0x000012E8)

  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x090012E8)

  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x010912E8)

  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A12E8)

  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B12E8)

  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A12E8)

  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B12E8)

#define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_REG                         (0x000012EC)

  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x100012EC)

  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x071012EC)

  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x071712EC)

  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E12EC)

#define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x000012F0)

  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B0012F0)

  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B12F0)

  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C12F0)

#define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x000012F4)

  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x090012F4)

  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x110912F4)

  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A12F4)

#define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x000012F8)

  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x090012F8)

  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x110912F8)

  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A12F8)

#define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x000012FC)

  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x090012FC)

  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x110912FC)

  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A12FC)

#define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_REG                        (0x00001300)

  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06001300)

  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06061300)

  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C1300)

  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06121300)

  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07181300)

  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F1300)

#define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00001304)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06001304)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06061304)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C1304)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06121304)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06181304)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E1304)

#define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00001308)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06001308)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06061308)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C1308)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06121308)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06181308)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E1308)

#define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_REG                       (0x0000130C)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x0600130C)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x0606130C)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C130C)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x0612130C)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x0618130C)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E130C)

#define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00001310)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06001310)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06061310)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C1310)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06121310)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06181310)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E1310)

#define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00001314)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06001314)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06061314)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C1314)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06121314)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06181314)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E1314)

#define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00001318)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06001318)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06061318)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C1318)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06121318)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02181318)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A1318)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D1318)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E1318)

#define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_REG                       (0x0000131C)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x0600131C)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x0606131C)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C131C)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x0612131C)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x0618131C)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E131C)

#define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_REG                       (0x00001320)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x06001320)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x06061320)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C1320)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x06121320)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x06181320)

  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA6CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E1320)

#define DDRDATA6CH0_CR_DCCDATADCCPILUT0_REG                            (0x00001324)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x06001324)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x06061324)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C1324)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x06121324)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x06181324)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E1324)

#define DDRDATA6CH0_CR_DCCDATADCCPILUT1_REG                            (0x00001328)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x06001328)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x06061328)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C1328)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x06121328)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x06181328)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E1328)

#define DDRDATA6CH0_CR_DCCDATADCCPILUT2_REG                            (0x0000132C)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x0600132C)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x0606132C)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C132C)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x0612132C)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x0618132C)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E132C)

#define DDRDATA6CH0_CR_DCCDATADCCPILUT3_REG                            (0x00001330)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x06001330)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x06061330)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C1330)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x06121330)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x06181330)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E1330)

#define DDRDATA6CH0_CR_DCCDATADCCPILUT4_REG                            (0x00001334)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x06001334)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x06061334)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C1334)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x06121334)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x06181334)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E1334)

#define DDRDATA6CH0_CR_DCCDATADCCPILUT5_REG                            (0x00001338)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x06001338)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x06061338)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C1338)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x06121338)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x06181338)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E1338)

#define DDRDATA6CH0_CR_DCCDATADCCPILUT6_REG                            (0x0000133C)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x0600133C)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x0606133C)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C133C)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x0612133C)

  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH0_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x0818133C)

#define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_REG                        (0x00001340)

  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x06001340)

  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x06061340)

  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C1340)

  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x06121340)

  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x06181340)

  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E1340)

#define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_REG                        (0x00001344)

  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x06001344)

  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x06061344)

  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C1344)

  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x06121344)

  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x06181344)

  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E1344)

#define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x00001348)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x06001348)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x06061348)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C1348)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x06121348)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x02181348)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A1348)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C1348)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E1348)

#define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x0000134C)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x0600134C)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x0606134C)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C134C)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x0612134C)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x0818134C)

#define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x00001350)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x06001350)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x06061350)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C1350)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x06121350)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x06181350)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E1350)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F1350)

#define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x00001354)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x06001354)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x06061354)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C1354)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x06121354)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x06181354)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E1354)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F1354)

#define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x00001358)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x06001358)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x06061358)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C1358)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x06121358)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x06181358)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E1358)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F1358)

#define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x0000135C)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x0600135C)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x0606135C)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C135C)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x0612135C)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x0618135C)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E135C)

  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA6CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F135C)

#define DDRDATA6CH1_CR_RXCONTROL0RANK0_REG                             (0x00001380)

  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B001380)

  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B1380)

  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07121380)

  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07191380)

#define DDRDATA6CH1_CR_RXCONTROL0RANK1_REG                             (0x00001384)

  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B001384)

  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B1384)

  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07121384)

  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07191384)

#define DDRDATA6CH1_CR_RXCONTROL0RANK2_REG                             (0x00001388)

  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B001388)

  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B1388)

  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07121388)

  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07191388)

#define DDRDATA6CH1_CR_RXCONTROL0RANK3_REG                             (0x0000138C)

  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B00138C)

  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B138C)

  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x0712138C)

  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x0719138C)

#define DDRDATA6CH1_CR_RXCONTROL1RANK0_REG                             (0x00001390)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06001390)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06061390)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C1390)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06121390)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02181390)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A1390)

#define DDRDATA6CH1_CR_RXCONTROL1RANK1_REG                             (0x00001394)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06001394)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06061394)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C1394)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06121394)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02181394)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A1394)

#define DDRDATA6CH1_CR_RXCONTROL1RANK2_REG                             (0x00001398)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06001398)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06061398)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C1398)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06121398)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02181398)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A1398)

#define DDRDATA6CH1_CR_RXCONTROL1RANK3_REG                             (0x0000139C)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x0600139C)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x0606139C)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C139C)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x0612139C)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x0218139C)

  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A139C)

#define DDRDATA6CH1_CR_TXTRAINRANK0_REG                                (0x000013A0)

  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A0013A0)

  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A13A0)

  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxEqualization_HSH               (0x061413A0)

  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A13A0)

  #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E13A0)

#define DDRDATA6CH1_CR_TXTRAINRANK1_REG                                (0x000013A4)

  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A0013A4)

  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A13A4)

  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxEqualization_HSH               (0x061413A4)

  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A13A4)

  #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C13A4)

#define DDRDATA6CH1_CR_TXTRAINRANK2_REG                                (0x000013A8)

  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A0013A8)

  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A13A8)

  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_TxEqualization_HSH               (0x061413A8)

  #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A13A8)

#define DDRDATA6CH1_CR_TXTRAINRANK3_REG                                (0x000013AC)

  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A0013AC)

  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A13AC)

  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_TxEqualization_HSH               (0x061413AC)

  #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA6CH1_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A13AC)

#define DDRDATA6CH1_CR_TXPERBITLOWRANK0_REG                            (0x000013B0)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x060013B0)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x060613B0)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C13B0)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x061213B0)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x081813B0)

#define DDRDATA6CH1_CR_TXPERBITLOWRANK1_REG                            (0x000013B4)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x060013B4)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x060613B4)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C13B4)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x061213B4)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x081813B4)

#define DDRDATA6CH1_CR_TXPERBITLOWRANK2_REG                            (0x000013B8)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x060013B8)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x060613B8)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C13B8)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x061213B8)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x081813B8)

#define DDRDATA6CH1_CR_TXPERBITLOWRANK3_REG                            (0x000013BC)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x060013BC)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x060613BC)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C13BC)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x061213BC)

  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x081813BC)

#define DDRDATA6CH1_CR_RCOMPDATA0_REG                                  (0x000013C0)

  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x060013C0)

  #define DDRDATA6CH1_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA6CH1_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA6CH1_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA6CH1_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA6CH1_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA6CH1_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA6CH1_CR_RCOMPDATA0_Rsvd_HSH                           (0x080613C0)

  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA6CH1_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E13C0)

  #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA6CH1_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x051413C0)

  #define DDRDATA6CH1_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA6CH1_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA6CH1_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA6CH1_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA6CH1_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA6CH1_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA6CH1_CR_RCOMPDATA0_Spare_HSH                          (0x071913C0)

#define DDRDATA6CH1_CR_RCOMPDATA1_REG                                  (0x000013C4)

  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x060013C4)

  #define DDRDATA6CH1_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA6CH1_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA6CH1_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA6CH1_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA6CH1_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA6CH1_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA6CH1_CR_RCOMPDATA1_spare_HSH                          (0x140613C4)

  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA6CH1_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A13C4)

#define DDRDATA6CH1_CR_DDRCRDATACONTROL8_REG                           (0x000013C8)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x020013C8)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x020213C8)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x020413C8)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x020613C8)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x010813C8)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL8_spare_HSH                   (0x170913C8)

#define DDRDATA6CH1_CR_RCOMPDATA2_REG                                  (0x000013CC)

  #define DDRDATA6CH1_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA6CH1_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA6CH1_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA6CH1_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA6CH1_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA6CH1_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x080013CC)

  #define DDRDATA6CH1_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA6CH1_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA6CH1_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA6CH1_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA6CH1_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA6CH1_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x080813CC)

  #define DDRDATA6CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA6CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA6CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA6CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA6CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA6CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x061013CC)

  #define DDRDATA6CH1_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA6CH1_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA6CH1_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA6CH1_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA6CH1_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA6CH1_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA6CH1_CR_RCOMPDATA2_Spare_HSH                          (0x0A1613CC)

#define DDRDATA6CH1_CR_RXCONTROL2RANK0_REG                             (0x000013D0)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x060013D0)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x060613D0)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C13D0)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x051113D0)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x051613D0)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B13D0)

#define DDRDATA6CH1_CR_RXCONTROL2RANK1_REG                             (0x000013D4)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x060013D4)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x060613D4)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C13D4)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x051113D4)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x051613D4)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B13D4)

#define DDRDATA6CH1_CR_RXCONTROL2RANK2_REG                             (0x000013D8)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x060013D8)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x060613D8)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C13D8)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x051113D8)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x051613D8)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B13D8)

#define DDRDATA6CH1_CR_RXCONTROL2RANK3_REG                             (0x000013DC)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x060013DC)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x060613DC)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C13DC)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x051113DC)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x051613DC)

  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B13DC)

#define DDRDATA6CH1_CR_DATATRAINFEEDBACK_REG                           (0x000013E0)

  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x090013E0)

  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA6CH1_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x170913E0)

#define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_REG                         (0x000013E8)

  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x860013E8)

  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x860613E8)

  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C13E8)

  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x851113E8)

  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x051613E8)

  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B13E8)

#define DDRDATA6CH1_CR_DDRCRDATACONTROL1_REG                           (0x000013EC)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x840013EC)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x020413EC)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x010613EC)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x030713EC)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A13EC)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E13EC)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x031313EC)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x851613EC)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B13EC)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E13EC)

#define DDRDATA6CH1_CR_DDRCRDATACONTROL2_REG                           (0x000013F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x050013F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x010513F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x010613F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x010713F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x010813F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x040913F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D13F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x011213F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x011313F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x011413F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x011513F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x011613F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x011713F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x011813F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x011913F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A13F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D13F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E13F0)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F13F0)

#define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x000013FC)

  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x860013FC)

  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x870613FC)

  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D13FC)

  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x861313FC)

  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x871913FC)

#define DDRDATA6CH1_CR_DDRCRDATACONTROL0_REG                           (0x00001400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01001400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01011400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01021400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01031400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01041400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01051400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01061400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01071400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01081400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01091400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A1400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B1400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C1400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D1400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F1400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02131400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01151400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01161400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01171400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01181400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01191400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A1400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B1400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C1400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D1400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E1400)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F1400)

#define DDRDATA6CH1_CR_DDRCRDATACONTROL3_REG                           (0x00001408)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04001408)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02041408)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01061408)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01071408)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86081408)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E1408)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F1408)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03101408)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01131408)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03141408)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01171408)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01181408)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01191408)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A1408)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E1408)

#define DDRDATA6CH1_CR_DDRCRDATACONTROL4_REG                           (0x0000140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x0100140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x0101140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x0302140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x0105140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x0106140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x0107140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x0108140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x0209140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x0110140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x0111140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x0112140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x0513140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x0518140C)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_spare2_OFF                  (29)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_spare2_WID                  ( 3)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_spare2_MSK                  (0xE0000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_spare2_MIN                  (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_spare2_MAX                  (7) // 0x00000007
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_spare2_DEF                  (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL4_spare2_HSH                  (0x031D140C)

#define DDRDATA6CH1_CR_DDRCRDATACONTROL5_REG                           (0x00001410)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08001410)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01081410)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02091410)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B1410)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F1410)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08101410)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08181410)

#define DDRDATA6CH1_CR_DDRCRDATACONTROL6_REG                           (0x00001414)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01001414)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02011414)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01031414)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05041414)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01091414)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A1414)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B1414)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C1414)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E1414)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F1414)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08101414)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01181414)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01191414)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A1414)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D1414)

#define DDRDATA6CH1_CR_DDRCRDATACONTROL7_REG                           (0x00001418)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06001418)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06061418)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C1418)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06121418)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04181418)

  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA6CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C1418)

#define DDRDATA6CH1_CR_DELTADQSRANK0_REG                               (0x0000141C)

  #define DDRDATA6CH1_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA6CH1_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA6CH1_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA6CH1_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA6CH1_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA6CH1_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A00141C)

  #define DDRDATA6CH1_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA6CH1_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA6CH1_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA6CH1_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA6CH1_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA6CH1_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA6CH1_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A141C)

#define DDRDATA6CH1_CR_DELTADQSRANK1_REG                               (0x00001420)

  #define DDRDATA6CH1_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA6CH1_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA6CH1_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA6CH1_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA6CH1_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA6CH1_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A001420)

  #define DDRDATA6CH1_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA6CH1_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA6CH1_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA6CH1_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA6CH1_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA6CH1_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA6CH1_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A1420)

#define DDRDATA6CH1_CR_DELTADQSRANK2_REG                               (0x00001424)

  #define DDRDATA6CH1_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA6CH1_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA6CH1_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA6CH1_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA6CH1_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA6CH1_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A001424)

  #define DDRDATA6CH1_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA6CH1_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA6CH1_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA6CH1_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA6CH1_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA6CH1_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA6CH1_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A1424)

#define DDRDATA6CH1_CR_DELTADQSRANK3_REG                               (0x00001428)

  #define DDRDATA6CH1_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA6CH1_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA6CH1_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA6CH1_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA6CH1_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA6CH1_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A001428)

  #define DDRDATA6CH1_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA6CH1_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA6CH1_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA6CH1_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA6CH1_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA6CH1_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA6CH1_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A1428)

#define DDRDATA6CH1_CR_RXCONTROL3RANK0_REG                             (0x0000142C)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x0600142C)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x0606142C)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C142C)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x0511142C)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x0516142C)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B142C)

#define DDRDATA6CH1_CR_RXCONTROL3RANK1_REG                             (0x00001430)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x06001430)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x06061430)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C1430)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x05111430)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x05161430)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B1430)

#define DDRDATA6CH1_CR_RXCONTROL3RANK2_REG                             (0x00001434)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x06001434)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x06061434)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C1434)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x05111434)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x05161434)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B1434)

#define DDRDATA6CH1_CR_RXCONTROL3RANK3_REG                             (0x00001438)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x06001438)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x06061438)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C1438)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x05111438)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x05161438)

  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA6CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B1438)

#define DDRDATA6CH1_CR_TXPERBITHIRANK0_REG                             (0x0000143C)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x0600143C)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x0606143C)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C143C)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x0612143C)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK0_Spare_HSH                     (0x0818143C)

#define DDRDATA6CH1_CR_TXPERBITHIRANK1_REG                             (0x00001440)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x06001440)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x06061440)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C1440)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x06121440)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK1_Spare_HSH                     (0x08181440)

#define DDRDATA6CH1_CR_TXPERBITHIRANK2_REG                             (0x00001444)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x06001444)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x06061444)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C1444)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x06121444)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK2_Spare_HSH                     (0x08181444)

#define DDRDATA6CH1_CR_TXPERBITHIRANK3_REG                             (0x00001448)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x06001448)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x06061448)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C1448)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x06121448)

  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_TXPERBITHIRANK3_Spare_HSH                     (0x08181448)

#define DDRDATA6CH1_CR_DCCDATACONTROL0_REG                             (0x0000144C)

  #define DDRDATA6CH1_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x0100144C)

  #define DDRDATA6CH1_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x0201144C)

  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x0103144C)

  #define DDRDATA6CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x0204144C)

  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x0706144C)

  #define DDRDATA6CH1_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D144C)

  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA6CH1_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C144C)

#define DDRDATA6CH1_CR_DCCDATACONTROL1_REG                             (0x00001450)

  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x06001450)

  #define DDRDATA6CH1_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x02061450)

  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x04081450)

  #define DDRDATA6CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C1450)

  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E1450)

  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F1450)

  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F101450)

  #define DDRDATA6CH1_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F1450)

#define DDRDATA6CH1_CR_DCCDATACONTROL2_REG                             (0x00001454)

  #define DDRDATA6CH1_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x06001454)

  #define DDRDATA6CH1_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x03061454)

  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D091454)

  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x05161454)

  #define DDRDATA6CH1_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B1454)

  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C1454)

#define DDRDATA6CH1_CR_DCCDATACONTROL3_REG                             (0x00001458)

  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B001458)

  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B1458)

  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x09141458)

  #define DDRDATA6CH1_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D1458)

#define DDRDATA6CH1_CR_DCCDATACONTROL4_REG                             (0x0000145C)

  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x0900145C)

  #define DDRDATA6CH1_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_Spare_HSH                     (0x0109145C)

  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A145C)

  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x0610145C)

  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x0616145C)

  #define DDRDATA6CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C145C)

#define DDRDATA6CH1_CR_DCCDATACONTROL5_REG                             (0x00001460)

  #define DDRDATA6CH1_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_Spare_HSH                     (0x02001460)

  #define DDRDATA6CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x01021460)

  #define DDRDATA6CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x06031460)

  #define DDRDATA6CH1_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x05091460)

  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E1460)

  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B141460)

  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F1460)

#define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_REG                         (0x00001464)

  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B001464)

  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B1464)

  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x09141464)

  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D1464)

#define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_REG                         (0x00001468)

  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x09001468)

  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x01091468)

  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A1468)

  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B1468)

  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A1468)

  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B1468)

#define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_REG                         (0x0000146C)

  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x1000146C)

  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x0710146C)

  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x0717146C)

  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E146C)

#define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x00001470)

  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B001470)

  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B1470)

  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C1470)

#define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x00001474)

  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x09001474)

  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x11091474)

  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A1474)

#define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x00001478)

  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x09001478)

  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x11091478)

  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A1478)

#define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x0000147C)

  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x0900147C)

  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x1109147C)

  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A147C)

#define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_REG                        (0x00001480)

  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06001480)

  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06061480)

  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C1480)

  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06121480)

  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07181480)

  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F1480)

#define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00001484)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06001484)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06061484)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C1484)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06121484)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06181484)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E1484)

#define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00001488)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06001488)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06061488)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C1488)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06121488)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06181488)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E1488)

#define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_REG                       (0x0000148C)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x0600148C)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x0606148C)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C148C)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x0612148C)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x0618148C)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E148C)

#define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00001490)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06001490)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06061490)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C1490)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06121490)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06181490)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E1490)

#define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00001494)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06001494)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06061494)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C1494)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06121494)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06181494)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E1494)

#define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00001498)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06001498)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06061498)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C1498)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06121498)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02181498)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A1498)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D1498)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E1498)

#define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_REG                       (0x0000149C)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x0600149C)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x0606149C)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C149C)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x0612149C)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x0618149C)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E149C)

#define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_REG                       (0x000014A0)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x060014A0)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x060614A0)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C14A0)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x061214A0)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x061814A0)

  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA6CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E14A0)

#define DDRDATA6CH1_CR_DCCDATADCCPILUT0_REG                            (0x000014A4)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x060014A4)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x060614A4)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C14A4)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x061214A4)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x061814A4)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E14A4)

#define DDRDATA6CH1_CR_DCCDATADCCPILUT1_REG                            (0x000014A8)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x060014A8)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x060614A8)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C14A8)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x061214A8)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x061814A8)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E14A8)

#define DDRDATA6CH1_CR_DCCDATADCCPILUT2_REG                            (0x000014AC)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x060014AC)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x060614AC)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C14AC)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x061214AC)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x061814AC)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E14AC)

#define DDRDATA6CH1_CR_DCCDATADCCPILUT3_REG                            (0x000014B0)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x060014B0)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x060614B0)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C14B0)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x061214B0)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x061814B0)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E14B0)

#define DDRDATA6CH1_CR_DCCDATADCCPILUT4_REG                            (0x000014B4)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x060014B4)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x060614B4)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C14B4)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x061214B4)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x061814B4)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E14B4)

#define DDRDATA6CH1_CR_DCCDATADCCPILUT5_REG                            (0x000014B8)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x060014B8)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x060614B8)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C14B8)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x061214B8)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x061814B8)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E14B8)

#define DDRDATA6CH1_CR_DCCDATADCCPILUT6_REG                            (0x000014BC)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x060014BC)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x060614BC)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C14BC)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x061214BC)

  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA6CH1_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x081814BC)

#define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_REG                        (0x000014C0)

  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x060014C0)

  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x060614C0)

  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C14C0)

  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x061214C0)

  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x061814C0)

  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E14C0)

#define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_REG                        (0x000014C4)

  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x060014C4)

  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x060614C4)

  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C14C4)

  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x061214C4)

  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x061814C4)

  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E14C4)

#define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x000014C8)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x060014C8)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x060614C8)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C14C8)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x061214C8)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x021814C8)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A14C8)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C14C8)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E14C8)

#define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x000014CC)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x060014CC)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x060614CC)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C14CC)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x061214CC)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x081814CC)

#define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x000014D0)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x060014D0)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x060614D0)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C14D0)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x061214D0)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x061814D0)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E14D0)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F14D0)

#define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x000014D4)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x060014D4)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x060614D4)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C14D4)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x061214D4)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x061814D4)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E14D4)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F14D4)

#define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x000014D8)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x060014D8)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x060614D8)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C14D8)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x061214D8)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x061814D8)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E14D8)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F14D8)

#define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x000014DC)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x060014DC)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x060614DC)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C14DC)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x061214DC)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x061814DC)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E14DC)

  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA6CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F14DC)

#define DDRDATA7CH0_CR_RXCONTROL0RANK0_REG                             (0x00001500)

  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B001500)

  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B1500)

  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07121500)

  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07191500)

#define DDRDATA7CH0_CR_RXCONTROL0RANK1_REG                             (0x00001504)

  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B001504)

  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B1504)

  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07121504)

  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07191504)

#define DDRDATA7CH0_CR_RXCONTROL0RANK2_REG                             (0x00001508)

  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B001508)

  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B1508)

  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07121508)

  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07191508)

#define DDRDATA7CH0_CR_RXCONTROL0RANK3_REG                             (0x0000150C)

  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B00150C)

  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B150C)

  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x0712150C)

  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x0719150C)

#define DDRDATA7CH0_CR_RXCONTROL1RANK0_REG                             (0x00001510)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06001510)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06061510)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C1510)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06121510)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02181510)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A1510)

#define DDRDATA7CH0_CR_RXCONTROL1RANK1_REG                             (0x00001514)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06001514)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06061514)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C1514)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06121514)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02181514)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A1514)

#define DDRDATA7CH0_CR_RXCONTROL1RANK2_REG                             (0x00001518)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06001518)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06061518)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C1518)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06121518)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02181518)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A1518)

#define DDRDATA7CH0_CR_RXCONTROL1RANK3_REG                             (0x0000151C)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x0600151C)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x0606151C)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C151C)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x0612151C)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x0218151C)

  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A151C)

#define DDRDATA7CH0_CR_TXTRAINRANK0_REG                                (0x00001520)

  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A001520)

  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A1520)

  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxEqualization_HSH               (0x06141520)

  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A1520)

  #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E1520)

#define DDRDATA7CH0_CR_TXTRAINRANK1_REG                                (0x00001524)

  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A001524)

  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A1524)

  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxEqualization_HSH               (0x06141524)

  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A1524)

  #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C1524)

#define DDRDATA7CH0_CR_TXTRAINRANK2_REG                                (0x00001528)

  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A001528)

  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A1528)

  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_TxEqualization_HSH               (0x06141528)

  #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A1528)

#define DDRDATA7CH0_CR_TXTRAINRANK3_REG                                (0x0000152C)

  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A00152C)

  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A152C)

  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_TxEqualization_HSH               (0x0614152C)

  #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA7CH0_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A152C)

#define DDRDATA7CH0_CR_TXPERBITLOWRANK0_REG                            (0x00001530)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x06001530)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x06061530)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C1530)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x06121530)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x08181530)

#define DDRDATA7CH0_CR_TXPERBITLOWRANK1_REG                            (0x00001534)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x06001534)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x06061534)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C1534)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x06121534)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x08181534)

#define DDRDATA7CH0_CR_TXPERBITLOWRANK2_REG                            (0x00001538)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x06001538)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x06061538)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C1538)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x06121538)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x08181538)

#define DDRDATA7CH0_CR_TXPERBITLOWRANK3_REG                            (0x0000153C)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x0600153C)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x0606153C)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C153C)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x0612153C)

  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x0818153C)

#define DDRDATA7CH0_CR_RCOMPDATA0_REG                                  (0x00001540)

  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x06001540)

  #define DDRDATA7CH0_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA7CH0_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA7CH0_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA7CH0_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA7CH0_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA7CH0_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA7CH0_CR_RCOMPDATA0_Rsvd_HSH                           (0x08061540)

  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA7CH0_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E1540)

  #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA7CH0_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x05141540)

  #define DDRDATA7CH0_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA7CH0_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA7CH0_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA7CH0_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA7CH0_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA7CH0_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA7CH0_CR_RCOMPDATA0_Spare_HSH                          (0x07191540)

#define DDRDATA7CH0_CR_RCOMPDATA1_REG                                  (0x00001544)

  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x06001544)

  #define DDRDATA7CH0_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA7CH0_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA7CH0_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA7CH0_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA7CH0_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA7CH0_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA7CH0_CR_RCOMPDATA1_spare_HSH                          (0x14061544)

  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA7CH0_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A1544)

#define DDRDATA7CH0_CR_DDRCRDATACONTROL8_REG                           (0x00001548)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x02001548)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x02021548)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x02041548)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x02061548)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x01081548)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL8_spare_HSH                   (0x17091548)

#define DDRDATA7CH0_CR_RCOMPDATA2_REG                                  (0x0000154C)

  #define DDRDATA7CH0_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA7CH0_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA7CH0_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA7CH0_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA7CH0_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA7CH0_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x0800154C)

  #define DDRDATA7CH0_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA7CH0_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA7CH0_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA7CH0_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA7CH0_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA7CH0_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x0808154C)

  #define DDRDATA7CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA7CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA7CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA7CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA7CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA7CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x0610154C)

  #define DDRDATA7CH0_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA7CH0_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA7CH0_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA7CH0_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA7CH0_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA7CH0_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA7CH0_CR_RCOMPDATA2_Spare_HSH                          (0x0A16154C)

#define DDRDATA7CH0_CR_RXCONTROL2RANK0_REG                             (0x00001550)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x06001550)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x06061550)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C1550)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x05111550)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x05161550)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B1550)

#define DDRDATA7CH0_CR_RXCONTROL2RANK1_REG                             (0x00001554)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x06001554)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x06061554)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C1554)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x05111554)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x05161554)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B1554)

#define DDRDATA7CH0_CR_RXCONTROL2RANK2_REG                             (0x00001558)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x06001558)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x06061558)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C1558)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x05111558)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x05161558)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B1558)

#define DDRDATA7CH0_CR_RXCONTROL2RANK3_REG                             (0x0000155C)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x0600155C)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x0606155C)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C155C)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x0511155C)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x0516155C)

  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B155C)

#define DDRDATA7CH0_CR_DATATRAINFEEDBACK_REG                           (0x00001560)

  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x09001560)

  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA7CH0_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x17091560)

#define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_REG                         (0x00001568)

  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x86001568)

  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x86061568)

  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C1568)

  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x85111568)

  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x05161568)

  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B1568)

#define DDRDATA7CH0_CR_DDRCRDATACONTROL1_REG                           (0x0000156C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x8400156C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x0204156C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x0106156C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x0307156C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A156C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E156C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x0313156C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x8516156C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B156C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E156C)

#define DDRDATA7CH0_CR_DDRCRDATACONTROL2_REG                           (0x00001570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x05001570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x01051570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x01061570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x01071570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x01081570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x04091570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D1570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x01121570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x01131570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x01141570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x01151570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x01161570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x01171570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x01181570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x01191570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A1570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D1570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E1570)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F1570)

#define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x0000157C)

  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x8600157C)

  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x8706157C)

  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D157C)

  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x8613157C)

  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x8719157C)

#define DDRDATA7CH0_CR_DDRCRDATACONTROL0_REG                           (0x00001580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01001580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01011580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01021580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01031580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01041580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01051580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01061580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01071580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01081580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01091580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A1580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B1580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C1580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D1580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F1580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02131580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01151580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01161580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01171580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01181580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01191580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A1580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B1580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C1580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D1580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E1580)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F1580)

#define DDRDATA7CH0_CR_DDRCRDATACONTROL3_REG                           (0x00001588)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04001588)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02041588)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01061588)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01071588)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86081588)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E1588)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F1588)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03101588)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01131588)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03141588)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01171588)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01181588)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01191588)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A1588)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E1588)

#define DDRDATA7CH0_CR_DDRCRDATACONTROL4_REG                           (0x0000158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x0100158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x0101158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x0302158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x0105158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x0106158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x0107158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x0108158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x0209158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x0110158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x0111158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x0112158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x0513158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x0518158C)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_spare2_OFF                  (29)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_spare2_WID                  ( 3)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_spare2_MSK                  (0xE0000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_spare2_MIN                  (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_spare2_MAX                  (7) // 0x00000007
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_spare2_DEF                  (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL4_spare2_HSH                  (0x031D158C)

#define DDRDATA7CH0_CR_DDRCRDATACONTROL5_REG                           (0x00001590)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08001590)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01081590)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02091590)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B1590)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F1590)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08101590)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08181590)

#define DDRDATA7CH0_CR_DDRCRDATACONTROL6_REG                           (0x00001594)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01001594)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02011594)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01031594)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05041594)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01091594)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A1594)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B1594)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C1594)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E1594)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F1594)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08101594)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01181594)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01191594)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A1594)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D1594)

#define DDRDATA7CH0_CR_DDRCRDATACONTROL7_REG                           (0x00001598)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06001598)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06061598)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C1598)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06121598)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04181598)

  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA7CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C1598)

#define DDRDATA7CH0_CR_DELTADQSRANK0_REG                               (0x0000159C)

  #define DDRDATA7CH0_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA7CH0_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA7CH0_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA7CH0_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA7CH0_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA7CH0_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A00159C)

  #define DDRDATA7CH0_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA7CH0_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA7CH0_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA7CH0_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA7CH0_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA7CH0_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA7CH0_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A159C)

#define DDRDATA7CH0_CR_DELTADQSRANK1_REG                               (0x000015A0)

  #define DDRDATA7CH0_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA7CH0_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA7CH0_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA7CH0_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA7CH0_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA7CH0_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A0015A0)

  #define DDRDATA7CH0_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA7CH0_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA7CH0_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA7CH0_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA7CH0_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA7CH0_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA7CH0_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A15A0)

#define DDRDATA7CH0_CR_DELTADQSRANK2_REG                               (0x000015A4)

  #define DDRDATA7CH0_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA7CH0_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA7CH0_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA7CH0_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA7CH0_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA7CH0_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A0015A4)

  #define DDRDATA7CH0_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA7CH0_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA7CH0_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA7CH0_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA7CH0_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA7CH0_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA7CH0_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A15A4)

#define DDRDATA7CH0_CR_DELTADQSRANK3_REG                               (0x000015A8)

  #define DDRDATA7CH0_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA7CH0_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA7CH0_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA7CH0_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA7CH0_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA7CH0_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A0015A8)

  #define DDRDATA7CH0_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA7CH0_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA7CH0_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA7CH0_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA7CH0_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA7CH0_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA7CH0_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A15A8)

#define DDRDATA7CH0_CR_RXCONTROL3RANK0_REG                             (0x000015AC)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x060015AC)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x060615AC)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C15AC)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x051115AC)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x051615AC)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B15AC)

#define DDRDATA7CH0_CR_RXCONTROL3RANK1_REG                             (0x000015B0)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x060015B0)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x060615B0)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C15B0)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x051115B0)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x051615B0)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B15B0)

#define DDRDATA7CH0_CR_RXCONTROL3RANK2_REG                             (0x000015B4)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x060015B4)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x060615B4)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C15B4)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x051115B4)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x051615B4)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B15B4)

#define DDRDATA7CH0_CR_RXCONTROL3RANK3_REG                             (0x000015B8)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x060015B8)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x060615B8)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C15B8)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x051115B8)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x051615B8)

  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B15B8)

#define DDRDATA7CH0_CR_TXPERBITHIRANK0_REG                             (0x000015BC)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x060015BC)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x060615BC)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C15BC)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x061215BC)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK0_Spare_HSH                     (0x081815BC)

#define DDRDATA7CH0_CR_TXPERBITHIRANK1_REG                             (0x000015C0)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x060015C0)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x060615C0)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C15C0)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x061215C0)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK1_Spare_HSH                     (0x081815C0)

#define DDRDATA7CH0_CR_TXPERBITHIRANK2_REG                             (0x000015C4)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x060015C4)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x060615C4)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C15C4)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x061215C4)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK2_Spare_HSH                     (0x081815C4)

#define DDRDATA7CH0_CR_TXPERBITHIRANK3_REG                             (0x000015C8)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x060015C8)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x060615C8)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C15C8)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x061215C8)

  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_TXPERBITHIRANK3_Spare_HSH                     (0x081815C8)

#define DDRDATA7CH0_CR_DCCDATACONTROL0_REG                             (0x000015CC)

  #define DDRDATA7CH0_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x010015CC)

  #define DDRDATA7CH0_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x020115CC)

  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x010315CC)

  #define DDRDATA7CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x020415CC)

  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x070615CC)

  #define DDRDATA7CH0_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D15CC)

  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA7CH0_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C15CC)

#define DDRDATA7CH0_CR_DCCDATACONTROL1_REG                             (0x000015D0)

  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x060015D0)

  #define DDRDATA7CH0_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x020615D0)

  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x040815D0)

  #define DDRDATA7CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C15D0)

  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E15D0)

  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F15D0)

  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F1015D0)

  #define DDRDATA7CH0_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F15D0)

#define DDRDATA7CH0_CR_DCCDATACONTROL2_REG                             (0x000015D4)

  #define DDRDATA7CH0_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x060015D4)

  #define DDRDATA7CH0_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x030615D4)

  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D0915D4)

  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x051615D4)

  #define DDRDATA7CH0_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B15D4)

  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C15D4)

#define DDRDATA7CH0_CR_DCCDATACONTROL3_REG                             (0x000015D8)

  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B0015D8)

  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B15D8)

  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x091415D8)

  #define DDRDATA7CH0_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D15D8)

#define DDRDATA7CH0_CR_DCCDATACONTROL4_REG                             (0x000015DC)

  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x090015DC)

  #define DDRDATA7CH0_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_Spare_HSH                     (0x010915DC)

  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A15DC)

  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x061015DC)

  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x061615DC)

  #define DDRDATA7CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C15DC)

#define DDRDATA7CH0_CR_DCCDATACONTROL5_REG                             (0x000015E0)

  #define DDRDATA7CH0_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_Spare_HSH                     (0x020015E0)

  #define DDRDATA7CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x010215E0)

  #define DDRDATA7CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x060315E0)

  #define DDRDATA7CH0_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x050915E0)

  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E15E0)

  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B1415E0)

  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F15E0)

#define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_REG                         (0x000015E4)

  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B0015E4)

  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B15E4)

  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x091415E4)

  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D15E4)

#define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_REG                         (0x000015E8)

  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x090015E8)

  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x010915E8)

  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A15E8)

  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B15E8)

  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A15E8)

  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B15E8)

#define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_REG                         (0x000015EC)

  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x100015EC)

  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x071015EC)

  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x071715EC)

  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E15EC)

#define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x000015F0)

  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B0015F0)

  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B15F0)

  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C15F0)

#define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x000015F4)

  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x090015F4)

  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x110915F4)

  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A15F4)

#define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x000015F8)

  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x090015F8)

  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x110915F8)

  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A15F8)

#define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x000015FC)

  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x090015FC)

  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x110915FC)

  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A15FC)

#define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_REG                        (0x00001600)

  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06001600)

  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06061600)

  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C1600)

  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06121600)

  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07181600)

  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F1600)

#define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00001604)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06001604)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06061604)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C1604)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06121604)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06181604)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E1604)

#define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00001608)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06001608)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06061608)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C1608)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06121608)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06181608)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E1608)

#define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_REG                       (0x0000160C)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x0600160C)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x0606160C)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C160C)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x0612160C)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x0618160C)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E160C)

#define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00001610)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06001610)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06061610)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C1610)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06121610)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06181610)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E1610)

#define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00001614)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06001614)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06061614)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C1614)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06121614)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06181614)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E1614)

#define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00001618)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06001618)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06061618)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C1618)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06121618)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02181618)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A1618)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D1618)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E1618)

#define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_REG                       (0x0000161C)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x0600161C)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x0606161C)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C161C)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x0612161C)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x0618161C)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E161C)

#define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_REG                       (0x00001620)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x06001620)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x06061620)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C1620)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x06121620)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x06181620)

  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA7CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E1620)

#define DDRDATA7CH0_CR_DCCDATADCCPILUT0_REG                            (0x00001624)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x06001624)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x06061624)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C1624)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x06121624)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x06181624)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E1624)

#define DDRDATA7CH0_CR_DCCDATADCCPILUT1_REG                            (0x00001628)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x06001628)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x06061628)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C1628)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x06121628)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x06181628)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E1628)

#define DDRDATA7CH0_CR_DCCDATADCCPILUT2_REG                            (0x0000162C)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x0600162C)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x0606162C)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C162C)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x0612162C)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x0618162C)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E162C)

#define DDRDATA7CH0_CR_DCCDATADCCPILUT3_REG                            (0x00001630)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x06001630)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x06061630)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C1630)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x06121630)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x06181630)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E1630)

#define DDRDATA7CH0_CR_DCCDATADCCPILUT4_REG                            (0x00001634)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x06001634)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x06061634)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C1634)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x06121634)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x06181634)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E1634)

#define DDRDATA7CH0_CR_DCCDATADCCPILUT5_REG                            (0x00001638)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x06001638)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x06061638)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C1638)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x06121638)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x06181638)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E1638)

#define DDRDATA7CH0_CR_DCCDATADCCPILUT6_REG                            (0x0000163C)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x0600163C)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x0606163C)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C163C)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x0612163C)

  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH0_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x0818163C)

#define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_REG                        (0x00001640)

  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x06001640)

  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x06061640)

  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C1640)

  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x06121640)

  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x06181640)

  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E1640)

#define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_REG                        (0x00001644)

  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x06001644)

  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x06061644)

  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C1644)

  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x06121644)

  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x06181644)

  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E1644)

#define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x00001648)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x06001648)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x06061648)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C1648)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x06121648)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x02181648)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A1648)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C1648)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E1648)

#define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x0000164C)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x0600164C)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x0606164C)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C164C)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x0612164C)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x0818164C)

#define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x00001650)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x06001650)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x06061650)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C1650)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x06121650)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x06181650)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E1650)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F1650)

#define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x00001654)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x06001654)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x06061654)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C1654)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x06121654)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x06181654)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E1654)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F1654)

#define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x00001658)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x06001658)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x06061658)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C1658)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x06121658)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x06181658)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E1658)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F1658)

#define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x0000165C)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x0600165C)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x0606165C)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C165C)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x0612165C)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x0618165C)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E165C)

  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA7CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F165C)

#define DDRDATA7CH1_CR_RXCONTROL0RANK0_REG                             (0x00001680)

  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B001680)

  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B1680)

  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07121680)

  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07191680)

#define DDRDATA7CH1_CR_RXCONTROL0RANK1_REG                             (0x00001684)

  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B001684)

  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B1684)

  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07121684)

  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07191684)

#define DDRDATA7CH1_CR_RXCONTROL0RANK2_REG                             (0x00001688)

  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B001688)

  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B1688)

  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07121688)

  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07191688)

#define DDRDATA7CH1_CR_RXCONTROL0RANK3_REG                             (0x0000168C)

  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B00168C)

  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B168C)

  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x0712168C)

  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x0719168C)

#define DDRDATA7CH1_CR_RXCONTROL1RANK0_REG                             (0x00001690)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06001690)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06061690)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C1690)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06121690)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02181690)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A1690)

#define DDRDATA7CH1_CR_RXCONTROL1RANK1_REG                             (0x00001694)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06001694)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06061694)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C1694)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06121694)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02181694)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A1694)

#define DDRDATA7CH1_CR_RXCONTROL1RANK2_REG                             (0x00001698)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06001698)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06061698)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C1698)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06121698)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02181698)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A1698)

#define DDRDATA7CH1_CR_RXCONTROL1RANK3_REG                             (0x0000169C)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x0600169C)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x0606169C)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C169C)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x0612169C)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x0218169C)

  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A169C)

#define DDRDATA7CH1_CR_TXTRAINRANK0_REG                                (0x000016A0)

  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A0016A0)

  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A16A0)

  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxEqualization_HSH               (0x061416A0)

  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A16A0)

  #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E16A0)

#define DDRDATA7CH1_CR_TXTRAINRANK1_REG                                (0x000016A4)

  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A0016A4)

  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A16A4)

  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxEqualization_HSH               (0x061416A4)

  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A16A4)

  #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C16A4)

#define DDRDATA7CH1_CR_TXTRAINRANK2_REG                                (0x000016A8)

  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A0016A8)

  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A16A8)

  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_TxEqualization_HSH               (0x061416A8)

  #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A16A8)

#define DDRDATA7CH1_CR_TXTRAINRANK3_REG                                (0x000016AC)

  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A0016AC)

  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A16AC)

  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_TxEqualization_HSH               (0x061416AC)

  #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA7CH1_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A16AC)

#define DDRDATA7CH1_CR_TXPERBITLOWRANK0_REG                            (0x000016B0)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x060016B0)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x060616B0)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C16B0)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x061216B0)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x081816B0)

#define DDRDATA7CH1_CR_TXPERBITLOWRANK1_REG                            (0x000016B4)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x060016B4)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x060616B4)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C16B4)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x061216B4)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x081816B4)

#define DDRDATA7CH1_CR_TXPERBITLOWRANK2_REG                            (0x000016B8)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x060016B8)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x060616B8)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C16B8)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x061216B8)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x081816B8)

#define DDRDATA7CH1_CR_TXPERBITLOWRANK3_REG                            (0x000016BC)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x060016BC)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x060616BC)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C16BC)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x061216BC)

  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x081816BC)

#define DDRDATA7CH1_CR_RCOMPDATA0_REG                                  (0x000016C0)

  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x060016C0)

  #define DDRDATA7CH1_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA7CH1_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA7CH1_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA7CH1_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA7CH1_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA7CH1_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA7CH1_CR_RCOMPDATA0_Rsvd_HSH                           (0x080616C0)

  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA7CH1_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E16C0)

  #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA7CH1_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x051416C0)

  #define DDRDATA7CH1_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA7CH1_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA7CH1_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA7CH1_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA7CH1_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA7CH1_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA7CH1_CR_RCOMPDATA0_Spare_HSH                          (0x071916C0)

#define DDRDATA7CH1_CR_RCOMPDATA1_REG                                  (0x000016C4)

  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x060016C4)

  #define DDRDATA7CH1_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA7CH1_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA7CH1_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA7CH1_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA7CH1_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA7CH1_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA7CH1_CR_RCOMPDATA1_spare_HSH                          (0x140616C4)

  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA7CH1_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A16C4)

#define DDRDATA7CH1_CR_DDRCRDATACONTROL8_REG                           (0x000016C8)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x020016C8)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x020216C8)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x020416C8)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x020616C8)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x010816C8)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL8_spare_HSH                   (0x170916C8)

#define DDRDATA7CH1_CR_RCOMPDATA2_REG                                  (0x000016CC)

  #define DDRDATA7CH1_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA7CH1_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA7CH1_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA7CH1_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA7CH1_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA7CH1_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x080016CC)

  #define DDRDATA7CH1_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA7CH1_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA7CH1_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA7CH1_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA7CH1_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA7CH1_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x080816CC)

  #define DDRDATA7CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA7CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA7CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA7CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA7CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA7CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x061016CC)

  #define DDRDATA7CH1_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA7CH1_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA7CH1_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA7CH1_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA7CH1_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA7CH1_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA7CH1_CR_RCOMPDATA2_Spare_HSH                          (0x0A1616CC)

#define DDRDATA7CH1_CR_RXCONTROL2RANK0_REG                             (0x000016D0)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x060016D0)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x060616D0)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C16D0)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x051116D0)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x051616D0)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B16D0)

#define DDRDATA7CH1_CR_RXCONTROL2RANK1_REG                             (0x000016D4)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x060016D4)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x060616D4)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C16D4)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x051116D4)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x051616D4)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B16D4)

#define DDRDATA7CH1_CR_RXCONTROL2RANK2_REG                             (0x000016D8)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x060016D8)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x060616D8)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C16D8)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x051116D8)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x051616D8)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B16D8)

#define DDRDATA7CH1_CR_RXCONTROL2RANK3_REG                             (0x000016DC)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x060016DC)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x060616DC)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C16DC)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x051116DC)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x051616DC)

  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B16DC)

#define DDRDATA7CH1_CR_DATATRAINFEEDBACK_REG                           (0x000016E0)

  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x090016E0)

  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA7CH1_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x170916E0)

#define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_REG                         (0x000016E8)

  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x860016E8)

  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x860616E8)

  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C16E8)

  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x851116E8)

  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x051616E8)

  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B16E8)

#define DDRDATA7CH1_CR_DDRCRDATACONTROL1_REG                           (0x000016EC)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x840016EC)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x020416EC)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x010616EC)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x030716EC)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A16EC)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E16EC)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x031316EC)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x851616EC)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B16EC)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E16EC)

#define DDRDATA7CH1_CR_DDRCRDATACONTROL2_REG                           (0x000016F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x050016F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x010516F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x010616F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x010716F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x010816F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x040916F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D16F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x011216F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x011316F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x011416F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x011516F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x011616F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x011716F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x011816F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x011916F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A16F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D16F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E16F0)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F16F0)

#define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x000016FC)

  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x860016FC)

  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x870616FC)

  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D16FC)

  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x861316FC)

  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x871916FC)

#define DDRDATA7CH1_CR_DDRCRDATACONTROL0_REG                           (0x00001700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01001700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01011700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01021700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01031700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01041700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01051700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01061700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01071700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01081700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01091700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A1700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B1700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C1700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D1700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F1700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02131700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01151700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01161700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01171700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01181700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01191700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A1700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B1700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C1700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D1700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E1700)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F1700)

#define DDRDATA7CH1_CR_DDRCRDATACONTROL3_REG                           (0x00001708)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04001708)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02041708)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01061708)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01071708)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86081708)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E1708)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F1708)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03101708)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01131708)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03141708)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01171708)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01181708)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01191708)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A1708)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E1708)

#define DDRDATA7CH1_CR_DDRCRDATACONTROL4_REG                           (0x0000170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x0100170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x0101170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x0302170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x0105170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x0106170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x0107170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x0108170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x0209170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x0110170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x0111170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x0112170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x0513170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x0518170C)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_spare2_OFF                  (29)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_spare2_WID                  ( 3)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_spare2_MSK                  (0xE0000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_spare2_MIN                  (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_spare2_MAX                  (7) // 0x00000007
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_spare2_DEF                  (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL4_spare2_HSH                  (0x031D170C)

#define DDRDATA7CH1_CR_DDRCRDATACONTROL5_REG                           (0x00001710)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08001710)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01081710)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02091710)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B1710)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F1710)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08101710)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08181710)

#define DDRDATA7CH1_CR_DDRCRDATACONTROL6_REG                           (0x00001714)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01001714)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02011714)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01031714)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05041714)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01091714)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A1714)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B1714)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C1714)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E1714)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F1714)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08101714)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01181714)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01191714)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A1714)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D1714)

#define DDRDATA7CH1_CR_DDRCRDATACONTROL7_REG                           (0x00001718)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06001718)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06061718)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C1718)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06121718)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04181718)

  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA7CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C1718)

#define DDRDATA7CH1_CR_DELTADQSRANK0_REG                               (0x0000171C)

  #define DDRDATA7CH1_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA7CH1_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA7CH1_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA7CH1_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA7CH1_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA7CH1_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A00171C)

  #define DDRDATA7CH1_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA7CH1_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA7CH1_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA7CH1_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA7CH1_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA7CH1_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA7CH1_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A171C)

#define DDRDATA7CH1_CR_DELTADQSRANK1_REG                               (0x00001720)

  #define DDRDATA7CH1_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA7CH1_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA7CH1_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA7CH1_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA7CH1_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA7CH1_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A001720)

  #define DDRDATA7CH1_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA7CH1_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA7CH1_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA7CH1_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA7CH1_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA7CH1_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA7CH1_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A1720)

#define DDRDATA7CH1_CR_DELTADQSRANK2_REG                               (0x00001724)

  #define DDRDATA7CH1_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA7CH1_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA7CH1_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA7CH1_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA7CH1_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA7CH1_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A001724)

  #define DDRDATA7CH1_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA7CH1_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA7CH1_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA7CH1_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA7CH1_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA7CH1_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA7CH1_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A1724)

#define DDRDATA7CH1_CR_DELTADQSRANK3_REG                               (0x00001728)

  #define DDRDATA7CH1_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA7CH1_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA7CH1_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA7CH1_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA7CH1_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA7CH1_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A001728)

  #define DDRDATA7CH1_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA7CH1_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA7CH1_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA7CH1_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA7CH1_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA7CH1_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA7CH1_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A1728)

#define DDRDATA7CH1_CR_RXCONTROL3RANK0_REG                             (0x0000172C)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x0600172C)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x0606172C)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C172C)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x0511172C)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x0516172C)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B172C)

#define DDRDATA7CH1_CR_RXCONTROL3RANK1_REG                             (0x00001730)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x06001730)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x06061730)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C1730)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x05111730)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x05161730)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B1730)

#define DDRDATA7CH1_CR_RXCONTROL3RANK2_REG                             (0x00001734)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x06001734)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x06061734)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C1734)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x05111734)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x05161734)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B1734)

#define DDRDATA7CH1_CR_RXCONTROL3RANK3_REG                             (0x00001738)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x06001738)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x06061738)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C1738)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x05111738)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x05161738)

  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA7CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B1738)

#define DDRDATA7CH1_CR_TXPERBITHIRANK0_REG                             (0x0000173C)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x0600173C)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x0606173C)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C173C)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x0612173C)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK0_Spare_HSH                     (0x0818173C)

#define DDRDATA7CH1_CR_TXPERBITHIRANK1_REG                             (0x00001740)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x06001740)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x06061740)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C1740)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x06121740)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK1_Spare_HSH                     (0x08181740)

#define DDRDATA7CH1_CR_TXPERBITHIRANK2_REG                             (0x00001744)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x06001744)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x06061744)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C1744)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x06121744)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK2_Spare_HSH                     (0x08181744)

#define DDRDATA7CH1_CR_TXPERBITHIRANK3_REG                             (0x00001748)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x06001748)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x06061748)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C1748)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x06121748)

  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_TXPERBITHIRANK3_Spare_HSH                     (0x08181748)

#define DDRDATA7CH1_CR_DCCDATACONTROL0_REG                             (0x0000174C)

  #define DDRDATA7CH1_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x0100174C)

  #define DDRDATA7CH1_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x0201174C)

  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x0103174C)

  #define DDRDATA7CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x0204174C)

  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x0706174C)

  #define DDRDATA7CH1_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D174C)

  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA7CH1_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C174C)

#define DDRDATA7CH1_CR_DCCDATACONTROL1_REG                             (0x00001750)

  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x06001750)

  #define DDRDATA7CH1_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x02061750)

  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x04081750)

  #define DDRDATA7CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C1750)

  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E1750)

  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F1750)

  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F101750)

  #define DDRDATA7CH1_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F1750)

#define DDRDATA7CH1_CR_DCCDATACONTROL2_REG                             (0x00001754)

  #define DDRDATA7CH1_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x06001754)

  #define DDRDATA7CH1_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x03061754)

  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D091754)

  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x05161754)

  #define DDRDATA7CH1_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B1754)

  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C1754)

#define DDRDATA7CH1_CR_DCCDATACONTROL3_REG                             (0x00001758)

  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B001758)

  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B1758)

  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x09141758)

  #define DDRDATA7CH1_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D1758)

#define DDRDATA7CH1_CR_DCCDATACONTROL4_REG                             (0x0000175C)

  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x0900175C)

  #define DDRDATA7CH1_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_Spare_HSH                     (0x0109175C)

  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A175C)

  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x0610175C)

  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x0616175C)

  #define DDRDATA7CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C175C)

#define DDRDATA7CH1_CR_DCCDATACONTROL5_REG                             (0x00001760)

  #define DDRDATA7CH1_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_Spare_HSH                     (0x02001760)

  #define DDRDATA7CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x01021760)

  #define DDRDATA7CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x06031760)

  #define DDRDATA7CH1_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x05091760)

  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E1760)

  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B141760)

  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F1760)

#define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_REG                         (0x00001764)

  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B001764)

  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B1764)

  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x09141764)

  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D1764)

#define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_REG                         (0x00001768)

  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x09001768)

  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x01091768)

  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A1768)

  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B1768)

  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A1768)

  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B1768)

#define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_REG                         (0x0000176C)

  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x1000176C)

  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x0710176C)

  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x0717176C)

  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E176C)

#define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x00001770)

  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B001770)

  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B1770)

  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C1770)

#define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x00001774)

  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x09001774)

  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x11091774)

  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A1774)

#define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x00001778)

  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x09001778)

  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x11091778)

  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A1778)

#define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x0000177C)

  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x0900177C)

  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x1109177C)

  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A177C)

#define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_REG                        (0x00001780)

  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06001780)

  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06061780)

  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C1780)

  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06121780)

  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07181780)

  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F1780)

#define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00001784)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06001784)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06061784)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C1784)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06121784)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06181784)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E1784)

#define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00001788)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06001788)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06061788)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C1788)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06121788)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06181788)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E1788)

#define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_REG                       (0x0000178C)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x0600178C)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x0606178C)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C178C)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x0612178C)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x0618178C)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E178C)

#define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00001790)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06001790)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06061790)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C1790)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06121790)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06181790)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E1790)

#define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00001794)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06001794)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06061794)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C1794)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06121794)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06181794)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E1794)

#define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00001798)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06001798)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06061798)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C1798)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06121798)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02181798)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A1798)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D1798)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E1798)

#define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_REG                       (0x0000179C)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x0600179C)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x0606179C)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C179C)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x0612179C)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x0618179C)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E179C)

#define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_REG                       (0x000017A0)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x060017A0)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x060617A0)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C17A0)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x061217A0)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x061817A0)

  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA7CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E17A0)

#define DDRDATA7CH1_CR_DCCDATADCCPILUT0_REG                            (0x000017A4)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x060017A4)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x060617A4)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C17A4)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x061217A4)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x061817A4)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E17A4)

#define DDRDATA7CH1_CR_DCCDATADCCPILUT1_REG                            (0x000017A8)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x060017A8)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x060617A8)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C17A8)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x061217A8)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x061817A8)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E17A8)

#define DDRDATA7CH1_CR_DCCDATADCCPILUT2_REG                            (0x000017AC)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x060017AC)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x060617AC)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C17AC)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x061217AC)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x061817AC)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E17AC)

#define DDRDATA7CH1_CR_DCCDATADCCPILUT3_REG                            (0x000017B0)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x060017B0)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x060617B0)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C17B0)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x061217B0)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x061817B0)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E17B0)

#define DDRDATA7CH1_CR_DCCDATADCCPILUT4_REG                            (0x000017B4)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x060017B4)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x060617B4)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C17B4)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x061217B4)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x061817B4)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E17B4)

#define DDRDATA7CH1_CR_DCCDATADCCPILUT5_REG                            (0x000017B8)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x060017B8)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x060617B8)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C17B8)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x061217B8)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x061817B8)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E17B8)

#define DDRDATA7CH1_CR_DCCDATADCCPILUT6_REG                            (0x000017BC)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x060017BC)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x060617BC)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C17BC)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x061217BC)

  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA7CH1_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x081817BC)

#define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_REG                        (0x000017C0)

  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x060017C0)

  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x060617C0)

  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C17C0)

  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x061217C0)

  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x061817C0)

  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E17C0)

#define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_REG                        (0x000017C4)

  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x060017C4)

  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x060617C4)

  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C17C4)

  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x061217C4)

  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x061817C4)

  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E17C4)

#define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x000017C8)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x060017C8)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x060617C8)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C17C8)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x061217C8)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x021817C8)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A17C8)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C17C8)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E17C8)

#define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x000017CC)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x060017CC)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x060617CC)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C17CC)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x061217CC)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x081817CC)

#define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x000017D0)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x060017D0)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x060617D0)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C17D0)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x061217D0)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x061817D0)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E17D0)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F17D0)

#define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x000017D4)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x060017D4)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x060617D4)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C17D4)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x061217D4)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x061817D4)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E17D4)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F17D4)

#define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x000017D8)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x060017D8)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x060617D8)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C17D8)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x061217D8)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x061817D8)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E17D8)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F17D8)

#define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x000017DC)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x060017DC)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x060617DC)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C17DC)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x061217DC)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x061817DC)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E17DC)

  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA7CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F17DC)

#define DDRDATA8CH0_CR_RXCONTROL0RANK0_REG                             (0x00001800)

  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B001800)

  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B1800)

  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07121800)

  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07191800)

#define DDRDATA8CH0_CR_RXCONTROL0RANK1_REG                             (0x00001804)

  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B001804)

  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B1804)

  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07121804)

  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07191804)

#define DDRDATA8CH0_CR_RXCONTROL0RANK2_REG                             (0x00001808)

  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B001808)

  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B1808)

  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07121808)

  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07191808)

#define DDRDATA8CH0_CR_RXCONTROL0RANK3_REG                             (0x0000180C)

  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B00180C)

  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B180C)

  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x0712180C)

  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x0719180C)

#define DDRDATA8CH0_CR_RXCONTROL1RANK0_REG                             (0x00001810)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06001810)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06061810)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C1810)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06121810)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02181810)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A1810)

#define DDRDATA8CH0_CR_RXCONTROL1RANK1_REG                             (0x00001814)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06001814)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06061814)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C1814)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06121814)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02181814)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A1814)

#define DDRDATA8CH0_CR_RXCONTROL1RANK2_REG                             (0x00001818)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06001818)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06061818)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C1818)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06121818)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02181818)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A1818)

#define DDRDATA8CH0_CR_RXCONTROL1RANK3_REG                             (0x0000181C)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x0600181C)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x0606181C)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C181C)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x0612181C)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x0218181C)

  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A181C)

#define DDRDATA8CH0_CR_TXTRAINRANK0_REG                                (0x00001820)

  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A001820)

  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A1820)

  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxEqualization_HSH               (0x06141820)

  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A1820)

  #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E1820)

#define DDRDATA8CH0_CR_TXTRAINRANK1_REG                                (0x00001824)

  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A001824)

  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A1824)

  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxEqualization_HSH               (0x06141824)

  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A1824)

  #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C1824)

#define DDRDATA8CH0_CR_TXTRAINRANK2_REG                                (0x00001828)

  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A001828)

  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A1828)

  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_TxEqualization_HSH               (0x06141828)

  #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A1828)

#define DDRDATA8CH0_CR_TXTRAINRANK3_REG                                (0x0000182C)

  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A00182C)

  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A182C)

  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_TxEqualization_HSH               (0x0614182C)

  #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA8CH0_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A182C)

#define DDRDATA8CH0_CR_TXPERBITLOWRANK0_REG                            (0x00001830)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x06001830)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x06061830)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C1830)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x06121830)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x08181830)

#define DDRDATA8CH0_CR_TXPERBITLOWRANK1_REG                            (0x00001834)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x06001834)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x06061834)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C1834)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x06121834)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x08181834)

#define DDRDATA8CH0_CR_TXPERBITLOWRANK2_REG                            (0x00001838)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x06001838)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x06061838)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C1838)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x06121838)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x08181838)

#define DDRDATA8CH0_CR_TXPERBITLOWRANK3_REG                            (0x0000183C)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x0600183C)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x0606183C)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C183C)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x0612183C)

  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x0818183C)

#define DDRDATA8CH0_CR_RCOMPDATA0_REG                                  (0x00001840)

  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x06001840)

  #define DDRDATA8CH0_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA8CH0_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA8CH0_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA8CH0_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA8CH0_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA8CH0_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA8CH0_CR_RCOMPDATA0_Rsvd_HSH                           (0x08061840)

  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA8CH0_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E1840)

  #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA8CH0_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x05141840)

  #define DDRDATA8CH0_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA8CH0_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA8CH0_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA8CH0_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA8CH0_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA8CH0_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA8CH0_CR_RCOMPDATA0_Spare_HSH                          (0x07191840)

#define DDRDATA8CH0_CR_RCOMPDATA1_REG                                  (0x00001844)

  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x06001844)

  #define DDRDATA8CH0_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA8CH0_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA8CH0_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA8CH0_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA8CH0_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA8CH0_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA8CH0_CR_RCOMPDATA1_spare_HSH                          (0x14061844)

  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA8CH0_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A1844)

#define DDRDATA8CH0_CR_DDRCRDATACONTROL8_REG                           (0x00001848)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x02001848)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x02021848)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x02041848)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x02061848)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x01081848)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL8_spare_HSH                   (0x17091848)

#define DDRDATA8CH0_CR_RCOMPDATA2_REG                                  (0x0000184C)

  #define DDRDATA8CH0_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA8CH0_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA8CH0_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA8CH0_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA8CH0_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA8CH0_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x0800184C)

  #define DDRDATA8CH0_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA8CH0_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA8CH0_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA8CH0_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA8CH0_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA8CH0_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x0808184C)

  #define DDRDATA8CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA8CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA8CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA8CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA8CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA8CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x0610184C)

  #define DDRDATA8CH0_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA8CH0_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA8CH0_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA8CH0_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA8CH0_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA8CH0_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA8CH0_CR_RCOMPDATA2_Spare_HSH                          (0x0A16184C)

#define DDRDATA8CH0_CR_RXCONTROL2RANK0_REG                             (0x00001850)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x06001850)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x06061850)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C1850)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x05111850)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x05161850)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B1850)

#define DDRDATA8CH0_CR_RXCONTROL2RANK1_REG                             (0x00001854)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x06001854)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x06061854)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C1854)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x05111854)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x05161854)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B1854)

#define DDRDATA8CH0_CR_RXCONTROL2RANK2_REG                             (0x00001858)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x06001858)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x06061858)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C1858)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x05111858)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x05161858)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B1858)

#define DDRDATA8CH0_CR_RXCONTROL2RANK3_REG                             (0x0000185C)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x0600185C)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x0606185C)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C185C)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x0511185C)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x0516185C)

  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B185C)

#define DDRDATA8CH0_CR_DATATRAINFEEDBACK_REG                           (0x00001860)

  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x09001860)

  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA8CH0_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x17091860)

#define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_REG                         (0x00001868)

  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x86001868)

  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x86061868)

  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C1868)

  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x85111868)

  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x05161868)

  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B1868)

#define DDRDATA8CH0_CR_DDRCRDATACONTROL1_REG                           (0x0000186C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x8400186C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x0204186C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x0106186C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x0307186C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A186C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E186C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x0313186C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x8516186C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B186C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E186C)

#define DDRDATA8CH0_CR_DDRCRDATACONTROL2_REG                           (0x00001870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x05001870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x01051870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x01061870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x01071870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x01081870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x04091870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D1870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x01121870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x01131870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x01141870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x01151870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x01161870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x01171870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x01181870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x01191870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A1870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D1870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E1870)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F1870)

#define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x0000187C)

  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x8600187C)

  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x8706187C)

  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D187C)

  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x8613187C)

  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x8719187C)

#define DDRDATA8CH0_CR_DDRCRDATACONTROL0_REG                           (0x00001880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01001880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01011880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01021880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01031880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01041880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01051880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01061880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01071880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01081880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01091880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A1880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B1880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C1880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D1880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F1880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02131880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01151880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01161880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01171880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01181880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01191880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A1880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B1880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C1880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D1880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E1880)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F1880)

#define DDRDATA8CH0_CR_DDRCRDATACONTROL3_REG                           (0x00001888)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04001888)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02041888)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01061888)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01071888)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86081888)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E1888)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F1888)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03101888)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01131888)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03141888)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01171888)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01181888)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01191888)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A1888)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E1888)

#define DDRDATA8CH0_CR_DDRCRDATACONTROL4_REG                           (0x0000188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x0100188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x0101188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x0302188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x0105188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x0106188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x0107188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x0108188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x0209188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x0110188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x0111188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x0112188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x0513188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x0518188C)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_spare2_OFF                  (29)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_spare2_WID                  ( 3)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_spare2_MSK                  (0xE0000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_spare2_MIN                  (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_spare2_MAX                  (7) // 0x00000007
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_spare2_DEF                  (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL4_spare2_HSH                  (0x031D188C)

#define DDRDATA8CH0_CR_DDRCRDATACONTROL5_REG                           (0x00001890)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08001890)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01081890)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02091890)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B1890)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F1890)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08101890)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08181890)

#define DDRDATA8CH0_CR_DDRCRDATACONTROL6_REG                           (0x00001894)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01001894)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02011894)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01031894)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05041894)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01091894)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A1894)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B1894)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C1894)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E1894)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F1894)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08101894)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01181894)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01191894)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A1894)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D1894)

#define DDRDATA8CH0_CR_DDRCRDATACONTROL7_REG                           (0x00001898)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06001898)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06061898)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C1898)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06121898)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04181898)

  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA8CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C1898)

#define DDRDATA8CH0_CR_DELTADQSRANK0_REG                               (0x0000189C)

  #define DDRDATA8CH0_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA8CH0_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA8CH0_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA8CH0_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA8CH0_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA8CH0_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A00189C)

  #define DDRDATA8CH0_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA8CH0_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA8CH0_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA8CH0_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA8CH0_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA8CH0_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA8CH0_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A189C)

#define DDRDATA8CH0_CR_DELTADQSRANK1_REG                               (0x000018A0)

  #define DDRDATA8CH0_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA8CH0_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA8CH0_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA8CH0_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA8CH0_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA8CH0_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A0018A0)

  #define DDRDATA8CH0_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA8CH0_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA8CH0_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA8CH0_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA8CH0_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA8CH0_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA8CH0_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A18A0)

#define DDRDATA8CH0_CR_DELTADQSRANK2_REG                               (0x000018A4)

  #define DDRDATA8CH0_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA8CH0_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA8CH0_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA8CH0_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA8CH0_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA8CH0_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A0018A4)

  #define DDRDATA8CH0_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA8CH0_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA8CH0_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA8CH0_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA8CH0_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA8CH0_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA8CH0_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A18A4)

#define DDRDATA8CH0_CR_DELTADQSRANK3_REG                               (0x000018A8)

  #define DDRDATA8CH0_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA8CH0_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA8CH0_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA8CH0_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA8CH0_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA8CH0_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A0018A8)

  #define DDRDATA8CH0_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA8CH0_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA8CH0_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA8CH0_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA8CH0_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA8CH0_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA8CH0_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A18A8)

#define DDRDATA8CH0_CR_RXCONTROL3RANK0_REG                             (0x000018AC)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x060018AC)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x060618AC)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C18AC)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x051118AC)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x051618AC)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B18AC)

#define DDRDATA8CH0_CR_RXCONTROL3RANK1_REG                             (0x000018B0)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x060018B0)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x060618B0)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C18B0)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x051118B0)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x051618B0)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B18B0)

#define DDRDATA8CH0_CR_RXCONTROL3RANK2_REG                             (0x000018B4)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x060018B4)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x060618B4)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C18B4)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x051118B4)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x051618B4)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B18B4)

#define DDRDATA8CH0_CR_RXCONTROL3RANK3_REG                             (0x000018B8)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x060018B8)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x060618B8)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C18B8)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x051118B8)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x051618B8)

  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B18B8)

#define DDRDATA8CH0_CR_TXPERBITHIRANK0_REG                             (0x000018BC)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x060018BC)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x060618BC)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C18BC)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x061218BC)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK0_Spare_HSH                     (0x081818BC)

#define DDRDATA8CH0_CR_TXPERBITHIRANK1_REG                             (0x000018C0)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x060018C0)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x060618C0)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C18C0)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x061218C0)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK1_Spare_HSH                     (0x081818C0)

#define DDRDATA8CH0_CR_TXPERBITHIRANK2_REG                             (0x000018C4)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x060018C4)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x060618C4)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C18C4)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x061218C4)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK2_Spare_HSH                     (0x081818C4)

#define DDRDATA8CH0_CR_TXPERBITHIRANK3_REG                             (0x000018C8)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x060018C8)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x060618C8)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C18C8)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x061218C8)

  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_TXPERBITHIRANK3_Spare_HSH                     (0x081818C8)

#define DDRDATA8CH0_CR_DCCDATACONTROL0_REG                             (0x000018CC)

  #define DDRDATA8CH0_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x010018CC)

  #define DDRDATA8CH0_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x020118CC)

  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x010318CC)

  #define DDRDATA8CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x020418CC)

  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x070618CC)

  #define DDRDATA8CH0_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D18CC)

  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA8CH0_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C18CC)

#define DDRDATA8CH0_CR_DCCDATACONTROL1_REG                             (0x000018D0)

  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x060018D0)

  #define DDRDATA8CH0_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x020618D0)

  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x040818D0)

  #define DDRDATA8CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C18D0)

  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E18D0)

  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F18D0)

  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F1018D0)

  #define DDRDATA8CH0_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F18D0)

#define DDRDATA8CH0_CR_DCCDATACONTROL2_REG                             (0x000018D4)

  #define DDRDATA8CH0_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x060018D4)

  #define DDRDATA8CH0_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x030618D4)

  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D0918D4)

  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x051618D4)

  #define DDRDATA8CH0_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B18D4)

  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C18D4)

#define DDRDATA8CH0_CR_DCCDATACONTROL3_REG                             (0x000018D8)

  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B0018D8)

  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B18D8)

  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x091418D8)

  #define DDRDATA8CH0_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D18D8)

#define DDRDATA8CH0_CR_DCCDATACONTROL4_REG                             (0x000018DC)

  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x090018DC)

  #define DDRDATA8CH0_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_Spare_HSH                     (0x010918DC)

  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A18DC)

  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x061018DC)

  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x061618DC)

  #define DDRDATA8CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C18DC)

#define DDRDATA8CH0_CR_DCCDATACONTROL5_REG                             (0x000018E0)

  #define DDRDATA8CH0_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_Spare_HSH                     (0x020018E0)

  #define DDRDATA8CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x010218E0)

  #define DDRDATA8CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x060318E0)

  #define DDRDATA8CH0_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x050918E0)

  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E18E0)

  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B1418E0)

  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F18E0)

#define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_REG                         (0x000018E4)

  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B0018E4)

  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B18E4)

  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x091418E4)

  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D18E4)

#define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_REG                         (0x000018E8)

  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x090018E8)

  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x010918E8)

  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A18E8)

  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B18E8)

  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A18E8)

  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B18E8)

#define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_REG                         (0x000018EC)

  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x100018EC)

  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x071018EC)

  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x071718EC)

  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E18EC)

#define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x000018F0)

  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B0018F0)

  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B18F0)

  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C18F0)

#define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x000018F4)

  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x090018F4)

  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x110918F4)

  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A18F4)

#define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x000018F8)

  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x090018F8)

  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x110918F8)

  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A18F8)

#define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x000018FC)

  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x090018FC)

  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x110918FC)

  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A18FC)

#define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_REG                        (0x00001900)

  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06001900)

  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06061900)

  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C1900)

  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06121900)

  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07181900)

  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F1900)

#define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00001904)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06001904)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06061904)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C1904)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06121904)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06181904)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E1904)

#define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00001908)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06001908)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06061908)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C1908)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06121908)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06181908)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E1908)

#define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_REG                       (0x0000190C)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x0600190C)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x0606190C)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C190C)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x0612190C)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x0618190C)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E190C)

#define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00001910)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06001910)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06061910)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C1910)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06121910)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06181910)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E1910)

#define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00001914)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06001914)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06061914)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C1914)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06121914)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06181914)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E1914)

#define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00001918)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06001918)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06061918)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C1918)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06121918)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02181918)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A1918)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D1918)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E1918)

#define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_REG                       (0x0000191C)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x0600191C)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x0606191C)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C191C)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x0612191C)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x0618191C)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E191C)

#define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_REG                       (0x00001920)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x06001920)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x06061920)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C1920)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x06121920)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x06181920)

  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA8CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E1920)

#define DDRDATA8CH0_CR_DCCDATADCCPILUT0_REG                            (0x00001924)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x06001924)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x06061924)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C1924)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x06121924)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x06181924)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E1924)

#define DDRDATA8CH0_CR_DCCDATADCCPILUT1_REG                            (0x00001928)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x06001928)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x06061928)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C1928)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x06121928)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x06181928)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E1928)

#define DDRDATA8CH0_CR_DCCDATADCCPILUT2_REG                            (0x0000192C)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x0600192C)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x0606192C)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C192C)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x0612192C)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x0618192C)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E192C)

#define DDRDATA8CH0_CR_DCCDATADCCPILUT3_REG                            (0x00001930)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x06001930)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x06061930)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C1930)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x06121930)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x06181930)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E1930)

#define DDRDATA8CH0_CR_DCCDATADCCPILUT4_REG                            (0x00001934)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x06001934)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x06061934)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C1934)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x06121934)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x06181934)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E1934)

#define DDRDATA8CH0_CR_DCCDATADCCPILUT5_REG                            (0x00001938)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x06001938)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x06061938)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C1938)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x06121938)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x06181938)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E1938)

#define DDRDATA8CH0_CR_DCCDATADCCPILUT6_REG                            (0x0000193C)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x0600193C)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x0606193C)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C193C)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x0612193C)

  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH0_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x0818193C)

#define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_REG                        (0x00001940)

  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x06001940)

  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x06061940)

  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C1940)

  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x06121940)

  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x06181940)

  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E1940)

#define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_REG                        (0x00001944)

  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x06001944)

  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x06061944)

  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C1944)

  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x06121944)

  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x06181944)

  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E1944)

#define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x00001948)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x06001948)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x06061948)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C1948)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x06121948)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x02181948)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A1948)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C1948)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E1948)

#define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x0000194C)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x0600194C)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x0606194C)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C194C)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x0612194C)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x0818194C)

#define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x00001950)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x06001950)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x06061950)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C1950)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x06121950)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x06181950)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E1950)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F1950)

#define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x00001954)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x06001954)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x06061954)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C1954)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x06121954)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x06181954)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E1954)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F1954)

#define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x00001958)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x06001958)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x06061958)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C1958)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x06121958)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x06181958)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E1958)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F1958)

#define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x0000195C)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x0600195C)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x0606195C)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C195C)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x0612195C)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x0618195C)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E195C)

  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA8CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F195C)

#define DDRDATA8CH1_CR_RXCONTROL0RANK0_REG                             (0x00001980)

  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B001980)

  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B1980)

  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07121980)

  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07191980)

#define DDRDATA8CH1_CR_RXCONTROL0RANK1_REG                             (0x00001984)

  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B001984)

  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B1984)

  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07121984)

  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07191984)

#define DDRDATA8CH1_CR_RXCONTROL0RANK2_REG                             (0x00001988)

  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B001988)

  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B1988)

  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07121988)

  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07191988)

#define DDRDATA8CH1_CR_RXCONTROL0RANK3_REG                             (0x0000198C)

  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B00198C)

  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B198C)

  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x0712198C)

  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x0719198C)

#define DDRDATA8CH1_CR_RXCONTROL1RANK0_REG                             (0x00001990)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06001990)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06061990)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C1990)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06121990)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02181990)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A1990)

#define DDRDATA8CH1_CR_RXCONTROL1RANK1_REG                             (0x00001994)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06001994)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06061994)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C1994)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06121994)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02181994)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A1994)

#define DDRDATA8CH1_CR_RXCONTROL1RANK2_REG                             (0x00001998)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06001998)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06061998)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C1998)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06121998)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02181998)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A1998)

#define DDRDATA8CH1_CR_RXCONTROL1RANK3_REG                             (0x0000199C)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x0600199C)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x0606199C)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C199C)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x0612199C)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x0218199C)

  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A199C)

#define DDRDATA8CH1_CR_TXTRAINRANK0_REG                                (0x000019A0)

  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A0019A0)

  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A19A0)

  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxEqualization_HSH               (0x061419A0)

  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A19A0)

  #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E19A0)

#define DDRDATA8CH1_CR_TXTRAINRANK1_REG                                (0x000019A4)

  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A0019A4)

  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A19A4)

  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxEqualization_HSH               (0x061419A4)

  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A19A4)

  #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C19A4)

#define DDRDATA8CH1_CR_TXTRAINRANK2_REG                                (0x000019A8)

  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A0019A8)

  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A19A8)

  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_TxEqualization_HSH               (0x061419A8)

  #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A19A8)

#define DDRDATA8CH1_CR_TXTRAINRANK3_REG                                (0x000019AC)

  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A0019AC)

  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A19AC)

  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_TxEqualization_HSH               (0x061419AC)

  #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA8CH1_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A19AC)

#define DDRDATA8CH1_CR_TXPERBITLOWRANK0_REG                            (0x000019B0)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x060019B0)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x060619B0)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C19B0)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x061219B0)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x081819B0)

#define DDRDATA8CH1_CR_TXPERBITLOWRANK1_REG                            (0x000019B4)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x060019B4)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x060619B4)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C19B4)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x061219B4)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x081819B4)

#define DDRDATA8CH1_CR_TXPERBITLOWRANK2_REG                            (0x000019B8)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x060019B8)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x060619B8)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C19B8)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x061219B8)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x081819B8)

#define DDRDATA8CH1_CR_TXPERBITLOWRANK3_REG                            (0x000019BC)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x060019BC)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x060619BC)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C19BC)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x061219BC)

  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x081819BC)

#define DDRDATA8CH1_CR_RCOMPDATA0_REG                                  (0x000019C0)

  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x060019C0)

  #define DDRDATA8CH1_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA8CH1_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA8CH1_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA8CH1_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA8CH1_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA8CH1_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA8CH1_CR_RCOMPDATA0_Rsvd_HSH                           (0x080619C0)

  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA8CH1_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E19C0)

  #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA8CH1_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x051419C0)

  #define DDRDATA8CH1_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA8CH1_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA8CH1_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA8CH1_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA8CH1_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA8CH1_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA8CH1_CR_RCOMPDATA0_Spare_HSH                          (0x071919C0)

#define DDRDATA8CH1_CR_RCOMPDATA1_REG                                  (0x000019C4)

  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x060019C4)

  #define DDRDATA8CH1_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA8CH1_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA8CH1_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA8CH1_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA8CH1_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA8CH1_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA8CH1_CR_RCOMPDATA1_spare_HSH                          (0x140619C4)

  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA8CH1_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A19C4)

#define DDRDATA8CH1_CR_DDRCRDATACONTROL8_REG                           (0x000019C8)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x020019C8)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x020219C8)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x020419C8)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x020619C8)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x010819C8)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL8_spare_HSH                   (0x170919C8)

#define DDRDATA8CH1_CR_RCOMPDATA2_REG                                  (0x000019CC)

  #define DDRDATA8CH1_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA8CH1_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA8CH1_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA8CH1_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA8CH1_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA8CH1_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x080019CC)

  #define DDRDATA8CH1_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA8CH1_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA8CH1_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA8CH1_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA8CH1_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA8CH1_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x080819CC)

  #define DDRDATA8CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA8CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA8CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA8CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA8CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA8CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x061019CC)

  #define DDRDATA8CH1_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA8CH1_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA8CH1_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA8CH1_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA8CH1_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA8CH1_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA8CH1_CR_RCOMPDATA2_Spare_HSH                          (0x0A1619CC)

#define DDRDATA8CH1_CR_RXCONTROL2RANK0_REG                             (0x000019D0)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x060019D0)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x060619D0)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C19D0)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x051119D0)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x051619D0)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B19D0)

#define DDRDATA8CH1_CR_RXCONTROL2RANK1_REG                             (0x000019D4)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x060019D4)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x060619D4)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C19D4)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x051119D4)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x051619D4)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B19D4)

#define DDRDATA8CH1_CR_RXCONTROL2RANK2_REG                             (0x000019D8)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x060019D8)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x060619D8)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C19D8)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x051119D8)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x051619D8)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B19D8)

#define DDRDATA8CH1_CR_RXCONTROL2RANK3_REG                             (0x000019DC)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x060019DC)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x060619DC)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C19DC)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x051119DC)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x051619DC)

  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B19DC)

#define DDRDATA8CH1_CR_DATATRAINFEEDBACK_REG                           (0x000019E0)

  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x090019E0)

  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA8CH1_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x170919E0)

#define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_REG                         (0x000019E8)

  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x860019E8)

  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x860619E8)

  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C19E8)

  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x851119E8)

  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x051619E8)

  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B19E8)

#define DDRDATA8CH1_CR_DDRCRDATACONTROL1_REG                           (0x000019EC)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x840019EC)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x020419EC)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x010619EC)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x030719EC)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A19EC)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E19EC)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x031319EC)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x851619EC)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B19EC)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E19EC)

#define DDRDATA8CH1_CR_DDRCRDATACONTROL2_REG                           (0x000019F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x050019F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x010519F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x010619F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x010719F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x010819F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x040919F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D19F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x011219F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x011319F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x011419F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x011519F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x011619F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x011719F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x011819F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x011919F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A19F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D19F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E19F0)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F19F0)

#define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x000019FC)

  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x860019FC)

  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x870619FC)

  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D19FC)

  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x861319FC)

  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x871919FC)

#define DDRDATA8CH1_CR_DDRCRDATACONTROL0_REG                           (0x00001A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01001A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01011A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01021A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01031A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01041A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01051A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01061A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01071A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01081A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01091A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A1A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B1A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C1A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D1A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F1A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02131A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01151A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01161A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01171A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01181A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01191A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A1A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B1A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C1A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D1A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E1A00)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F1A00)

#define DDRDATA8CH1_CR_DDRCRDATACONTROL3_REG                           (0x00001A08)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04001A08)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02041A08)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01061A08)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01071A08)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86081A08)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E1A08)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F1A08)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03101A08)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01131A08)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03141A08)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01171A08)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01181A08)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01191A08)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A1A08)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E1A08)

#define DDRDATA8CH1_CR_DDRCRDATACONTROL4_REG                           (0x00001A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x01001A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x01011A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x03021A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x01051A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x01061A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x01071A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x01081A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x02091A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B1A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C1A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D1A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E1A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F1A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x01101A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x01111A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x01121A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x05131A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x05181A0C)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_spare2_OFF                  (29)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_spare2_WID                  ( 3)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_spare2_MSK                  (0xE0000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_spare2_MIN                  (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_spare2_MAX                  (7) // 0x00000007
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_spare2_DEF                  (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL4_spare2_HSH                  (0x031D1A0C)

#define DDRDATA8CH1_CR_DDRCRDATACONTROL5_REG                           (0x00001A10)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08001A10)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01081A10)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02091A10)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B1A10)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F1A10)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08101A10)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08181A10)

#define DDRDATA8CH1_CR_DDRCRDATACONTROL6_REG                           (0x00001A14)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01001A14)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02011A14)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01031A14)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05041A14)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01091A14)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A1A14)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B1A14)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C1A14)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E1A14)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F1A14)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08101A14)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01181A14)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01191A14)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A1A14)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D1A14)

#define DDRDATA8CH1_CR_DDRCRDATACONTROL7_REG                           (0x00001A18)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06001A18)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06061A18)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C1A18)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06121A18)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04181A18)

  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA8CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C1A18)

#define DDRDATA8CH1_CR_DELTADQSRANK0_REG                               (0x00001A1C)

  #define DDRDATA8CH1_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA8CH1_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA8CH1_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA8CH1_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA8CH1_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA8CH1_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A001A1C)

  #define DDRDATA8CH1_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA8CH1_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA8CH1_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA8CH1_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA8CH1_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA8CH1_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA8CH1_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A1A1C)

#define DDRDATA8CH1_CR_DELTADQSRANK1_REG                               (0x00001A20)

  #define DDRDATA8CH1_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA8CH1_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA8CH1_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA8CH1_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA8CH1_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA8CH1_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A001A20)

  #define DDRDATA8CH1_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA8CH1_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA8CH1_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA8CH1_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA8CH1_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA8CH1_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA8CH1_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A1A20)

#define DDRDATA8CH1_CR_DELTADQSRANK2_REG                               (0x00001A24)

  #define DDRDATA8CH1_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA8CH1_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA8CH1_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA8CH1_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA8CH1_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA8CH1_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A001A24)

  #define DDRDATA8CH1_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA8CH1_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA8CH1_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA8CH1_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA8CH1_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA8CH1_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA8CH1_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A1A24)

#define DDRDATA8CH1_CR_DELTADQSRANK3_REG                               (0x00001A28)

  #define DDRDATA8CH1_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA8CH1_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA8CH1_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA8CH1_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA8CH1_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA8CH1_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A001A28)

  #define DDRDATA8CH1_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA8CH1_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA8CH1_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA8CH1_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA8CH1_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA8CH1_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA8CH1_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A1A28)

#define DDRDATA8CH1_CR_RXCONTROL3RANK0_REG                             (0x00001A2C)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x06001A2C)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x06061A2C)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C1A2C)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x05111A2C)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x05161A2C)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B1A2C)

#define DDRDATA8CH1_CR_RXCONTROL3RANK1_REG                             (0x00001A30)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x06001A30)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x06061A30)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C1A30)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x05111A30)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x05161A30)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B1A30)

#define DDRDATA8CH1_CR_RXCONTROL3RANK2_REG                             (0x00001A34)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x06001A34)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x06061A34)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C1A34)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x05111A34)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x05161A34)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B1A34)

#define DDRDATA8CH1_CR_RXCONTROL3RANK3_REG                             (0x00001A38)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x06001A38)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x06061A38)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C1A38)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x05111A38)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x05161A38)

  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA8CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B1A38)

#define DDRDATA8CH1_CR_TXPERBITHIRANK0_REG                             (0x00001A3C)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x06001A3C)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x06061A3C)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C1A3C)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x06121A3C)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK0_Spare_HSH                     (0x08181A3C)

#define DDRDATA8CH1_CR_TXPERBITHIRANK1_REG                             (0x00001A40)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x06001A40)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x06061A40)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C1A40)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x06121A40)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK1_Spare_HSH                     (0x08181A40)

#define DDRDATA8CH1_CR_TXPERBITHIRANK2_REG                             (0x00001A44)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x06001A44)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x06061A44)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C1A44)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x06121A44)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK2_Spare_HSH                     (0x08181A44)

#define DDRDATA8CH1_CR_TXPERBITHIRANK3_REG                             (0x00001A48)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x06001A48)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x06061A48)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C1A48)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x06121A48)

  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_TXPERBITHIRANK3_Spare_HSH                     (0x08181A48)

#define DDRDATA8CH1_CR_DCCDATACONTROL0_REG                             (0x00001A4C)

  #define DDRDATA8CH1_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x01001A4C)

  #define DDRDATA8CH1_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x02011A4C)

  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x01031A4C)

  #define DDRDATA8CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x02041A4C)

  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x07061A4C)

  #define DDRDATA8CH1_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D1A4C)

  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA8CH1_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C1A4C)

#define DDRDATA8CH1_CR_DCCDATACONTROL1_REG                             (0x00001A50)

  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x06001A50)

  #define DDRDATA8CH1_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x02061A50)

  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x04081A50)

  #define DDRDATA8CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C1A50)

  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E1A50)

  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F1A50)

  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F101A50)

  #define DDRDATA8CH1_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F1A50)

#define DDRDATA8CH1_CR_DCCDATACONTROL2_REG                             (0x00001A54)

  #define DDRDATA8CH1_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x06001A54)

  #define DDRDATA8CH1_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x03061A54)

  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D091A54)

  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x05161A54)

  #define DDRDATA8CH1_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B1A54)

  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C1A54)

#define DDRDATA8CH1_CR_DCCDATACONTROL3_REG                             (0x00001A58)

  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B001A58)

  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B1A58)

  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x09141A58)

  #define DDRDATA8CH1_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D1A58)

#define DDRDATA8CH1_CR_DCCDATACONTROL4_REG                             (0x00001A5C)

  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x09001A5C)

  #define DDRDATA8CH1_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_Spare_HSH                     (0x01091A5C)

  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A1A5C)

  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x06101A5C)

  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x06161A5C)

  #define DDRDATA8CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C1A5C)

#define DDRDATA8CH1_CR_DCCDATACONTROL5_REG                             (0x00001A60)

  #define DDRDATA8CH1_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_Spare_HSH                     (0x02001A60)

  #define DDRDATA8CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x01021A60)

  #define DDRDATA8CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x06031A60)

  #define DDRDATA8CH1_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x05091A60)

  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E1A60)

  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B141A60)

  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F1A60)

#define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_REG                         (0x00001A64)

  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B001A64)

  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B1A64)

  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x09141A64)

  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D1A64)

#define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_REG                         (0x00001A68)

  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x09001A68)

  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x01091A68)

  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A1A68)

  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B1A68)

  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A1A68)

  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B1A68)

#define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_REG                         (0x00001A6C)

  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x10001A6C)

  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x07101A6C)

  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x07171A6C)

  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E1A6C)

#define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x00001A70)

  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B001A70)

  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B1A70)

  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C1A70)

#define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x00001A74)

  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x09001A74)

  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x11091A74)

  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A1A74)

#define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x00001A78)

  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x09001A78)

  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x11091A78)

  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A1A78)

#define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x00001A7C)

  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x09001A7C)

  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x11091A7C)

  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A1A7C)

#define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_REG                        (0x00001A80)

  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06001A80)

  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06061A80)

  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C1A80)

  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06121A80)

  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07181A80)

  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F1A80)

#define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00001A84)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06001A84)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06061A84)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C1A84)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06121A84)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06181A84)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E1A84)

#define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00001A88)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06001A88)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06061A88)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C1A88)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06121A88)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06181A88)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E1A88)

#define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_REG                       (0x00001A8C)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x06001A8C)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x06061A8C)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C1A8C)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x06121A8C)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x06181A8C)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E1A8C)

#define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00001A90)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06001A90)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06061A90)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C1A90)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06121A90)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06181A90)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E1A90)

#define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00001A94)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06001A94)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06061A94)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C1A94)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06121A94)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06181A94)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E1A94)

#define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00001A98)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06001A98)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06061A98)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C1A98)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06121A98)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02181A98)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A1A98)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D1A98)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E1A98)

#define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_REG                       (0x00001A9C)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x06001A9C)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x06061A9C)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C1A9C)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x06121A9C)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x06181A9C)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E1A9C)

#define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_REG                       (0x00001AA0)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x06001AA0)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x06061AA0)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C1AA0)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x06121AA0)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x06181AA0)

  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA8CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E1AA0)

#define DDRDATA8CH1_CR_DCCDATADCCPILUT0_REG                            (0x00001AA4)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x06001AA4)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x06061AA4)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C1AA4)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x06121AA4)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x06181AA4)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E1AA4)

#define DDRDATA8CH1_CR_DCCDATADCCPILUT1_REG                            (0x00001AA8)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x06001AA8)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x06061AA8)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C1AA8)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x06121AA8)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x06181AA8)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E1AA8)

#define DDRDATA8CH1_CR_DCCDATADCCPILUT2_REG                            (0x00001AAC)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x06001AAC)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x06061AAC)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C1AAC)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x06121AAC)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x06181AAC)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E1AAC)

#define DDRDATA8CH1_CR_DCCDATADCCPILUT3_REG                            (0x00001AB0)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x06001AB0)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x06061AB0)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C1AB0)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x06121AB0)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x06181AB0)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E1AB0)

#define DDRDATA8CH1_CR_DCCDATADCCPILUT4_REG                            (0x00001AB4)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x06001AB4)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x06061AB4)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C1AB4)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x06121AB4)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x06181AB4)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E1AB4)

#define DDRDATA8CH1_CR_DCCDATADCCPILUT5_REG                            (0x00001AB8)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x06001AB8)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x06061AB8)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C1AB8)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x06121AB8)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x06181AB8)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E1AB8)

#define DDRDATA8CH1_CR_DCCDATADCCPILUT6_REG                            (0x00001ABC)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x06001ABC)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x06061ABC)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C1ABC)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x06121ABC)

  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA8CH1_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x08181ABC)

#define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_REG                        (0x00001AC0)

  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x06001AC0)

  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x06061AC0)

  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C1AC0)

  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x06121AC0)

  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x06181AC0)

  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E1AC0)

#define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_REG                        (0x00001AC4)

  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x06001AC4)

  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x06061AC4)

  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C1AC4)

  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x06121AC4)

  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x06181AC4)

  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E1AC4)

#define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x00001AC8)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x06001AC8)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x06061AC8)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C1AC8)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x06121AC8)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x02181AC8)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A1AC8)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C1AC8)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E1AC8)

#define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x00001ACC)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x06001ACC)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x06061ACC)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C1ACC)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x06121ACC)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x08181ACC)

#define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x00001AD0)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x06001AD0)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x06061AD0)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C1AD0)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x06121AD0)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x06181AD0)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E1AD0)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F1AD0)

#define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x00001AD4)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x06001AD4)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x06061AD4)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C1AD4)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x06121AD4)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x06181AD4)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E1AD4)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F1AD4)

#define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x00001AD8)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x06001AD8)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x06061AD8)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C1AD8)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x06121AD8)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x06181AD8)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E1AD8)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F1AD8)

#define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x00001ADC)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x06001ADC)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x06061ADC)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C1ADC)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x06121ADC)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x06181ADC)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E1ADC)

  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA8CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F1ADC)

#define DDRCMDBCH0_CR_DDRCRCMDCOMP_REG                                 (0x00001B00)

  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_Scomp_OFF                         ( 0)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_Scomp_WID                         ( 6)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_Scomp_MSK                         (0x0000003F)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_Scomp_MIN                         (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_Scomp_MAX                         (63) // 0x0000003F
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_Scomp_DEF                         (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_Scomp_HSH                         (0x06001B00)

  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_RcompDrvUp_OFF                    ( 6)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_RcompDrvUp_WID                    ( 6)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_RcompDrvUp_MSK                    (0x00000FC0)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_RcompDrvUp_MIN                    (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_RcompDrvUp_MAX                    (63) // 0x0000003F
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_RcompDrvUp_DEF                    (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_RcompDrvUp_HSH                    (0x06061B00)

  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_RcompDrvDown_OFF                  (12)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_RcompDrvDown_WID                  ( 6)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_RcompDrvDown_MSK                  (0x0003F000)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_RcompDrvDown_MIN                  (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_RcompDrvDown_MAX                  (63) // 0x0000003F
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_RcompDrvDown_DEF                  (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_RcompDrvDown_HSH                  (0x060C1B00)

  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_Spare_OFF                         (18)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_Spare_WID                         (14)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_Spare_MSK                         (0xFFFC0000)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_Spare_MIN                         (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_Spare_MAX                         (16383) // 0x00003FFF
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_Spare_DEF                         (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMP_Spare_HSH                         (0x0E121B00)

#define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_REG                           (0x00001B04)

  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF             ( 0)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID             ( 5)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK             (0x0000001F)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MIN             (-16)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX             (15) // 0x0000000F
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF             (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_HSH             (0x85001B04)

  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF        ( 5)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID        ( 4)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK        (0x000001E0)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MIN        (-8)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX        (7) // 0x00000007
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF        (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_HSH        (0x84051B04)

  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF      ( 9)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID      ( 4)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK      (0x00001E00)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MIN      (-8)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX      (7) // 0x00000007
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF      (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_HSH      (0x84091B04)

  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_Spare_OFF                   (13)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_Spare_WID                   (19)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_Spare_MSK                   (0xFFFFE000)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_Spare_MIN                   (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_Spare_MAX                   (524287) // 0x0007FFFF
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_Spare_DEF                   (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCOMPOFFSET_Spare_HSH                   (0x130D1B04)

#define DDRCMDBCH0_CR_DDRCRCMDPICODING_REG                             (0x00001B08)

  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi0Code_OFF                ( 0)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi0Code_WID                ( 7)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi0Code_MSK                (0x0000007F)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi0Code_MIN                (0)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi0Code_MAX                (127) // 0x0000007F
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi0Code_DEF                (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi0Code_HSH                (0x07001B08)

  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi1Code_OFF                ( 7)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi1Code_WID                ( 7)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi1Code_MSK                (0x00003F80)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi1Code_MIN                (0)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi1Code_MAX                (127) // 0x0000007F
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi1Code_DEF                (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi1Code_HSH                (0x07071B08)

  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_spare0_OFF                    (14)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_spare0_WID                    ( 2)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_spare0_MSK                    (0x0000C000)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_spare0_MIN                    (0)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_spare0_MAX                    (3) // 0x00000003
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_spare0_DEF                    (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_spare0_HSH                    (0x020E1B08)

  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi2Code_OFF                (16)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi2Code_WID                ( 7)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi2Code_MSK                (0x007F0000)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi2Code_MIN                (0)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi2Code_MAX                (127) // 0x0000007F
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi2Code_DEF                (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_CmdPi2Code_HSH                (0x07101B08)

  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_spare1_OFF                    (23)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_spare1_WID                    ( 9)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_spare1_MSK                    (0xFF800000)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_spare1_MIN                    (0)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_spare1_MAX                    (511) // 0x000001FF
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_spare1_DEF                    (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDPICODING_spare1_HSH                    (0x09171B08)

#define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_REG                             (0x00001B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_RefPi_OFF                     ( 0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_RefPi_WID                     ( 4)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_RefPi_MSK                     (0x0000000F)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_RefPi_MIN                     (-8)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_RefPi_MAX                     (7) // 0x00000007
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_RefPi_DEF                     (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_RefPi_HSH                     (0x84001B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DllMask_OFF                   ( 4)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DllMask_WID                   ( 2)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DllMask_MSK                   (0x00000030)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DllMask_MIN                   (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DllMask_MAX                   (3) // 0x00000003
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DllMask_DEF                   (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DllMask_HSH                   (0x02041B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_ClkGateDisable_OFF            ( 6)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_ClkGateDisable_WID            ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_ClkGateDisable_MSK            (0x00000040)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_ClkGateDisable_MIN            (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_ClkGateDisable_DEF            (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_ClkGateDisable_HSH            (0x01061B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_TxOn_OFF                      ( 7)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_TxOn_WID                      ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_TxOn_MSK                      (0x00000080)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_TxOn_MIN                      (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_TxOn_MAX                      (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_TxOn_DEF                      (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_TxOn_HSH                      (0x01071B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IntClkOn_OFF                  ( 8)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IntClkOn_WID                  ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IntClkOn_MSK                  (0x00000100)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IntClkOn_MIN                  (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IntClkOn_MAX                  (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IntClkOn_DEF                  (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IntClkOn_HSH                  (0x01081B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_RepClkOn_OFF                  ( 9)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_RepClkOn_WID                  ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_RepClkOn_MSK                  (0x00000200)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_RepClkOn_MIN                  (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_RepClkOn_MAX                  (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_RepClkOn_DEF                  (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_RepClkOn_HSH                  (0x01091B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IolbOrMisr_OFF                (10)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IolbOrMisr_WID                ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IolbOrMisr_MSK                (0x00000400)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IolbOrMisr_MIN                (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IolbOrMisr_MAX                (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IolbOrMisr_DEF                (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IolbOrMisr_HSH                (0x010A1B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IolbHold_OFF                  (11)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IolbHold_WID                  ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IolbHold_MSK                  (0x00000800)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IolbHold_MIN                  (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IolbHold_MAX                  (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IolbHold_DEF                  (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_IolbHold_HSH                  (0x010B1B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_OdtMode_OFF                   (12)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_OdtMode_WID                   ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_OdtMode_MSK                   (0x00001000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_OdtMode_MIN                   (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_OdtMode_MAX                   (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_OdtMode_DEF                   (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_OdtMode_HSH                   (0x010C1B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF                   (13)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_WID                   ( 2)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK                   (0x00006000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MIN                   (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX                   (3) // 0x00000003
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF                   (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CmdTxEq_HSH                   (0x020D1B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF            (15)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID            ( 2)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK            (0x00018000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MIN            (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX            (3) // 0x00000003
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF            (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_HSH            (0x020F1B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_OFF        (17)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_WID        ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_MSK        (0x00020000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_MIN        (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_MAX        (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_DEF        (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_HSH        (0x01111B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_OFF    (18)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_WID    ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_MSK    (0x00040000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_MIN    (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_MAX    (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_DEF    (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_HSH    (0x01121B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_OFF               (19)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_WID               ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_MSK               (0x00080000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_MIN               (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_MAX               (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_DEF               (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_HSH               (0x01131B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_OFF           (20)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_WID           ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_MSK           (0x00100000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_MIN           (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_MAX           (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_DEF           (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_HSH           (0x01141B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_Spares_OFF                    (21)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_Spares_WID                    ( 6)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_Spares_MSK                    (0x07E00000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_Spares_MIN                    (-32)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_Spares_MAX                    (31) // 0x0000001F
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_Spares_DEF                    (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_Spares_HSH                    (0x86151B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_VccddqHi_OFF                  (27)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_VccddqHi_WID                  ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_VccddqHi_MSK                  (0x08000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_VccddqHi_MIN                  (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_VccddqHi_MAX                  (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_VccddqHi_DEF                  (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_VccddqHi_HSH                  (0x011B1B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF               (28)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_WID               ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK               (0x10000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MIN               (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX               (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF               (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_DllWeakLock_HSH               (0x011C1B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CMD_Rate_OFF                  (29)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CMD_Rate_WID                  ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CMD_Rate_MSK                  (0x20000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CMD_Rate_MIN                  (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CMD_Rate_MAX                  (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CMD_Rate_DEF                  (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_CMD_Rate_HSH                  (0x011D1B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_OFF       (30)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_WID       ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_MSK       (0x40000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_MIN       (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_MAX       (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_DEF       (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_HSH       (0x011E1B0C)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_OFF         (31)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_WID         ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_MSK         (0x80000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_MIN         (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_MAX         (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_DEF         (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_HSH         (0x011F1B0C)

#define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_REG                            (0x00001B10)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_RxVref_OFF                   ( 0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_RxVref_WID                   ( 8)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_RxVref_MSK                   (0x000000FF)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_RxVref_MIN                   (-128)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_RxVref_MAX                   (127) // 0x0000007F
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_RxVref_DEF                   (0x00000060)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_RxVref_HSH                   (0x88001B10)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_OFF              ( 8)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_WID              ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_MSK              (0x00000100)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_MIN              (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_MAX              (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_DEF              (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_HSH              (0x01081B10)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_Gear1_OFF                    ( 9)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_Gear1_WID                    ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_Gear1_MSK                    (0x00000200)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_Gear1_MIN                    (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_Gear1_MAX                    (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_Gear1_DEF                    (0x00000001)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_Gear1_HSH                    (0x01091B10)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_OFF       (10)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_WID       ( 2)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_MSK       (0x00000C00)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_MIN       (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_MAX       (3) // 0x00000003
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_DEF       (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_HSH       (0x020A1B10)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_OFF           (12)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_WID           ( 4)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_MSK           (0x0000F000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_MIN           (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_MAX           (15) // 0x0000000F
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_DEF           (0x0000000F)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_HSH           (0x040C1B10)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_en_OFF                (16)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_en_WID                ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_en_MSK                (0x00010000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_en_MIN                (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_en_MAX                (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_en_DEF                (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_en_HSH                (0x01101B10)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_OFF            (17)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_WID            ( 1)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_MSK            (0x00020000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_MIN            (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_MAX            (1) // 0x00000001
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_DEF            (0x00000001)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_HSH            (0x01111B10)

  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_Spare_OFF                    (18)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_Spare_WID                    (14)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_Spare_MSK                    (0xFFFC0000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_Spare_MIN                    (0)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_Spare_MAX                    (16383) // 0x00003FFF
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_Spare_DEF                    (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDCONTROLS1_Spare_HSH                    (0x0E121B10)

#define DDRCMDBCH0_CR_DDRCRLOOPBACKFEEDBACK_REG                        (0x00001B14)

  #define DDRCMDBCH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_OFF    ( 0)
  #define DDRCMDBCH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_WID    (10)
  #define DDRCMDBCH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MSK    (0x000003FF)
  #define DDRCMDBCH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MIN    (0)
  #define DDRCMDBCH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MAX    (1023) // 0x000003FF
  #define DDRCMDBCH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_DEF    (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_HSH    (0x0A001B14)

  #define DDRCMDBCH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_OFF                (10)
  #define DDRCMDBCH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_WID                (22)
  #define DDRCMDBCH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_MSK                (0xFFFFFC00)
  #define DDRCMDBCH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_MIN                (0)
  #define DDRCMDBCH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_MAX                (4194303) // 0x003FFFFF
  #define DDRCMDBCH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_DEF                (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_HSH                (0x160A1B14)

#define DDRCMDBCH0_CR_DDRCRCMDTCOCONTROL0_REG                          (0x00001B18)

  #define DDRCMDBCH0_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_OFF             ( 0)
  #define DDRCMDBCH0_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_WID             ( 6)
  #define DDRCMDBCH0_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_MSK             (0x0000003F)
  #define DDRCMDBCH0_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_MIN             (0)
  #define DDRCMDBCH0_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_MAX             (63) // 0x0000003F
  #define DDRCMDBCH0_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_DEF             (0x00000020)
  #define DDRCMDBCH0_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_HSH             (0x06001B18)

  #define DDRCMDBCH0_CR_DDRCRCMDTCOCONTROL0_Spare_OFF                  ( 6)
  #define DDRCMDBCH0_CR_DDRCRCMDTCOCONTROL0_Spare_WID                  (26)
  #define DDRCMDBCH0_CR_DDRCRCMDTCOCONTROL0_Spare_MSK                  (0xFFFFFFC0)
  #define DDRCMDBCH0_CR_DDRCRCMDTCOCONTROL0_Spare_MIN                  (0)
  #define DDRCMDBCH0_CR_DDRCRCMDTCOCONTROL0_Spare_MAX                  (67108863) // 0x03FFFFFF
  #define DDRCMDBCH0_CR_DDRCRCMDTCOCONTROL0_Spare_DEF                  (0x00000000)
  #define DDRCMDBCH0_CR_DDRCRCMDTCOCONTROL0_Spare_HSH                  (0x1A061B18)

#define DDRCMDBCH1_CR_DDRCRCMDCOMP_REG                                 (0x00001B80)

  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_Scomp_OFF                         ( 0)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_Scomp_WID                         ( 6)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_Scomp_MSK                         (0x0000003F)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_Scomp_MIN                         (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_Scomp_MAX                         (63) // 0x0000003F
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_Scomp_DEF                         (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_Scomp_HSH                         (0x06001B80)

  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_RcompDrvUp_OFF                    ( 6)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_RcompDrvUp_WID                    ( 6)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_RcompDrvUp_MSK                    (0x00000FC0)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_RcompDrvUp_MIN                    (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_RcompDrvUp_MAX                    (63) // 0x0000003F
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_RcompDrvUp_DEF                    (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_RcompDrvUp_HSH                    (0x06061B80)

  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_RcompDrvDown_OFF                  (12)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_RcompDrvDown_WID                  ( 6)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_RcompDrvDown_MSK                  (0x0003F000)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_RcompDrvDown_MIN                  (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_RcompDrvDown_MAX                  (63) // 0x0000003F
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_RcompDrvDown_DEF                  (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_RcompDrvDown_HSH                  (0x060C1B80)

  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_Spare_OFF                         (18)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_Spare_WID                         (14)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_Spare_MSK                         (0xFFFC0000)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_Spare_MIN                         (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_Spare_MAX                         (16383) // 0x00003FFF
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_Spare_DEF                         (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMP_Spare_HSH                         (0x0E121B80)

#define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_REG                           (0x00001B84)

  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF             ( 0)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID             ( 5)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK             (0x0000001F)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MIN             (-16)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX             (15) // 0x0000000F
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF             (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_HSH             (0x85001B84)

  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF        ( 5)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID        ( 4)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK        (0x000001E0)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MIN        (-8)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX        (7) // 0x00000007
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF        (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_HSH        (0x84051B84)

  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF      ( 9)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID      ( 4)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK      (0x00001E00)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MIN      (-8)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX      (7) // 0x00000007
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF      (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_HSH      (0x84091B84)

  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_Spare_OFF                   (13)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_Spare_WID                   (19)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_Spare_MSK                   (0xFFFFE000)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_Spare_MIN                   (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_Spare_MAX                   (524287) // 0x0007FFFF
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_Spare_DEF                   (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCOMPOFFSET_Spare_HSH                   (0x130D1B84)

#define DDRCMDBCH1_CR_DDRCRCMDPICODING_REG                             (0x00001B88)

  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi0Code_OFF                ( 0)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi0Code_WID                ( 7)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi0Code_MSK                (0x0000007F)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi0Code_MIN                (0)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi0Code_MAX                (127) // 0x0000007F
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi0Code_DEF                (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi0Code_HSH                (0x07001B88)

  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi1Code_OFF                ( 7)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi1Code_WID                ( 7)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi1Code_MSK                (0x00003F80)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi1Code_MIN                (0)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi1Code_MAX                (127) // 0x0000007F
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi1Code_DEF                (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi1Code_HSH                (0x07071B88)

  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_spare0_OFF                    (14)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_spare0_WID                    ( 2)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_spare0_MSK                    (0x0000C000)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_spare0_MIN                    (0)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_spare0_MAX                    (3) // 0x00000003
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_spare0_DEF                    (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_spare0_HSH                    (0x020E1B88)

  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi2Code_OFF                (16)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi2Code_WID                ( 7)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi2Code_MSK                (0x007F0000)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi2Code_MIN                (0)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi2Code_MAX                (127) // 0x0000007F
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi2Code_DEF                (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_CmdPi2Code_HSH                (0x07101B88)

  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_spare1_OFF                    (23)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_spare1_WID                    ( 9)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_spare1_MSK                    (0xFF800000)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_spare1_MIN                    (0)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_spare1_MAX                    (511) // 0x000001FF
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_spare1_DEF                    (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDPICODING_spare1_HSH                    (0x09171B88)

#define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_REG                             (0x00001B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_RefPi_OFF                     ( 0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_RefPi_WID                     ( 4)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_RefPi_MSK                     (0x0000000F)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_RefPi_MIN                     (-8)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_RefPi_MAX                     (7) // 0x00000007
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_RefPi_DEF                     (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_RefPi_HSH                     (0x84001B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DllMask_OFF                   ( 4)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DllMask_WID                   ( 2)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DllMask_MSK                   (0x00000030)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DllMask_MIN                   (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DllMask_MAX                   (3) // 0x00000003
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DllMask_DEF                   (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DllMask_HSH                   (0x02041B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_ClkGateDisable_OFF            ( 6)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_ClkGateDisable_WID            ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_ClkGateDisable_MSK            (0x00000040)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_ClkGateDisable_MIN            (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_ClkGateDisable_DEF            (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_ClkGateDisable_HSH            (0x01061B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_TxOn_OFF                      ( 7)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_TxOn_WID                      ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_TxOn_MSK                      (0x00000080)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_TxOn_MIN                      (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_TxOn_MAX                      (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_TxOn_DEF                      (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_TxOn_HSH                      (0x01071B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IntClkOn_OFF                  ( 8)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IntClkOn_WID                  ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IntClkOn_MSK                  (0x00000100)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IntClkOn_MIN                  (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IntClkOn_MAX                  (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IntClkOn_DEF                  (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IntClkOn_HSH                  (0x01081B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_RepClkOn_OFF                  ( 9)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_RepClkOn_WID                  ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_RepClkOn_MSK                  (0x00000200)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_RepClkOn_MIN                  (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_RepClkOn_MAX                  (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_RepClkOn_DEF                  (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_RepClkOn_HSH                  (0x01091B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IolbOrMisr_OFF                (10)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IolbOrMisr_WID                ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IolbOrMisr_MSK                (0x00000400)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IolbOrMisr_MIN                (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IolbOrMisr_MAX                (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IolbOrMisr_DEF                (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IolbOrMisr_HSH                (0x010A1B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IolbHold_OFF                  (11)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IolbHold_WID                  ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IolbHold_MSK                  (0x00000800)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IolbHold_MIN                  (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IolbHold_MAX                  (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IolbHold_DEF                  (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_IolbHold_HSH                  (0x010B1B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_OdtMode_OFF                   (12)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_OdtMode_WID                   ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_OdtMode_MSK                   (0x00001000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_OdtMode_MIN                   (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_OdtMode_MAX                   (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_OdtMode_DEF                   (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_OdtMode_HSH                   (0x010C1B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF                   (13)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_WID                   ( 2)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK                   (0x00006000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MIN                   (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX                   (3) // 0x00000003
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF                   (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CmdTxEq_HSH                   (0x020D1B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF            (15)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID            ( 2)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK            (0x00018000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MIN            (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX            (3) // 0x00000003
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF            (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_HSH            (0x020F1B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_OFF        (17)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_WID        ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_MSK        (0x00020000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_MIN        (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_MAX        (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_DEF        (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_HSH        (0x01111B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_OFF    (18)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_WID    ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_MSK    (0x00040000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_MIN    (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_MAX    (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_DEF    (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_HSH    (0x01121B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_OFF               (19)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_WID               ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_MSK               (0x00080000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_MIN               (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_MAX               (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_DEF               (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_HSH               (0x01131B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_OFF           (20)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_WID           ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_MSK           (0x00100000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_MIN           (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_MAX           (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_DEF           (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_HSH           (0x01141B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_Spares_OFF                    (21)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_Spares_WID                    ( 6)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_Spares_MSK                    (0x07E00000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_Spares_MIN                    (-32)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_Spares_MAX                    (31) // 0x0000001F
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_Spares_DEF                    (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_Spares_HSH                    (0x86151B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_VccddqHi_OFF                  (27)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_VccddqHi_WID                  ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_VccddqHi_MSK                  (0x08000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_VccddqHi_MIN                  (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_VccddqHi_MAX                  (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_VccddqHi_DEF                  (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_VccddqHi_HSH                  (0x011B1B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF               (28)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_WID               ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK               (0x10000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MIN               (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX               (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF               (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_DllWeakLock_HSH               (0x011C1B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CMD_Rate_OFF                  (29)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CMD_Rate_WID                  ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CMD_Rate_MSK                  (0x20000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CMD_Rate_MIN                  (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CMD_Rate_MAX                  (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CMD_Rate_DEF                  (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_CMD_Rate_HSH                  (0x011D1B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_OFF       (30)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_WID       ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_MSK       (0x40000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_MIN       (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_MAX       (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_DEF       (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_HSH       (0x011E1B8C)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_OFF         (31)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_WID         ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_MSK         (0x80000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_MIN         (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_MAX         (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_DEF         (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_HSH         (0x011F1B8C)

#define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_REG                            (0x00001B90)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_RxVref_OFF                   ( 0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_RxVref_WID                   ( 8)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_RxVref_MSK                   (0x000000FF)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_RxVref_MIN                   (-128)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_RxVref_MAX                   (127) // 0x0000007F
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_RxVref_DEF                   (0x00000060)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_RxVref_HSH                   (0x88001B90)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_OFF              ( 8)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_WID              ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_MSK              (0x00000100)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_MIN              (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_MAX              (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_DEF              (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_HSH              (0x01081B90)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_Gear1_OFF                    ( 9)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_Gear1_WID                    ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_Gear1_MSK                    (0x00000200)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_Gear1_MIN                    (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_Gear1_MAX                    (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_Gear1_DEF                    (0x00000001)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_Gear1_HSH                    (0x01091B90)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_OFF       (10)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_WID       ( 2)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_MSK       (0x00000C00)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_MIN       (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_MAX       (3) // 0x00000003
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_DEF       (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_HSH       (0x020A1B90)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_OFF           (12)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_WID           ( 4)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_MSK           (0x0000F000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_MIN           (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_MAX           (15) // 0x0000000F
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_DEF           (0x0000000F)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_HSH           (0x040C1B90)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_en_OFF                (16)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_en_WID                ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_en_MSK                (0x00010000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_en_MIN                (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_en_MAX                (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_en_DEF                (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_en_HSH                (0x01101B90)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_OFF            (17)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_WID            ( 1)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_MSK            (0x00020000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_MIN            (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_MAX            (1) // 0x00000001
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_DEF            (0x00000001)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_HSH            (0x01111B90)

  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_Spare_OFF                    (18)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_Spare_WID                    (14)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_Spare_MSK                    (0xFFFC0000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_Spare_MIN                    (0)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_Spare_MAX                    (16383) // 0x00003FFF
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_Spare_DEF                    (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDCONTROLS1_Spare_HSH                    (0x0E121B90)

#define DDRCMDBCH1_CR_DDRCRLOOPBACKFEEDBACK_REG                        (0x00001B94)

  #define DDRCMDBCH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_OFF    ( 0)
  #define DDRCMDBCH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_WID    (10)
  #define DDRCMDBCH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MSK    (0x000003FF)
  #define DDRCMDBCH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MIN    (0)
  #define DDRCMDBCH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MAX    (1023) // 0x000003FF
  #define DDRCMDBCH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_DEF    (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_HSH    (0x0A001B94)

  #define DDRCMDBCH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_OFF                (10)
  #define DDRCMDBCH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_WID                (22)
  #define DDRCMDBCH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_MSK                (0xFFFFFC00)
  #define DDRCMDBCH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_MIN                (0)
  #define DDRCMDBCH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_MAX                (4194303) // 0x003FFFFF
  #define DDRCMDBCH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_DEF                (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_HSH                (0x160A1B94)

#define DDRCMDBCH1_CR_DDRCRCMDTCOCONTROL0_REG                          (0x00001B98)

  #define DDRCMDBCH1_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_OFF             ( 0)
  #define DDRCMDBCH1_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_WID             ( 6)
  #define DDRCMDBCH1_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_MSK             (0x0000003F)
  #define DDRCMDBCH1_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_MIN             (0)
  #define DDRCMDBCH1_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_MAX             (63) // 0x0000003F
  #define DDRCMDBCH1_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_DEF             (0x00000020)
  #define DDRCMDBCH1_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_HSH             (0x06001B98)

  #define DDRCMDBCH1_CR_DDRCRCMDTCOCONTROL0_Spare_OFF                  ( 6)
  #define DDRCMDBCH1_CR_DDRCRCMDTCOCONTROL0_Spare_WID                  (26)
  #define DDRCMDBCH1_CR_DDRCRCMDTCOCONTROL0_Spare_MSK                  (0xFFFFFFC0)
  #define DDRCMDBCH1_CR_DDRCRCMDTCOCONTROL0_Spare_MIN                  (0)
  #define DDRCMDBCH1_CR_DDRCRCMDTCOCONTROL0_Spare_MAX                  (67108863) // 0x03FFFFFF
  #define DDRCMDBCH1_CR_DDRCRCMDTCOCONTROL0_Spare_DEF                  (0x00000000)
  #define DDRCMDBCH1_CR_DDRCRCMDTCOCONTROL0_Spare_HSH                  (0x1A061B98)

#define DDRCTLCLKCKE0_CR_DDRCRCLKTCOCONTROL0_REG                       (0x00001C00)

  #define DDRCTLCLKCKE0_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_OFF          ( 0)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_WID          ( 6)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_MSK          (0x0000003F)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_MIN          (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_MAX          (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_DEF          (0x00000020)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_HSH          (0x06001C00)

  #define DDRCTLCLKCKE0_CR_DDRCRCLKTCOCONTROL0_Spare_OFF               ( 6)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKTCOCONTROL0_Spare_WID               (26)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKTCOCONTROL0_Spare_MSK               (0xFFFFFFC0)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKTCOCONTROL0_Spare_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKTCOCONTROL0_Spare_MAX               (67108863) // 0x03FFFFFF
  #define DDRCTLCLKCKE0_CR_DDRCRCLKTCOCONTROL0_Spare_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKTCOCONTROL0_Spare_HSH               (0x1A061C00)

#define DDRCTLCLKCKE0_CR_DDRCRCTLTCOCONTROL0_REG                       (0x00001C04)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_OFF          ( 0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_WID          ( 6)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_MSK          (0x0000003F)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_MIN          (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_MAX          (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_DEF          (0x00000020)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_HSH          (0x06001C04)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLTCOCONTROL0_Spare_OFF               ( 6)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLTCOCONTROL0_Spare_WID               (26)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLTCOCONTROL0_Spare_MSK               (0xFFFFFFC0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLTCOCONTROL0_Spare_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLTCOCONTROL0_Spare_MAX               (67108863) // 0x03FFFFFF
  #define DDRCTLCLKCKE0_CR_DDRCRCTLTCOCONTROL0_Spare_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLTCOCONTROL0_Spare_HSH               (0x1A061C04)

#define DDRCTLCLKCKE0_CR_DDRCRLOOPBACKFEEDBACK_REG                     (0x00001C08)

  #define DDRCTLCLKCKE0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_OFF ( 0)
  #define DDRCTLCLKCKE0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_WID (10)
  #define DDRCTLCLKCKE0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MSK (0x000003FF)
  #define DDRCTLCLKCKE0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MIN (0)
  #define DDRCTLCLKCKE0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MAX (1023) // 0x000003FF
  #define DDRCTLCLKCKE0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_DEF (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_HSH (0x0A001C08)

  #define DDRCTLCLKCKE0_CR_DDRCRLOOPBACKFEEDBACK_Spare_OFF             (10)
  #define DDRCTLCLKCKE0_CR_DDRCRLOOPBACKFEEDBACK_Spare_WID             (22)
  #define DDRCTLCLKCKE0_CR_DDRCRLOOPBACKFEEDBACK_Spare_MSK             (0xFFFFFC00)
  #define DDRCTLCLKCKE0_CR_DDRCRLOOPBACKFEEDBACK_Spare_MIN             (0)
  #define DDRCTLCLKCKE0_CR_DDRCRLOOPBACKFEEDBACK_Spare_MAX             (4194303) // 0x003FFFFF
  #define DDRCTLCLKCKE0_CR_DDRCRLOOPBACKFEEDBACK_Spare_DEF             (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRLOOPBACKFEEDBACK_Spare_HSH             (0x160A1C08)

#define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_REG                              (0x00001C10)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_Scomp_OFF                      ( 0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_Scomp_WID                      ( 6)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_Scomp_MSK                      (0x0000003F)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_Scomp_MIN                      (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_Scomp_MAX                      (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_Scomp_DEF                      (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_Scomp_HSH                      (0x06001C10)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_RcompDrvUp_OFF                 ( 6)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_RcompDrvUp_WID                 ( 6)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_RcompDrvUp_MSK                 (0x00000FC0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_RcompDrvUp_MIN                 (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_RcompDrvUp_MAX                 (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_RcompDrvUp_DEF                 (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_RcompDrvUp_HSH                 (0x06061C10)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_RcompDrvDown_OFF               (12)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_RcompDrvDown_WID               ( 6)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_RcompDrvDown_MSK               (0x0003F000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_RcompDrvDown_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_RcompDrvDown_MAX               (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_RcompDrvDown_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_RcompDrvDown_HSH               (0x060C1C10)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_Spare_OFF                      (18)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_Spare_WID                      (14)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_Spare_MSK                      (0xFFFC0000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_Spare_MIN                      (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_Spare_MAX                      (16383) // 0x00003FFF
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_Spare_DEF                      (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMP_Spare_HSH                      (0x0E121C10)

#define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_REG                        (0x00001C14)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF          ( 0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID          ( 5)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK          (0x0000001F)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MIN          (-16)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX          (15) // 0x0000000F
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF          (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_HSH          (0x85001C14)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF     ( 5)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID     ( 4)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK     (0x000001E0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MIN     (-8)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX     (7) // 0x00000007
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF     (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_HSH     (0x84051C14)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF   ( 9)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID   ( 4)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK   (0x00001E00)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MIN   (-8)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX   (7) // 0x00000007
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF   (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_HSH   (0x84091C14)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_Spare_OFF                (13)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_Spare_WID                (19)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_Spare_MSK                (0xFFFFE000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_Spare_MIN                (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_Spare_MAX                (524287) // 0x0007FFFF
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_Spare_DEF                (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCOMPOFFSET_Spare_HSH                (0x130D1C14)

#define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_REG                          (0x00001C18)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode0_OFF             ( 0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode0_WID             ( 7)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode0_MSK             (0x0000007F)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode0_MIN             (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode0_MAX             (127) // 0x0000007F
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode0_DEF             (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode0_HSH             (0x07001C18)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode1_OFF             ( 7)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode1_WID             ( 7)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode1_MSK             (0x00003F80)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode1_MIN             (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode1_MAX             (127) // 0x0000007F
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode1_DEF             (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode1_HSH             (0x07071C18)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode2_OFF             (14)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode2_WID             ( 7)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode2_MSK             (0x001FC000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode2_MIN             (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode2_MAX             (127) // 0x0000007F
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode2_DEF             (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode2_HSH             (0x070E1C18)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode3_OFF             (21)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode3_WID             ( 7)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode3_MSK             (0x0FE00000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode3_MIN             (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode3_MAX             (127) // 0x0000007F
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode3_DEF             (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlPiCode3_HSH             (0x07151C18)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF         (28)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlXoverEnable_WID         ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK         (0x10000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlXoverEnable_MIN         (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX         (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF         (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_CtlXoverEnable_HSH         (0x011C1C18)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_Spare_OFF                  (29)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_Spare_WID                  ( 3)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_Spare_MSK                  (0xE0000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_Spare_MIN                  (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_Spare_MAX                  (7) // 0x00000007
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_Spare_DEF                  (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLPICODING_Spare_HSH                  (0x031D1C18)

#define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_REG                          (0x00001C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RefPi_OFF                  ( 0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RefPi_WID                  ( 4)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RefPi_MSK                  (0x0000000F)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RefPi_MIN                  (-8)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RefPi_MAX                  (7) // 0x00000007
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RefPi_DEF                  (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RefPi_HSH                  (0x84001C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_DllMask_OFF                ( 4)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_DllMask_WID                ( 2)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_DllMask_MSK                (0x00000030)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_DllMask_MIN                (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_DllMask_MAX                (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_DllMask_DEF                (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_DllMask_HSH                (0x02041C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_ClkGateDisable_OFF         ( 6)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_ClkGateDisable_WID         ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_ClkGateDisable_MSK         (0x00000040)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_ClkGateDisable_MIN         (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_ClkGateDisable_MAX         (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_ClkGateDisable_DEF         (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_ClkGateDisable_HSH         (0x01061C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_TxOn_OFF                   ( 7)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_TxOn_WID                   ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_TxOn_MSK                   (0x00000080)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_TxOn_MIN                   (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_TxOn_MAX                   (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_TxOn_DEF                   (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_TxOn_HSH                   (0x01071C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IntClkOn_OFF               ( 8)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IntClkOn_WID               ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IntClkOn_MSK               (0x00000100)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IntClkOn_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IntClkOn_MAX               (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IntClkOn_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IntClkOn_HSH               (0x01081C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RepClkOn_OFF               ( 9)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RepClkOn_WID               ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RepClkOn_MSK               (0x00000200)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RepClkOn_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RepClkOn_MAX               (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RepClkOn_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RepClkOn_HSH               (0x01091C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IolbOrMisr_OFF             (10)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IolbOrMisr_WID             ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IolbOrMisr_MSK             (0x00000400)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IolbOrMisr_MIN             (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IolbOrMisr_MAX             (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IolbOrMisr_DEF             (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IolbOrMisr_HSH             (0x010A1C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IOLBHold_OFF               (11)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IOLBHold_WID               ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IOLBHold_MSK               (0x00000800)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IOLBHold_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IOLBHold_MAX               (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IOLBHold_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_IOLBHold_HSH               (0x010B1C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_OdtMode_OFF                (12)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_OdtMode_WID                ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_OdtMode_MSK                (0x00001000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_OdtMode_MIN                (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_OdtMode_MAX                (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_OdtMode_DEF                (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_OdtMode_HSH                (0x010C1C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF                (13)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CmdTxEq_WID                ( 2)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK                (0x00006000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CmdTxEq_MIN                (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX                (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF                (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CmdTxEq_HSH                (0x020D1C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF         (15)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID         ( 2)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK         (0x00018000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MIN         (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX         (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF         (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_HSH         (0x020F1C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF                (17)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CtlTxEq_WID                ( 2)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK                (0x00060000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CtlTxEq_MIN                (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX                (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF                (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CtlTxEq_HSH                (0x02111C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF               (19)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID               ( 2)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK               (0x00180000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX               (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CtlSRDrv_HSH               (0x02131C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RxVref_OFF                 (21)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RxVref_WID                 ( 6)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RxVref_MSK                 (0x07E00000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RxVref_MIN                 (-32)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RxVref_MAX                 (31) // 0x0000001F
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RxVref_DEF                 (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_RxVref_HSH                 (0x86151C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_VccddqHi_OFF               (27)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_VccddqHi_WID               ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_VccddqHi_MSK               (0x08000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_VccddqHi_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_VccddqHi_MAX               (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_VccddqHi_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_VccddqHi_HSH               (0x011B1C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF            (28)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_DllWeakLock_WID            ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK            (0x10000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_DllWeakLock_MIN            (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX            (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF            (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_DllWeakLock_HSH            (0x011C1C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CMD_Rate_OFF               (29)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CMD_Rate_WID               ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CMD_Rate_MSK               (0x20000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CMD_Rate_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CMD_Rate_MAX               (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CMD_Rate_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_CMD_Rate_HSH               (0x011D1C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF            (30)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID            ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK            (0x40000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MIN            (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX            (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF            (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_HSH            (0x011E1C1C)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_OFF        (31)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_WID        ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_MSK        (0x80000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_MIN        (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_MAX        (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_DEF        (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_HSH        (0x011F1C1C)

#define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_REG                         (0x00001C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_OFF             ( 0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_WID             ( 8)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_MSK             (0x000000FF)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_MIN             (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_MAX             (255) // 0x000000FF
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_DEF             (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_HSH             (0x08001C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_PiClkEn_OFF               ( 8)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_PiClkEn_WID               ( 4)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_PiClkEn_MSK               (0x00000F00)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_PiClkEn_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_PiClkEn_MAX               (15) // 0x0000000F
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_PiClkEn_DEF               (0x0000000F)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_PiClkEn_HSH               (0x04081C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_OFF    (12)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_WID    ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_MSK    (0x00001000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_MIN    (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_MAX    (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_DEF    (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_HSH    (0x010C1C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_OFF   (13)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_WID   ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_MSK   (0x00002000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_MIN   (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_MAX   (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_DEF   (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_HSH   (0x010D1C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_OFF  (14)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_WID  ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_MSK  (0x00004000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_MIN  (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_MAX  (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_DEF  (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_HSH  (0x010E1C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_OFF         (15)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_WID         ( 2)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_MSK         (0x00018000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_MIN         (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_MAX         (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_DEF         (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_HSH         (0x020F1C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_OFF      (17)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_WID      ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_MSK      (0x00020000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_MIN      (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_MAX      (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_DEF      (0x00000001)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_HSH      (0x01111C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_OFF      (18)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_WID      ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_MSK      (0x00040000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_MIN      (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_MAX      (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_DEF      (0x00000001)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_HSH      (0x01121C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_OFF        (19)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_WID        ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_MSK        (0x00080000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_MIN        (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_MAX        (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_DEF        (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_HSH        (0x01131C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_OFF        (20)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_WID        ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_MSK        (0x00100000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_MIN        (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_MAX        (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_DEF        (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_HSH        (0x01141C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_OFF        (21)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_WID        ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_MSK        (0x00200000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_MIN        (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_MAX        (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_DEF        (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_HSH        (0x01151C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_OFF        (22)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_WID        ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_MSK        (0x00400000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_MIN        (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_MAX        (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_DEF        (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_HSH        (0x01161C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_Gear1_OFF                 (23)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_Gear1_WID                 ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_Gear1_MSK                 (0x00800000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_Gear1_MIN                 (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_Gear1_MAX                 (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_Gear1_DEF                 (0x00000001)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_Gear1_HSH                 (0x01171C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_OFF     (24)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_WID     ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_MSK     (0x01000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_MIN     (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_MAX     (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_DEF     (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_HSH     (0x01181C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_OFF    (25)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_WID    ( 2)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_MSK    (0x06000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_MIN    (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_MAX    (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_DEF    (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_HSH    (0x02191C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_OFF      (27)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_WID      ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_MSK      (0x08000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_MIN      (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_MAX      (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_DEF      (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_HSH      (0x011B1C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_OFF (28)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_WID ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_MSK (0x10000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_MIN (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_MAX (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_DEF (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_HSH (0x011C1C20)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_Spare_OFF                 (29)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_Spare_WID                 ( 3)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_Spare_MSK                 (0xE0000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_Spare_MIN                 (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_Spare_MAX                 (7) // 0x00000007
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_Spare_DEF                 (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLRANKSUSED_Spare_HSH                 (0x031D1C20)

#define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_REG                         (0x00001C24)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_RxVref_OFF                ( 0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_RxVref_WID                ( 8)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_RxVref_MSK                (0x000000FF)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_RxVref_MIN                (-128)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_RxVref_MAX                (127) // 0x0000007F
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_RxVref_DEF                (0x00000060)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_RxVref_HSH                (0x88001C24)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_OFF        ( 8)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_WID        (18)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_MSK        (0x03FFFF00)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_MIN        (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_MAX        (262143) // 0x0003FFFF
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_DEF        (0x00010458)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_HSH        (0x12081C24)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_OFF           (26)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_WID           ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_MSK           (0x04000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_MIN           (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_MAX           (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_DEF           (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_HSH           (0x011A1C24)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CKELowsupEn_OFF           (27)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CKELowsupEn_WID           ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CKELowsupEn_MSK           (0x08000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CKELowsupEn_MIN           (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CKELowsupEn_MAX           (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CKELowsupEn_DEF           (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CKELowsupEn_HSH           (0x011B1C24)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_OFF           (28)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_WID           ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_MSK           (0x10000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_MIN           (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_MAX           (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_DEF           (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_HSH           (0x011C1C24)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_OFF           (29)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_WID           ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_MSK           (0x20000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_MIN           (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_MAX           (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_DEF           (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_HSH           (0x011D1C24)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_OFF     (30)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_WID     ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_MSK     (0x40000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_MIN     (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_MAX     (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_DEF     (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_HSH     (0x011E1C24)

  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_OFF    (31)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_WID    ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_MSK    (0x80000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_MIN    (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_MAX    (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_DEF    (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_HSH    (0x011F1C24)

#define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_REG                        (0x00001C2C)

  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_OFF          ( 0)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_WID          ( 4)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MSK          (0x0000000F)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MIN          (-8)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MAX          (7) // 0x00000007
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_DEF          (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_HSH          (0x84001C2C)

  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_OFF     ( 4)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_WID     ( 4)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MSK     (0x000000F0)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MIN     (-8)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MAX     (7) // 0x00000007
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_DEF     (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_HSH     (0x84041C2C)

  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_OFF   ( 8)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_WID   ( 4)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MSK   (0x00000F00)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MIN   (-8)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MAX   (7) // 0x00000007
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_DEF   (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_HSH   (0x84081C2C)

  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_OFF (12)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_WID ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_MSK (0x00001000)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_MIN (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_MAX (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_DEF (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_HSH (0x010C1C2C)

  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_Spare_OFF                (13)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_Spare_WID                (19)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_Spare_MSK                (0xFFFFE000)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_Spare_MIN                (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_Spare_MAX                (524287) // 0x0007FFFF
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_Spare_DEF                (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMPOFFSET_Spare_HSH                (0x130D1C2C)

#define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_REG                              (0x00001C30)

  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_Scomp_OFF                      ( 0)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_Scomp_WID                      ( 5)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_Scomp_MSK                      (0x0000001F)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_Scomp_MIN                      (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_Scomp_MAX                      (31) // 0x0000001F
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_Scomp_DEF                      (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_Scomp_HSH                      (0x05001C30)

  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_RcompDrvUp_OFF                 ( 5)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_RcompDrvUp_WID                 ( 6)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_RcompDrvUp_MSK                 (0x000007E0)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_RcompDrvUp_MIN                 (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_RcompDrvUp_MAX                 (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_RcompDrvUp_DEF                 (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_RcompDrvUp_HSH                 (0x06051C30)

  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_RcompDrvDown_OFF               (11)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_RcompDrvDown_WID               ( 6)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_RcompDrvDown_MSK               (0x0001F800)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_RcompDrvDown_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_RcompDrvDown_MAX               (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_RcompDrvDown_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_RcompDrvDown_HSH               (0x060B1C30)

  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_Spare_OFF                      (17)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_Spare_WID                      (15)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_Spare_MSK                      (0xFFFE0000)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_Spare_MIN                      (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_Spare_MAX                      (32767) // 0x00007FFF
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_Spare_DEF                      (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCLKCOMP_Spare_HSH                      (0x0F111C30)

#define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_REG                       (0x00001C34)

  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_ScompOffset_OFF         ( 0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_ScompOffset_WID         ( 5)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_ScompOffset_MSK         (0x0000001F)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_ScompOffset_MIN         (-16)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_ScompOffset_MAX         (15) // 0x0000000F
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_ScompOffset_DEF         (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_ScompOffset_HSH         (0x85001C34)

  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_RcompDrvUpOffset_OFF    ( 5)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_RcompDrvUpOffset_WID    ( 4)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_RcompDrvUpOffset_MSK    (0x000001E0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_RcompDrvUpOffset_MIN    (-8)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_RcompDrvUpOffset_MAX    (7) // 0x00000007
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_RcompDrvUpOffset_DEF    (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_RcompDrvUpOffset_HSH    (0x84051C34)

  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_RcompDrvDownOffset_OFF  ( 9)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_RcompDrvDownOffset_WID  ( 4)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_RcompDrvDownOffset_MSK  (0x00001E00)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_RcompDrvDownOffset_MIN  (-8)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_RcompDrvDownOffset_MAX  (7) // 0x00000007
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_RcompDrvDownOffset_DEF  (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_RcompDrvDownOffset_HSH  (0x84091C34)

  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_Spare_OFF               (13)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_Spare_WID               (19)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_Spare_MSK               (0xFFFFE000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_Spare_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_Spare_MAX               (524287) // 0x0007FFFF
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_Spare_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCCCOMPOFFSET1_Spare_HSH               (0x130D1C34)

#define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_REG                      (0x00001C38)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RefPi_OFF              ( 0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RefPi_WID              ( 4)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RefPi_MSK              (0x0000000F)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RefPi_MIN              (-8)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RefPi_MAX              (7) // 0x00000007
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RefPi_DEF              (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RefPi_HSH              (0x84001C38)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_ClkGateDisable_OFF     ( 4)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_ClkGateDisable_WID     ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_ClkGateDisable_MSK     (0x00000010)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_ClkGateDisable_MIN     (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_ClkGateDisable_MAX     (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_ClkGateDisable_DEF     (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_ClkGateDisable_HSH     (0x01041C38)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_TxOn_OFF               ( 5)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_TxOn_WID               ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_TxOn_MSK               (0x00000020)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_TxOn_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_TxOn_MAX               (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_TxOn_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_TxOn_HSH               (0x01051C38)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IntClkOn_OFF           ( 6)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IntClkOn_WID           ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IntClkOn_MSK           (0x00000040)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IntClkOn_MIN           (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IntClkOn_MAX           (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IntClkOn_DEF           (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IntClkOn_HSH           (0x01061C38)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RepClkOn_OFF           ( 7)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RepClkOn_WID           ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RepClkOn_MSK           (0x00000080)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RepClkOn_MIN           (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RepClkOn_MAX           (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RepClkOn_DEF           (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RepClkOn_HSH           (0x01071C38)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IolbOrMisr_OFF         ( 8)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IolbOrMisr_WID         ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IolbOrMisr_MSK         (0x00000100)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IolbOrMisr_MIN         (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IolbOrMisr_MAX         (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IolbOrMisr_DEF         (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IolbOrMisr_HSH         (0x01081C38)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IOLBHold_OFF           ( 9)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IOLBHold_WID           ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IOLBHold_MSK           (0x00000200)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IOLBHold_MIN           (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IOLBHold_MAX           (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IOLBHold_DEF           (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_IOLBHold_HSH           (0x01091C38)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_OdtMode_OFF            (10)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_OdtMode_WID            ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_OdtMode_MSK            (0x00000400)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_OdtMode_MIN            (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_OdtMode_MAX            (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_OdtMode_DEF            (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_OdtMode_HSH            (0x010A1C38)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CmdTxEq_OFF            (11)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CmdTxEq_WID            ( 2)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CmdTxEq_MSK            (0x00001800)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CmdTxEq_MIN            (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CmdTxEq_MAX            (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CmdTxEq_DEF            (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CmdTxEq_HSH            (0x020B1C38)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_EarlyWeakDrive_OFF     (13)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_EarlyWeakDrive_WID     ( 2)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_EarlyWeakDrive_MSK     (0x00006000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_EarlyWeakDrive_MIN     (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_EarlyWeakDrive_MAX     (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_EarlyWeakDrive_DEF     (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_EarlyWeakDrive_HSH     (0x020D1C38)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CtlTxEq_OFF            (15)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CtlTxEq_WID            ( 2)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CtlTxEq_MSK            (0x00018000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CtlTxEq_MIN            (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CtlTxEq_MAX            (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CtlTxEq_DEF            (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CtlTxEq_HSH            (0x020F1C38)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CtlSRDrv_OFF           (17)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CtlSRDrv_WID           ( 2)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CtlSRDrv_MSK           (0x00060000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CtlSRDrv_MIN           (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CtlSRDrv_MAX           (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CtlSRDrv_DEF           (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CtlSRDrv_HSH           (0x02111C38)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RxVref_OFF             (19)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RxVref_WID             ( 6)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RxVref_MSK             (0x01F80000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RxVref_MIN             (-32)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RxVref_MAX             (31) // 0x0000001F
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RxVref_DEF             (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_RxVref_HSH             (0x86131C38)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CKELowsupEn_OFF        (25)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CKELowsupEn_WID        ( 1)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CKELowsupEn_MSK        (0x02000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CKELowsupEn_MIN        (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CKELowsupEn_MAX        (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CKELowsupEn_DEF        (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_CKELowsupEn_HSH        (0x01191C38)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_spare_OFF              (26)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_spare_WID              ( 6)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_spare_MSK              (0xFC000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_spare_MIN              (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_spare_MAX              (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_spare_DEF              (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKECONTROLS_spare_HSH              (0x061A1C38)

#define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_REG                     (0x00001C3C)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_ctlcktxen_OFF         ( 0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_ctlcktxen_WID         ( 2)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_ctlcktxen_MSK         (0x00000003)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_ctlcktxen_MIN         (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_ctlcktxen_MAX         (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_ctlcktxen_DEF         (0x00000003)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_ctlcktxen_HSH         (0x02001C3C)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_PiClkEn_OFF           ( 2)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_PiClkEn_WID           ( 4)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_PiClkEn_MSK           (0x0000003C)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_PiClkEn_MIN           (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_PiClkEn_MAX           (15) // 0x0000000F
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_PiClkEn_DEF           (0x0000000F)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_PiClkEn_HSH           (0x04021C3C)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_DdrCkeCmdSlwDlyByp_OFF ( 6)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_DdrCkeCmdSlwDlyByp_WID ( 2)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_DdrCkeCmdSlwDlyByp_MSK (0x000000C0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_DdrCkeCmdSlwDlyByp_MIN (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_DdrCkeCmdSlwDlyByp_MAX (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_DdrCkeCmdSlwDlyByp_DEF (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_DdrCkeCmdSlwDlyByp_HSH (0x02061C3C)

  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_Spare_OFF             ( 8)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_Spare_WID             (24)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_Spare_MSK             (0xFFFFFF00)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_Spare_MIN             (0)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_Spare_MAX             (16777215) // 0x00FFFFFF
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_Spare_DEF             (0x00000000)
  #define DDRCTLCLKCKE0_CR_DDRCRCCC4CKERANKSUSED_Spare_HSH             (0x18081C3C)

#define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_REG                            (0x00001C40)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_CRVALID_OFF                  ( 0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_CRVALID_WID                  ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_CRVALID_MSK                  (0x00000001)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_CRVALID_MIN                  (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_CRVALID_MAX                  (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_CRVALID_DEF                  (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_CRVALID_HSH                  (0x01001C40)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_GVPointG2_OFF                ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_GVPointG2_WID                ( 2)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_GVPointG2_MSK                (0x00000006)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_GVPointG2_MIN                (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_GVPointG2_MAX                (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_GVPointG2_DEF                (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_GVPointG2_HSH                (0x02011C40)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ReplicaOffsetUse_OFF         ( 3)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ReplicaOffsetUse_WID         ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ReplicaOffsetUse_MSK         (0x00000008)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ReplicaOffsetUse_MIN         (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ReplicaOffsetUse_MAX         (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ReplicaOffsetUse_DEF         (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ReplicaOffsetUse_HSH         (0x01031C40)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_VTCompOffsetUse_OFF          ( 4)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_VTCompOffsetUse_WID          ( 2)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_VTCompOffsetUse_MSK          (0x00000030)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_VTCompOffsetUse_MIN          (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_VTCompOffsetUse_MAX          (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_VTCompOffsetUse_DEF          (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_VTCompOffsetUse_HSH          (0x02041C40)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ExtOffset_OFF                ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ExtOffset_WID                ( 7)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ExtOffset_MSK                (0x00001FC0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ExtOffset_MIN                (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ExtOffset_MAX                (127) // 0x0000007F
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ExtOffset_DEF                (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ExtOffset_HSH                (0x07061C40)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_BiasOffset_OFF               (13)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_BiasOffset_WID               (15)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_BiasOffset_MSK               (0x0FFFE000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_BiasOffset_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_BiasOffset_MAX               (32767) // 0x00007FFF
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_BiasOffset_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_BiasOffset_HSH               (0x0F0D1C40)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ActiveRanks_OFF              (28)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ActiveRanks_WID              ( 4)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ActiveRanks_MSK              (0xF0000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ActiveRanks_MIN              (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ActiveRanks_MAX              (15) // 0x0000000F
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ActiveRanks_DEF              (0x00000001)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL0_ActiveRanks_HSH              (0x041C1C40)

#define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_REG                            (0x00001C44)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DccCodeOvrd_OFF              ( 0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DccCodeOvrd_WID              ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DccCodeOvrd_MSK              (0x0000003F)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DccCodeOvrd_MIN              (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DccCodeOvrd_MAX              (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DccCodeOvrd_DEF              (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DccCodeOvrd_HSH              (0x06001C44)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_Rank0DccAipCb_OFF            ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_Rank0DccAipCb_WID            ( 2)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_Rank0DccAipCb_MSK            (0x000000C0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_Rank0DccAipCb_MIN            (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_Rank0DccAipCb_MAX            (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_Rank0DccAipCb_DEF            (0x00000001)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_Rank0DccAipCb_HSH            (0x02061C44)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DccPtrOvrd_OFF               ( 8)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DccPtrOvrd_WID               ( 4)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DccPtrOvrd_MSK               (0x00000F00)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DccPtrOvrd_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DccPtrOvrd_MAX               (15) // 0x0000000F
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DccPtrOvrd_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DccPtrOvrd_HSH               (0x04081C44)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_RnkPtrOvrd_OFF               (12)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_RnkPtrOvrd_WID               ( 2)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_RnkPtrOvrd_MSK               (0x00003000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_RnkPtrOvrd_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_RnkPtrOvrd_MAX               (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_RnkPtrOvrd_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_RnkPtrOvrd_HSH               (0x020C1C44)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdDigEnOvrd_OFF             (14)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdDigEnOvrd_WID             ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdDigEnOvrd_MSK             (0x00004000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdDigEnOvrd_MIN             (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdDigEnOvrd_MAX             (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdDigEnOvrd_DEF             (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdDigEnOvrd_HSH             (0x010E1C44)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_OFF             (15)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_WID             ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_MSK             (0x00008000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_MIN             (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_MAX             (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_DEF             (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_HSH             (0x010F1C44)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdWindow_OFF                (16)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdWindow_WID                (15)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdWindow_MSK                (0x7FFF0000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdWindow_MIN                (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdWindow_MAX                (32767) // 0x00007FFF
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdWindow_DEF                (0x00000800)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_DcdWindow_HSH                (0x0F101C44)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_Spare_OFF                    (31)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_Spare_WID                    ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_Spare_MSK                    (0x80000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_Spare_MIN                    (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_Spare_MAX                    (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_Spare_DEF                    (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL1_Spare_HSH                    (0x011F1C44)

#define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_REG                            (0x00001C48)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_StartBinCode_OFF             ( 0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_StartBinCode_WID             ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_StartBinCode_MSK             (0x0000003F)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_StartBinCode_MIN             (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_StartBinCode_MAX             (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_StartBinCode_DEF             (0x00000020)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_StartBinCode_HSH             (0x06001C48)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_CodePtrStartBit_OFF          ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_CodePtrStartBit_WID          ( 3)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_CodePtrStartBit_MSK          (0x000001C0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_CodePtrStartBit_MIN          (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_CodePtrStartBit_MAX          (7) // 0x00000007
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_CodePtrStartBit_DEF          (0x00000005)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_CodePtrStartBit_HSH          (0x03061C48)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DccTrshOld_OFF               ( 9)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DccTrshOld_WID               (13)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DccTrshOld_MSK               (0x003FFE00)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DccTrshOld_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DccTrshOld_MAX               (8191) // 0x00001FFF
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DccTrshOld_DEF               (0x00000008)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DccTrshOld_HSH               (0x0D091C48)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DcdCntsStartDiff_OFF         (22)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DcdCntsStartDiff_WID         ( 5)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DcdCntsStartDiff_MSK         (0x07C00000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DcdCntsStartDiff_MIN         (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DcdCntsStartDiff_MAX         (31) // 0x0000001F
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DcdCntsStartDiff_DEF         (0x00000003)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DcdCntsStartDiff_HSH         (0x05161C48)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_ClkGateDisable_OFF           (27)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_ClkGateDisable_WID           ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_ClkGateDisable_MSK           (0x08000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_ClkGateDisable_MIN           (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_ClkGateDisable_MAX           (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_ClkGateDisable_DEF           (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_ClkGateDisable_HSH           (0x011B1C48)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DccClkViewSelect0_OFF        (28)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DccClkViewSelect0_WID        ( 4)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DccClkViewSelect0_MSK        (0xF0000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DccClkViewSelect0_MIN        (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DccClkViewSelect0_MAX        (15) // 0x0000000F
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DccClkViewSelect0_DEF        (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL2_DccClkViewSelect0_HSH        (0x041C1C48)

#define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_REG                            (0x00001C4C)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank0_OFF           ( 0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank0_WID           (11)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank0_MSK           (0x000007FF)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank0_MIN           (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank0_MAX           (2047) // 0x000007FF
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank0_DEF           (0x00000007)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank0_HSH           (0x0B001C4C)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank1_OFF           (11)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank1_WID           ( 9)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank1_MSK           (0x000FF800)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank1_MIN           (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank1_MAX           (511) // 0x000001FF
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank1_DEF           (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank1_HSH           (0x090B1C4C)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank2_OFF           (20)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank2_WID           ( 9)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank2_MSK           (0x1FF00000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank2_MIN           (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank2_MAX           (511) // 0x000001FF
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank2_DEF           (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_ActiveDccRank2_HSH           (0x09141C4C)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_clkdccupdateoldpath_OFF      (29)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_clkdccupdateoldpath_WID      ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_clkdccupdateoldpath_MSK      (0x20000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_clkdccupdateoldpath_MIN      (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_clkdccupdateoldpath_MAX      (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_clkdccupdateoldpath_DEF      (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_clkdccupdateoldpath_HSH      (0x011D1C4C)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_clkdcccfgbypass_OFF          (30)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_clkdcccfgbypass_WID          ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_clkdcccfgbypass_MSK          (0x40000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_clkdcccfgbypass_MIN          (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_clkdcccfgbypass_MAX          (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_clkdcccfgbypass_DEF          (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_clkdcccfgbypass_HSH          (0x011E1C4C)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_Spare_OFF                    (31)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_Spare_WID                    ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_Spare_MSK                    (0x80000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_Spare_MIN                    (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_Spare_MAX                    (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_Spare_DEF                    (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL3_Spare_HSH                    (0x011F1C4C)

#define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_REG                            (0x00001C50)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ActiveDccRank3_OFF           ( 0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ActiveDccRank3_WID           ( 9)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ActiveDccRank3_MSK           (0x000001FF)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ActiveDccRank3_MIN           (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ActiveDccRank3_MAX           (511) // 0x000001FF
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ActiveDccRank3_DEF           (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ActiveDccRank3_HSH           (0x09001C50)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_Spare_OFF                    ( 9)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_Spare_WID                    ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_Spare_MSK                    (0x00000200)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_Spare_MIN                    (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_Spare_MAX                    (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_Spare_DEF                    (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_Spare_HSH                    (0x01091C50)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_OFF         (10)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_WID         ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_MSK         (0x0000FC00)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_MIN         (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_MAX         (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_DEF         (0x00000020)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_HSH         (0x060A1C50)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_OFF         (16)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_WID         ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_MSK         (0x003F0000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_MIN         (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_MAX         (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_DEF         (0x00000020)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_HSH         (0x06101C50)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_OFF         (22)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_WID         ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_MSK         (0x0FC00000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_MIN         (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_MAX         (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_DEF         (0x00000020)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_HSH         (0x06161C50)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_DccClkViewSelect1_OFF        (28)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_DccClkViewSelect1_WID        ( 4)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_DccClkViewSelect1_MSK        (0xF0000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_DccClkViewSelect1_MIN        (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_DccClkViewSelect1_MAX        (15) // 0x0000000F
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_DccClkViewSelect1_DEF        (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL4_DccClkViewSelect1_HSH        (0x041C1C50)

#define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_REG                            (0x00001C54)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_dccclkupdtstepsize_OFF       ( 0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_dccclkupdtstepsize_WID       ( 2)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_dccclkupdtstepsize_MSK       (0x00000003)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_dccclkupdtstepsize_MIN       (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_dccclkupdtstepsize_MAX       (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_dccclkupdtstepsize_DEF       (0x00000002)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_dccclkupdtstepsize_HSH       (0x02001C54)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_OFF      ( 2)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_WID      ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_MSK      (0x00000004)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_MIN      (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_MAX      (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_DEF      (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_HSH      (0x01021C54)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_OFF         ( 3)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_WID         ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_MSK         (0x000001F8)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_MIN         (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_MAX         (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_DEF         (0x00000020)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_HSH         (0x06031C54)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_BubbleCntVal_OFF             ( 9)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_BubbleCntVal_WID             ( 5)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_BubbleCntVal_MSK             (0x00003E00)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_BubbleCntVal_MIN             (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_BubbleCntVal_MAX             (31) // 0x0000001F
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_BubbleCntVal_DEF             (0x0000000B)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_BubbleCntVal_HSH             (0x05091C54)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicSyncVal_OFF     (14)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicSyncVal_WID     ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicSyncVal_MSK     (0x000FC000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicSyncVal_MIN     (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicSyncVal_MAX     (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicSyncVal_DEF     (0x00000020)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicSyncVal_HSH     (0x060E1C54)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicCntVal_OFF      (20)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicCntVal_WID      (11)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicCntVal_MSK      (0x7FF00000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicCntVal_MIN      (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicCntVal_MAX      (2047) // 0x000007FF
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicCntVal_DEF      (0x0000010E)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicCntVal_HSH      (0x0B141C54)

  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicMode_OFF        (31)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicMode_WID        ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicMode_MSK        (0x80000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicMode_MIN        (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicMode_MAX        (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicMode_DEF        (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKCONTROL5_DeterministicMode_HSH        (0x011F1C54)

#define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS0_REG                        (0x00001C58)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS0_ClkDccDone_OFF           ( 0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS0_ClkDccDone_WID           ( 3)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS0_ClkDccDone_MSK           (0x00000007)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS0_ClkDccDone_MIN           (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS0_ClkDccDone_MAX           (7) // 0x00000007
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS0_ClkDccDone_DEF           (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS0_ClkDccDone_HSH           (0x03001C58)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS0_Spare_OFF                ( 3)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS0_Spare_WID                (29)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS0_Spare_MSK                (0xFFFFFFF8)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS0_Spare_MIN                (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS0_Spare_MAX                (536870911) // 0x1FFFFFFF
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS0_Spare_DEF                (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS0_Spare_HSH                (0x1D031C58)

#define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_REG                        (0x00001C5C)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Spare0_OFF               ( 0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Spare0_WID               (10)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Spare0_MSK               (0x000003FF)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Spare0_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Spare0_MAX               (1023) // 0x000003FF
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Spare0_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Spare0_HSH               (0x0A001C5C)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_CntDone_OFF              (10)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_CntDone_WID              ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_CntDone_MSK              (0x00000400)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_CntDone_MIN              (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_CntDone_MAX              (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_CntDone_DEF              (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_CntDone_HSH              (0x010A1C5C)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_OFF            (11)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_WID            (15)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_MSK            (0x03FFF800)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_MIN            (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_MAX            (32767) // 0x00007FFF
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_DEF            (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_HSH            (0x0F0B1C5C)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Spare1_OFF               (26)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Spare1_WID               ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Spare1_MSK               (0x04000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Spare1_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Spare1_MAX               (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Spare1_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_Spare1_HSH               (0x011A1C5C)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_OFF      (27)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_WID      ( 5)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_MSK      (0xF8000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_MIN      (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_MAX      (31) // 0x0000001F
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_DEF      (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_HSH      (0x051B1C5C)

#define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_REG                        (0x00001C60)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_AuxCnt_OFF               ( 0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_AuxCnt_WID               (16)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_AuxCnt_MSK               (0x0000FFFF)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_AuxCnt_MIN               (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_AuxCnt_MAX               (65535) // 0x0000FFFF
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_AuxCnt_DEF               (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_AuxCnt_HSH               (0x10001C60)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_OFF        (16)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_WID        ( 7)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_MSK        (0x007F0000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_MIN        (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_MAX        (127) // 0x0000007F
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_DEF        (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_HSH        (0x07101C60)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_VTCompOffset_OFF         (23)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_VTCompOffset_WID         ( 7)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_VTCompOffset_MSK         (0x3F800000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_VTCompOffset_MIN         (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_VTCompOffset_MAX         (127) // 0x0000007F
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_VTCompOffset_DEF         (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_VTCompOffset_HSH         (0x07171C60)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_Spare_OFF                (30)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_Spare_WID                ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_Spare_MSK                (0x40000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_Spare_MIN                (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_Spare_MAX                (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_Spare_DEF                (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_Spare_HSH                (0x011E1C60)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_CRVALID_OFF              (31)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_CRVALID_WID              ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_CRVALID_MSK              (0x80000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_CRVALID_MIN              (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_CRVALID_MAX              (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_CRVALID_DEF              (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINSTATUS2_CRVALID_HSH              (0x011F1C60)

#define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_REG                      (0x00001C64)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_OFF     ( 0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_WID     (11)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_MSK     (0x000007FF)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_MIN     (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_MAX     (2047) // 0x000007FF
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_DEF     (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_HSH     (0x0B001C64)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_OFF     (11)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_WID     (17)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_MSK     (0x0FFFF800)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_MIN     (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_MAX     (131071) // 0x0001FFFF
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_DEF     (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_HSH     (0x110B1C64)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_Spare_OFF              (28)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_Spare_WID              ( 4)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_Spare_MSK              (0xF0000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_Spare_MIN              (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_Spare_MAX              (15) // 0x0000000F
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_Spare_DEF              (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINERRSTATUS_Spare_HSH              (0x041C1C64)

#define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_REG                           (0x00001C68)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Clk0DccVal_OFF              ( 0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Clk0DccVal_WID              ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Clk0DccVal_MSK              (0x0000003F)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Clk0DccVal_MIN              (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Clk0DccVal_MAX              (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Clk0DccVal_DEF              (0x00000020)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Clk0DccVal_HSH              (0x06001C68)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Clk1DccVal_OFF              ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Clk1DccVal_WID              ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Clk1DccVal_MSK              (0x00000FC0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Clk1DccVal_MIN              (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Clk1DccVal_MAX              (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Clk1DccVal_DEF              (0x00000020)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Clk1DccVal_HSH              (0x06061C68)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Spare_OFF                   (12)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Spare_WID                   (17)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Spare_MSK                   (0x1FFFF000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Spare_MIN                   (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Spare_MAX                   (131071) // 0x0001FFFF
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Spare_DEF                   (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Spare_HSH                   (0x110C1C68)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_CRVALID_OFF                 (29)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_CRVALID_WID                 ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_CRVALID_MSK                 (0x20000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_CRVALID_MIN                 (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_CRVALID_MAX                 (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_CRVALID_DEF                 (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_CRVALID_HSH                 (0x011D1C68)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_OFF           (30)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_WID           ( 2)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_MSK           (0xC0000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_MIN           (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_MAX           (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_DEF           (0x00000001)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_HSH           (0x021E1C68)

#define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_REG                           (0x00001C6C)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_OFF     ( 0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_WID     ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_MSK     (0x0000003F)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_MIN     (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_MAX     (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_DEF     (0x00000020)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_HSH     (0x06001C6C)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_Spare_OFF                   ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_Spare_WID                   (20)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_Spare_MSK                   (0x03FFFFC0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_Spare_MIN                   (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_Spare_MAX                   (1048575) // 0x000FFFFF
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_Spare_DEF                   (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_Spare_HSH                   (0x14061C6C)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_OFF    (26)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_WID    ( 3)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_MSK    (0x1C000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_MIN    (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_MAX    (7) // 0x00000007
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_DEF    (0x00000005)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_HSH    (0x031A1C6C)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_OFF (29)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_WID ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_MIN (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_HSH (0x011D1C6C)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_RepDccAipCb_OFF             (30)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_RepDccAipCb_WID             ( 2)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_RepDccAipCb_MSK             (0xC0000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_RepDccAipCb_MIN             (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_RepDccAipCb_MAX             (3) // 0x00000003
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_RepDccAipCb_DEF             (0x00000001)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINVAL1_RepDccAipCb_HSH             (0x021E1C6C)

#define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_REG                       (0x00001C70)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_OFF   ( 0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_WID   ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_MSK   (0x0000003F)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_MIN   (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_MAX   (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_DEF   (0x00000020)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_HSH   (0x06001C70)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_OFF   ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_WID   ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_MSK   (0x00000FC0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_MIN   (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_MAX   (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_DEF   (0x00000020)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_HSH   (0x06061C70)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_OFF   (12)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_WID   ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_MSK   (0x0003F000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_MIN   (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_MAX   (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_DEF   (0x00000020)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_HSH   (0x060C1C70)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_OFF   (18)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_WID   ( 6)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_MSK   (0x00FC0000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_MIN   (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_MAX   (63) // 0x0000003F
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_DEF   (0x00000020)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_HSH   (0x06121C70)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_OFF   (24)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_WID   ( 7)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_MSK   (0x7F000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_MIN   (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_MAX   (127) // 0x0000007F
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_DEF   (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_HSH   (0x07181C70)

  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_CRVALID_OFF             (31)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_CRVALID_WID             ( 1)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_CRVALID_MSK             (0x80000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_CRVALID_MIN             (0)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_CRVALID_MAX             (1) // 0x00000001
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_CRVALID_DEF             (0x00000000)
  #define DDRCTLCLKCKE0_CR_DCCCLKTRAINREPLICA0_CRVALID_HSH             (0x011F1C70)

#define DDRCTLCLKCKE1_CR_DDRCRCLKTCOCONTROL0_REG                       (0x00001C80)

  #define DDRCTLCLKCKE1_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_OFF          ( 0)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_WID          ( 6)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_MSK          (0x0000003F)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_MIN          (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_MAX          (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_DEF          (0x00000020)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_HSH          (0x06001C80)

  #define DDRCTLCLKCKE1_CR_DDRCRCLKTCOCONTROL0_Spare_OFF               ( 6)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKTCOCONTROL0_Spare_WID               (26)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKTCOCONTROL0_Spare_MSK               (0xFFFFFFC0)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKTCOCONTROL0_Spare_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKTCOCONTROL0_Spare_MAX               (67108863) // 0x03FFFFFF
  #define DDRCTLCLKCKE1_CR_DDRCRCLKTCOCONTROL0_Spare_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKTCOCONTROL0_Spare_HSH               (0x1A061C80)

#define DDRCTLCLKCKE1_CR_DDRCRCTLTCOCONTROL0_REG                       (0x00001C84)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_OFF          ( 0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_WID          ( 6)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_MSK          (0x0000003F)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_MIN          (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_MAX          (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_DEF          (0x00000020)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_HSH          (0x06001C84)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLTCOCONTROL0_Spare_OFF               ( 6)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLTCOCONTROL0_Spare_WID               (26)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLTCOCONTROL0_Spare_MSK               (0xFFFFFFC0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLTCOCONTROL0_Spare_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLTCOCONTROL0_Spare_MAX               (67108863) // 0x03FFFFFF
  #define DDRCTLCLKCKE1_CR_DDRCRCTLTCOCONTROL0_Spare_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLTCOCONTROL0_Spare_HSH               (0x1A061C84)

#define DDRCTLCLKCKE1_CR_DDRCRLOOPBACKFEEDBACK_REG                     (0x00001C88)

  #define DDRCTLCLKCKE1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_OFF ( 0)
  #define DDRCTLCLKCKE1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_WID (10)
  #define DDRCTLCLKCKE1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MSK (0x000003FF)
  #define DDRCTLCLKCKE1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MIN (0)
  #define DDRCTLCLKCKE1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MAX (1023) // 0x000003FF
  #define DDRCTLCLKCKE1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_DEF (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_HSH (0x0A001C88)

  #define DDRCTLCLKCKE1_CR_DDRCRLOOPBACKFEEDBACK_Spare_OFF             (10)
  #define DDRCTLCLKCKE1_CR_DDRCRLOOPBACKFEEDBACK_Spare_WID             (22)
  #define DDRCTLCLKCKE1_CR_DDRCRLOOPBACKFEEDBACK_Spare_MSK             (0xFFFFFC00)
  #define DDRCTLCLKCKE1_CR_DDRCRLOOPBACKFEEDBACK_Spare_MIN             (0)
  #define DDRCTLCLKCKE1_CR_DDRCRLOOPBACKFEEDBACK_Spare_MAX             (4194303) // 0x003FFFFF
  #define DDRCTLCLKCKE1_CR_DDRCRLOOPBACKFEEDBACK_Spare_DEF             (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRLOOPBACKFEEDBACK_Spare_HSH             (0x160A1C88)

#define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_REG                              (0x00001C90)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_Scomp_OFF                      ( 0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_Scomp_WID                      ( 6)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_Scomp_MSK                      (0x0000003F)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_Scomp_MIN                      (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_Scomp_MAX                      (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_Scomp_DEF                      (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_Scomp_HSH                      (0x06001C90)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_RcompDrvUp_OFF                 ( 6)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_RcompDrvUp_WID                 ( 6)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_RcompDrvUp_MSK                 (0x00000FC0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_RcompDrvUp_MIN                 (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_RcompDrvUp_MAX                 (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_RcompDrvUp_DEF                 (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_RcompDrvUp_HSH                 (0x06061C90)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_RcompDrvDown_OFF               (12)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_RcompDrvDown_WID               ( 6)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_RcompDrvDown_MSK               (0x0003F000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_RcompDrvDown_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_RcompDrvDown_MAX               (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_RcompDrvDown_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_RcompDrvDown_HSH               (0x060C1C90)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_Spare_OFF                      (18)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_Spare_WID                      (14)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_Spare_MSK                      (0xFFFC0000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_Spare_MIN                      (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_Spare_MAX                      (16383) // 0x00003FFF
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_Spare_DEF                      (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMP_Spare_HSH                      (0x0E121C90)

#define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_REG                        (0x00001C94)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF          ( 0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID          ( 5)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK          (0x0000001F)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MIN          (-16)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX          (15) // 0x0000000F
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF          (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_HSH          (0x85001C94)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF     ( 5)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID     ( 4)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK     (0x000001E0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MIN     (-8)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX     (7) // 0x00000007
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF     (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_HSH     (0x84051C94)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF   ( 9)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID   ( 4)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK   (0x00001E00)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MIN   (-8)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX   (7) // 0x00000007
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF   (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_HSH   (0x84091C94)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_Spare_OFF                (13)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_Spare_WID                (19)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_Spare_MSK                (0xFFFFE000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_Spare_MIN                (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_Spare_MAX                (524287) // 0x0007FFFF
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_Spare_DEF                (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCOMPOFFSET_Spare_HSH                (0x130D1C94)

#define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_REG                          (0x00001C98)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode0_OFF             ( 0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode0_WID             ( 7)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode0_MSK             (0x0000007F)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode0_MIN             (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode0_MAX             (127) // 0x0000007F
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode0_DEF             (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode0_HSH             (0x07001C98)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode1_OFF             ( 7)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode1_WID             ( 7)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode1_MSK             (0x00003F80)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode1_MIN             (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode1_MAX             (127) // 0x0000007F
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode1_DEF             (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode1_HSH             (0x07071C98)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode2_OFF             (14)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode2_WID             ( 7)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode2_MSK             (0x001FC000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode2_MIN             (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode2_MAX             (127) // 0x0000007F
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode2_DEF             (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode2_HSH             (0x070E1C98)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode3_OFF             (21)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode3_WID             ( 7)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode3_MSK             (0x0FE00000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode3_MIN             (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode3_MAX             (127) // 0x0000007F
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode3_DEF             (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlPiCode3_HSH             (0x07151C98)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF         (28)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlXoverEnable_WID         ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK         (0x10000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlXoverEnable_MIN         (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX         (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF         (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_CtlXoverEnable_HSH         (0x011C1C98)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_Spare_OFF                  (29)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_Spare_WID                  ( 3)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_Spare_MSK                  (0xE0000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_Spare_MIN                  (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_Spare_MAX                  (7) // 0x00000007
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_Spare_DEF                  (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLPICODING_Spare_HSH                  (0x031D1C98)

#define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_REG                          (0x00001C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RefPi_OFF                  ( 0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RefPi_WID                  ( 4)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RefPi_MSK                  (0x0000000F)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RefPi_MIN                  (-8)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RefPi_MAX                  (7) // 0x00000007
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RefPi_DEF                  (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RefPi_HSH                  (0x84001C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_DllMask_OFF                ( 4)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_DllMask_WID                ( 2)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_DllMask_MSK                (0x00000030)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_DllMask_MIN                (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_DllMask_MAX                (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_DllMask_DEF                (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_DllMask_HSH                (0x02041C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_ClkGateDisable_OFF         ( 6)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_ClkGateDisable_WID         ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_ClkGateDisable_MSK         (0x00000040)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_ClkGateDisable_MIN         (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_ClkGateDisable_MAX         (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_ClkGateDisable_DEF         (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_ClkGateDisable_HSH         (0x01061C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_TxOn_OFF                   ( 7)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_TxOn_WID                   ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_TxOn_MSK                   (0x00000080)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_TxOn_MIN                   (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_TxOn_MAX                   (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_TxOn_DEF                   (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_TxOn_HSH                   (0x01071C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IntClkOn_OFF               ( 8)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IntClkOn_WID               ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IntClkOn_MSK               (0x00000100)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IntClkOn_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IntClkOn_MAX               (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IntClkOn_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IntClkOn_HSH               (0x01081C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RepClkOn_OFF               ( 9)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RepClkOn_WID               ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RepClkOn_MSK               (0x00000200)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RepClkOn_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RepClkOn_MAX               (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RepClkOn_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RepClkOn_HSH               (0x01091C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IolbOrMisr_OFF             (10)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IolbOrMisr_WID             ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IolbOrMisr_MSK             (0x00000400)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IolbOrMisr_MIN             (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IolbOrMisr_MAX             (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IolbOrMisr_DEF             (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IolbOrMisr_HSH             (0x010A1C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IOLBHold_OFF               (11)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IOLBHold_WID               ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IOLBHold_MSK               (0x00000800)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IOLBHold_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IOLBHold_MAX               (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IOLBHold_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_IOLBHold_HSH               (0x010B1C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_OdtMode_OFF                (12)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_OdtMode_WID                ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_OdtMode_MSK                (0x00001000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_OdtMode_MIN                (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_OdtMode_MAX                (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_OdtMode_DEF                (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_OdtMode_HSH                (0x010C1C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF                (13)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CmdTxEq_WID                ( 2)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK                (0x00006000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CmdTxEq_MIN                (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX                (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF                (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CmdTxEq_HSH                (0x020D1C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF         (15)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID         ( 2)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK         (0x00018000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MIN         (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX         (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF         (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_HSH         (0x020F1C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF                (17)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CtlTxEq_WID                ( 2)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK                (0x00060000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CtlTxEq_MIN                (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX                (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF                (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CtlTxEq_HSH                (0x02111C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF               (19)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID               ( 2)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK               (0x00180000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX               (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CtlSRDrv_HSH               (0x02131C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RxVref_OFF                 (21)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RxVref_WID                 ( 6)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RxVref_MSK                 (0x07E00000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RxVref_MIN                 (-32)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RxVref_MAX                 (31) // 0x0000001F
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RxVref_DEF                 (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_RxVref_HSH                 (0x86151C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_VccddqHi_OFF               (27)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_VccddqHi_WID               ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_VccddqHi_MSK               (0x08000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_VccddqHi_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_VccddqHi_MAX               (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_VccddqHi_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_VccddqHi_HSH               (0x011B1C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF            (28)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_DllWeakLock_WID            ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK            (0x10000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_DllWeakLock_MIN            (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX            (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF            (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_DllWeakLock_HSH            (0x011C1C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CMD_Rate_OFF               (29)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CMD_Rate_WID               ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CMD_Rate_MSK               (0x20000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CMD_Rate_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CMD_Rate_MAX               (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CMD_Rate_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_CMD_Rate_HSH               (0x011D1C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF            (30)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID            ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK            (0x40000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MIN            (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX            (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF            (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_HSH            (0x011E1C9C)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_OFF        (31)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_WID        ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_MSK        (0x80000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_MIN        (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_MAX        (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_DEF        (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_HSH        (0x011F1C9C)

#define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_REG                         (0x00001CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_OFF             ( 0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_WID             ( 8)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_MSK             (0x000000FF)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_MIN             (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_MAX             (255) // 0x000000FF
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_DEF             (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_HSH             (0x08001CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_PiClkEn_OFF               ( 8)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_PiClkEn_WID               ( 4)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_PiClkEn_MSK               (0x00000F00)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_PiClkEn_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_PiClkEn_MAX               (15) // 0x0000000F
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_PiClkEn_DEF               (0x0000000F)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_PiClkEn_HSH               (0x04081CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_OFF    (12)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_WID    ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_MSK    (0x00001000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_MIN    (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_MAX    (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_DEF    (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_HSH    (0x010C1CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_OFF   (13)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_WID   ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_MSK   (0x00002000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_MIN   (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_MAX   (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_DEF   (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_HSH   (0x010D1CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_OFF  (14)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_WID  ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_MSK  (0x00004000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_MIN  (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_MAX  (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_DEF  (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_HSH  (0x010E1CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_OFF         (15)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_WID         ( 2)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_MSK         (0x00018000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_MIN         (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_MAX         (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_DEF         (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_HSH         (0x020F1CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_OFF      (17)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_WID      ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_MSK      (0x00020000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_MIN      (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_MAX      (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_DEF      (0x00000001)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_HSH      (0x01111CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_OFF      (18)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_WID      ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_MSK      (0x00040000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_MIN      (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_MAX      (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_DEF      (0x00000001)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_HSH      (0x01121CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_OFF        (19)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_WID        ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_MSK        (0x00080000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_MIN        (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_MAX        (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_DEF        (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_HSH        (0x01131CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_OFF        (20)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_WID        ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_MSK        (0x00100000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_MIN        (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_MAX        (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_DEF        (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_HSH        (0x01141CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_OFF        (21)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_WID        ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_MSK        (0x00200000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_MIN        (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_MAX        (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_DEF        (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_HSH        (0x01151CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_OFF        (22)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_WID        ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_MSK        (0x00400000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_MIN        (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_MAX        (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_DEF        (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_HSH        (0x01161CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_Gear1_OFF                 (23)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_Gear1_WID                 ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_Gear1_MSK                 (0x00800000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_Gear1_MIN                 (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_Gear1_MAX                 (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_Gear1_DEF                 (0x00000001)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_Gear1_HSH                 (0x01171CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_OFF     (24)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_WID     ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_MSK     (0x01000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_MIN     (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_MAX     (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_DEF     (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_HSH     (0x01181CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_OFF    (25)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_WID    ( 2)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_MSK    (0x06000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_MIN    (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_MAX    (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_DEF    (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_HSH    (0x02191CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_OFF      (27)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_WID      ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_MSK      (0x08000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_MIN      (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_MAX      (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_DEF      (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_HSH      (0x011B1CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_OFF (28)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_WID ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_MSK (0x10000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_MIN (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_MAX (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_DEF (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_HSH (0x011C1CA0)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_Spare_OFF                 (29)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_Spare_WID                 ( 3)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_Spare_MSK                 (0xE0000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_Spare_MIN                 (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_Spare_MAX                 (7) // 0x00000007
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_Spare_DEF                 (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLRANKSUSED_Spare_HSH                 (0x031D1CA0)

#define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_REG                         (0x00001CA4)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_RxVref_OFF                ( 0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_RxVref_WID                ( 8)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_RxVref_MSK                (0x000000FF)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_RxVref_MIN                (-128)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_RxVref_MAX                (127) // 0x0000007F
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_RxVref_DEF                (0x00000060)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_RxVref_HSH                (0x88001CA4)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_OFF        ( 8)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_WID        (18)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_MSK        (0x03FFFF00)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_MIN        (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_MAX        (262143) // 0x0003FFFF
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_DEF        (0x00010458)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_HSH        (0x12081CA4)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_OFF           (26)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_WID           ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_MSK           (0x04000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_MIN           (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_MAX           (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_DEF           (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_HSH           (0x011A1CA4)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CKELowsupEn_OFF           (27)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CKELowsupEn_WID           ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CKELowsupEn_MSK           (0x08000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CKELowsupEn_MIN           (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CKELowsupEn_MAX           (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CKELowsupEn_DEF           (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CKELowsupEn_HSH           (0x011B1CA4)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_OFF           (28)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_WID           ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_MSK           (0x10000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_MIN           (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_MAX           (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_DEF           (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_HSH           (0x011C1CA4)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_OFF           (29)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_WID           ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_MSK           (0x20000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_MIN           (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_MAX           (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_DEF           (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_HSH           (0x011D1CA4)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_OFF     (30)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_WID     ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_MSK     (0x40000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_MIN     (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_MAX     (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_DEF     (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_HSH     (0x011E1CA4)

  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_OFF    (31)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_WID    ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_MSK    (0x80000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_MIN    (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_MAX    (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_DEF    (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_HSH    (0x011F1CA4)

#define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_REG                        (0x00001CAC)

  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_OFF          ( 0)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_WID          ( 4)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MSK          (0x0000000F)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MIN          (-8)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MAX          (7) // 0x00000007
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_DEF          (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_HSH          (0x84001CAC)

  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_OFF     ( 4)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_WID     ( 4)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MSK     (0x000000F0)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MIN     (-8)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MAX     (7) // 0x00000007
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_DEF     (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_HSH     (0x84041CAC)

  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_OFF   ( 8)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_WID   ( 4)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MSK   (0x00000F00)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MIN   (-8)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MAX   (7) // 0x00000007
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_DEF   (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_HSH   (0x84081CAC)

  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_OFF (12)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_WID ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_MSK (0x00001000)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_MIN (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_MAX (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_DEF (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_HSH (0x010C1CAC)

  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_Spare_OFF                (13)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_Spare_WID                (19)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_Spare_MSK                (0xFFFFE000)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_Spare_MIN                (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_Spare_MAX                (524287) // 0x0007FFFF
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_Spare_DEF                (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMPOFFSET_Spare_HSH                (0x130D1CAC)

#define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_REG                              (0x00001CB0)

  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_Scomp_OFF                      ( 0)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_Scomp_WID                      ( 5)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_Scomp_MSK                      (0x0000001F)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_Scomp_MIN                      (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_Scomp_MAX                      (31) // 0x0000001F
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_Scomp_DEF                      (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_Scomp_HSH                      (0x05001CB0)

  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_RcompDrvUp_OFF                 ( 5)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_RcompDrvUp_WID                 ( 6)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_RcompDrvUp_MSK                 (0x000007E0)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_RcompDrvUp_MIN                 (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_RcompDrvUp_MAX                 (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_RcompDrvUp_DEF                 (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_RcompDrvUp_HSH                 (0x06051CB0)

  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_RcompDrvDown_OFF               (11)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_RcompDrvDown_WID               ( 6)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_RcompDrvDown_MSK               (0x0001F800)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_RcompDrvDown_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_RcompDrvDown_MAX               (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_RcompDrvDown_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_RcompDrvDown_HSH               (0x060B1CB0)

  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_Spare_OFF                      (17)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_Spare_WID                      (15)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_Spare_MSK                      (0xFFFE0000)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_Spare_MIN                      (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_Spare_MAX                      (32767) // 0x00007FFF
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_Spare_DEF                      (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCLKCOMP_Spare_HSH                      (0x0F111CB0)

#define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_REG                       (0x00001CB4)

  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_ScompOffset_OFF         ( 0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_ScompOffset_WID         ( 5)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_ScompOffset_MSK         (0x0000001F)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_ScompOffset_MIN         (-16)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_ScompOffset_MAX         (15) // 0x0000000F
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_ScompOffset_DEF         (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_ScompOffset_HSH         (0x85001CB4)

  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_RcompDrvUpOffset_OFF    ( 5)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_RcompDrvUpOffset_WID    ( 4)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_RcompDrvUpOffset_MSK    (0x000001E0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_RcompDrvUpOffset_MIN    (-8)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_RcompDrvUpOffset_MAX    (7) // 0x00000007
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_RcompDrvUpOffset_DEF    (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_RcompDrvUpOffset_HSH    (0x84051CB4)

  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_RcompDrvDownOffset_OFF  ( 9)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_RcompDrvDownOffset_WID  ( 4)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_RcompDrvDownOffset_MSK  (0x00001E00)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_RcompDrvDownOffset_MIN  (-8)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_RcompDrvDownOffset_MAX  (7) // 0x00000007
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_RcompDrvDownOffset_DEF  (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_RcompDrvDownOffset_HSH  (0x84091CB4)

  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_Spare_OFF               (13)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_Spare_WID               (19)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_Spare_MSK               (0xFFFFE000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_Spare_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_Spare_MAX               (524287) // 0x0007FFFF
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_Spare_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCCCOMPOFFSET1_Spare_HSH               (0x130D1CB4)

#define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_REG                      (0x00001CB8)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RefPi_OFF              ( 0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RefPi_WID              ( 4)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RefPi_MSK              (0x0000000F)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RefPi_MIN              (-8)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RefPi_MAX              (7) // 0x00000007
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RefPi_DEF              (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RefPi_HSH              (0x84001CB8)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_ClkGateDisable_OFF     ( 4)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_ClkGateDisable_WID     ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_ClkGateDisable_MSK     (0x00000010)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_ClkGateDisable_MIN     (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_ClkGateDisable_MAX     (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_ClkGateDisable_DEF     (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_ClkGateDisable_HSH     (0x01041CB8)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_TxOn_OFF               ( 5)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_TxOn_WID               ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_TxOn_MSK               (0x00000020)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_TxOn_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_TxOn_MAX               (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_TxOn_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_TxOn_HSH               (0x01051CB8)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IntClkOn_OFF           ( 6)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IntClkOn_WID           ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IntClkOn_MSK           (0x00000040)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IntClkOn_MIN           (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IntClkOn_MAX           (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IntClkOn_DEF           (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IntClkOn_HSH           (0x01061CB8)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RepClkOn_OFF           ( 7)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RepClkOn_WID           ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RepClkOn_MSK           (0x00000080)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RepClkOn_MIN           (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RepClkOn_MAX           (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RepClkOn_DEF           (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RepClkOn_HSH           (0x01071CB8)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IolbOrMisr_OFF         ( 8)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IolbOrMisr_WID         ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IolbOrMisr_MSK         (0x00000100)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IolbOrMisr_MIN         (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IolbOrMisr_MAX         (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IolbOrMisr_DEF         (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IolbOrMisr_HSH         (0x01081CB8)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IOLBHold_OFF           ( 9)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IOLBHold_WID           ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IOLBHold_MSK           (0x00000200)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IOLBHold_MIN           (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IOLBHold_MAX           (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IOLBHold_DEF           (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_IOLBHold_HSH           (0x01091CB8)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_OdtMode_OFF            (10)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_OdtMode_WID            ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_OdtMode_MSK            (0x00000400)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_OdtMode_MIN            (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_OdtMode_MAX            (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_OdtMode_DEF            (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_OdtMode_HSH            (0x010A1CB8)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CmdTxEq_OFF            (11)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CmdTxEq_WID            ( 2)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CmdTxEq_MSK            (0x00001800)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CmdTxEq_MIN            (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CmdTxEq_MAX            (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CmdTxEq_DEF            (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CmdTxEq_HSH            (0x020B1CB8)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_EarlyWeakDrive_OFF     (13)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_EarlyWeakDrive_WID     ( 2)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_EarlyWeakDrive_MSK     (0x00006000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_EarlyWeakDrive_MIN     (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_EarlyWeakDrive_MAX     (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_EarlyWeakDrive_DEF     (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_EarlyWeakDrive_HSH     (0x020D1CB8)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CtlTxEq_OFF            (15)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CtlTxEq_WID            ( 2)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CtlTxEq_MSK            (0x00018000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CtlTxEq_MIN            (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CtlTxEq_MAX            (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CtlTxEq_DEF            (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CtlTxEq_HSH            (0x020F1CB8)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CtlSRDrv_OFF           (17)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CtlSRDrv_WID           ( 2)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CtlSRDrv_MSK           (0x00060000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CtlSRDrv_MIN           (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CtlSRDrv_MAX           (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CtlSRDrv_DEF           (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CtlSRDrv_HSH           (0x02111CB8)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RxVref_OFF             (19)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RxVref_WID             ( 6)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RxVref_MSK             (0x01F80000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RxVref_MIN             (-32)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RxVref_MAX             (31) // 0x0000001F
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RxVref_DEF             (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_RxVref_HSH             (0x86131CB8)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CKELowsupEn_OFF        (25)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CKELowsupEn_WID        ( 1)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CKELowsupEn_MSK        (0x02000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CKELowsupEn_MIN        (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CKELowsupEn_MAX        (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CKELowsupEn_DEF        (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_CKELowsupEn_HSH        (0x01191CB8)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_spare_OFF              (26)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_spare_WID              ( 6)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_spare_MSK              (0xFC000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_spare_MIN              (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_spare_MAX              (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_spare_DEF              (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKECONTROLS_spare_HSH              (0x061A1CB8)

#define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_REG                     (0x00001CBC)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_ctlcktxen_OFF         ( 0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_ctlcktxen_WID         ( 2)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_ctlcktxen_MSK         (0x00000003)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_ctlcktxen_MIN         (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_ctlcktxen_MAX         (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_ctlcktxen_DEF         (0x00000003)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_ctlcktxen_HSH         (0x02001CBC)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_PiClkEn_OFF           ( 2)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_PiClkEn_WID           ( 4)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_PiClkEn_MSK           (0x0000003C)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_PiClkEn_MIN           (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_PiClkEn_MAX           (15) // 0x0000000F
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_PiClkEn_DEF           (0x0000000F)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_PiClkEn_HSH           (0x04021CBC)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_DdrCkeCmdSlwDlyByp_OFF ( 6)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_DdrCkeCmdSlwDlyByp_WID ( 2)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_DdrCkeCmdSlwDlyByp_MSK (0x000000C0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_DdrCkeCmdSlwDlyByp_MIN (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_DdrCkeCmdSlwDlyByp_MAX (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_DdrCkeCmdSlwDlyByp_DEF (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_DdrCkeCmdSlwDlyByp_HSH (0x02061CBC)

  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_Spare_OFF             ( 8)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_Spare_WID             (24)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_Spare_MSK             (0xFFFFFF00)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_Spare_MIN             (0)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_Spare_MAX             (16777215) // 0x00FFFFFF
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_Spare_DEF             (0x00000000)
  #define DDRCTLCLKCKE1_CR_DDRCRCCC4CKERANKSUSED_Spare_HSH             (0x18081CBC)

#define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_REG                            (0x00001CC0)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_CRVALID_OFF                  ( 0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_CRVALID_WID                  ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_CRVALID_MSK                  (0x00000001)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_CRVALID_MIN                  (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_CRVALID_MAX                  (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_CRVALID_DEF                  (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_CRVALID_HSH                  (0x01001CC0)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_GVPointG2_OFF                ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_GVPointG2_WID                ( 2)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_GVPointG2_MSK                (0x00000006)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_GVPointG2_MIN                (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_GVPointG2_MAX                (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_GVPointG2_DEF                (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_GVPointG2_HSH                (0x02011CC0)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ReplicaOffsetUse_OFF         ( 3)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ReplicaOffsetUse_WID         ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ReplicaOffsetUse_MSK         (0x00000008)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ReplicaOffsetUse_MIN         (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ReplicaOffsetUse_MAX         (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ReplicaOffsetUse_DEF         (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ReplicaOffsetUse_HSH         (0x01031CC0)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_VTCompOffsetUse_OFF          ( 4)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_VTCompOffsetUse_WID          ( 2)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_VTCompOffsetUse_MSK          (0x00000030)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_VTCompOffsetUse_MIN          (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_VTCompOffsetUse_MAX          (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_VTCompOffsetUse_DEF          (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_VTCompOffsetUse_HSH          (0x02041CC0)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ExtOffset_OFF                ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ExtOffset_WID                ( 7)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ExtOffset_MSK                (0x00001FC0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ExtOffset_MIN                (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ExtOffset_MAX                (127) // 0x0000007F
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ExtOffset_DEF                (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ExtOffset_HSH                (0x07061CC0)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_BiasOffset_OFF               (13)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_BiasOffset_WID               (15)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_BiasOffset_MSK               (0x0FFFE000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_BiasOffset_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_BiasOffset_MAX               (32767) // 0x00007FFF
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_BiasOffset_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_BiasOffset_HSH               (0x0F0D1CC0)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ActiveRanks_OFF              (28)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ActiveRanks_WID              ( 4)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ActiveRanks_MSK              (0xF0000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ActiveRanks_MIN              (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ActiveRanks_MAX              (15) // 0x0000000F
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ActiveRanks_DEF              (0x00000001)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL0_ActiveRanks_HSH              (0x041C1CC0)

#define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_REG                            (0x00001CC4)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DccCodeOvrd_OFF              ( 0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DccCodeOvrd_WID              ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DccCodeOvrd_MSK              (0x0000003F)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DccCodeOvrd_MIN              (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DccCodeOvrd_MAX              (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DccCodeOvrd_DEF              (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DccCodeOvrd_HSH              (0x06001CC4)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_Rank0DccAipCb_OFF            ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_Rank0DccAipCb_WID            ( 2)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_Rank0DccAipCb_MSK            (0x000000C0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_Rank0DccAipCb_MIN            (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_Rank0DccAipCb_MAX            (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_Rank0DccAipCb_DEF            (0x00000001)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_Rank0DccAipCb_HSH            (0x02061CC4)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DccPtrOvrd_OFF               ( 8)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DccPtrOvrd_WID               ( 4)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DccPtrOvrd_MSK               (0x00000F00)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DccPtrOvrd_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DccPtrOvrd_MAX               (15) // 0x0000000F
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DccPtrOvrd_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DccPtrOvrd_HSH               (0x04081CC4)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_RnkPtrOvrd_OFF               (12)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_RnkPtrOvrd_WID               ( 2)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_RnkPtrOvrd_MSK               (0x00003000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_RnkPtrOvrd_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_RnkPtrOvrd_MAX               (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_RnkPtrOvrd_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_RnkPtrOvrd_HSH               (0x020C1CC4)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdDigEnOvrd_OFF             (14)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdDigEnOvrd_WID             ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdDigEnOvrd_MSK             (0x00004000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdDigEnOvrd_MIN             (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdDigEnOvrd_MAX             (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdDigEnOvrd_DEF             (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdDigEnOvrd_HSH             (0x010E1CC4)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_OFF             (15)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_WID             ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_MSK             (0x00008000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_MIN             (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_MAX             (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_DEF             (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_HSH             (0x010F1CC4)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdWindow_OFF                (16)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdWindow_WID                (15)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdWindow_MSK                (0x7FFF0000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdWindow_MIN                (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdWindow_MAX                (32767) // 0x00007FFF
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdWindow_DEF                (0x00000800)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_DcdWindow_HSH                (0x0F101CC4)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_Spare_OFF                    (31)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_Spare_WID                    ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_Spare_MSK                    (0x80000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_Spare_MIN                    (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_Spare_MAX                    (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_Spare_DEF                    (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL1_Spare_HSH                    (0x011F1CC4)

#define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_REG                            (0x00001CC8)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_StartBinCode_OFF             ( 0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_StartBinCode_WID             ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_StartBinCode_MSK             (0x0000003F)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_StartBinCode_MIN             (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_StartBinCode_MAX             (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_StartBinCode_DEF             (0x00000020)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_StartBinCode_HSH             (0x06001CC8)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_CodePtrStartBit_OFF          ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_CodePtrStartBit_WID          ( 3)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_CodePtrStartBit_MSK          (0x000001C0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_CodePtrStartBit_MIN          (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_CodePtrStartBit_MAX          (7) // 0x00000007
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_CodePtrStartBit_DEF          (0x00000005)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_CodePtrStartBit_HSH          (0x03061CC8)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DccTrshOld_OFF               ( 9)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DccTrshOld_WID               (13)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DccTrshOld_MSK               (0x003FFE00)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DccTrshOld_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DccTrshOld_MAX               (8191) // 0x00001FFF
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DccTrshOld_DEF               (0x00000008)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DccTrshOld_HSH               (0x0D091CC8)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DcdCntsStartDiff_OFF         (22)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DcdCntsStartDiff_WID         ( 5)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DcdCntsStartDiff_MSK         (0x07C00000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DcdCntsStartDiff_MIN         (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DcdCntsStartDiff_MAX         (31) // 0x0000001F
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DcdCntsStartDiff_DEF         (0x00000003)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DcdCntsStartDiff_HSH         (0x05161CC8)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_ClkGateDisable_OFF           (27)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_ClkGateDisable_WID           ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_ClkGateDisable_MSK           (0x08000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_ClkGateDisable_MIN           (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_ClkGateDisable_MAX           (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_ClkGateDisable_DEF           (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_ClkGateDisable_HSH           (0x011B1CC8)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DccClkViewSelect0_OFF        (28)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DccClkViewSelect0_WID        ( 4)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DccClkViewSelect0_MSK        (0xF0000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DccClkViewSelect0_MIN        (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DccClkViewSelect0_MAX        (15) // 0x0000000F
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DccClkViewSelect0_DEF        (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL2_DccClkViewSelect0_HSH        (0x041C1CC8)

#define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_REG                            (0x00001CCC)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank0_OFF           ( 0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank0_WID           (11)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank0_MSK           (0x000007FF)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank0_MIN           (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank0_MAX           (2047) // 0x000007FF
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank0_DEF           (0x00000007)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank0_HSH           (0x0B001CCC)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank1_OFF           (11)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank1_WID           ( 9)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank1_MSK           (0x000FF800)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank1_MIN           (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank1_MAX           (511) // 0x000001FF
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank1_DEF           (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank1_HSH           (0x090B1CCC)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank2_OFF           (20)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank2_WID           ( 9)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank2_MSK           (0x1FF00000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank2_MIN           (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank2_MAX           (511) // 0x000001FF
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank2_DEF           (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_ActiveDccRank2_HSH           (0x09141CCC)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_clkdccupdateoldpath_OFF      (29)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_clkdccupdateoldpath_WID      ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_clkdccupdateoldpath_MSK      (0x20000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_clkdccupdateoldpath_MIN      (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_clkdccupdateoldpath_MAX      (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_clkdccupdateoldpath_DEF      (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_clkdccupdateoldpath_HSH      (0x011D1CCC)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_clkdcccfgbypass_OFF          (30)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_clkdcccfgbypass_WID          ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_clkdcccfgbypass_MSK          (0x40000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_clkdcccfgbypass_MIN          (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_clkdcccfgbypass_MAX          (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_clkdcccfgbypass_DEF          (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_clkdcccfgbypass_HSH          (0x011E1CCC)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_Spare_OFF                    (31)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_Spare_WID                    ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_Spare_MSK                    (0x80000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_Spare_MIN                    (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_Spare_MAX                    (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_Spare_DEF                    (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL3_Spare_HSH                    (0x011F1CCC)

#define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_REG                            (0x00001CD0)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ActiveDccRank3_OFF           ( 0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ActiveDccRank3_WID           ( 9)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ActiveDccRank3_MSK           (0x000001FF)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ActiveDccRank3_MIN           (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ActiveDccRank3_MAX           (511) // 0x000001FF
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ActiveDccRank3_DEF           (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ActiveDccRank3_HSH           (0x09001CD0)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_Spare_OFF                    ( 9)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_Spare_WID                    ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_Spare_MSK                    (0x00000200)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_Spare_MIN                    (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_Spare_MAX                    (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_Spare_DEF                    (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_Spare_HSH                    (0x01091CD0)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_OFF         (10)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_WID         ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_MSK         (0x0000FC00)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_MIN         (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_MAX         (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_DEF         (0x00000020)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_HSH         (0x060A1CD0)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_OFF         (16)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_WID         ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_MSK         (0x003F0000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_MIN         (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_MAX         (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_DEF         (0x00000020)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_HSH         (0x06101CD0)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_OFF         (22)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_WID         ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_MSK         (0x0FC00000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_MIN         (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_MAX         (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_DEF         (0x00000020)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_HSH         (0x06161CD0)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_DccClkViewSelect1_OFF        (28)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_DccClkViewSelect1_WID        ( 4)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_DccClkViewSelect1_MSK        (0xF0000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_DccClkViewSelect1_MIN        (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_DccClkViewSelect1_MAX        (15) // 0x0000000F
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_DccClkViewSelect1_DEF        (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL4_DccClkViewSelect1_HSH        (0x041C1CD0)

#define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_REG                            (0x00001CD4)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_dccclkupdtstepsize_OFF       ( 0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_dccclkupdtstepsize_WID       ( 2)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_dccclkupdtstepsize_MSK       (0x00000003)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_dccclkupdtstepsize_MIN       (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_dccclkupdtstepsize_MAX       (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_dccclkupdtstepsize_DEF       (0x00000002)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_dccclkupdtstepsize_HSH       (0x02001CD4)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_OFF      ( 2)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_WID      ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_MSK      (0x00000004)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_MIN      (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_MAX      (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_DEF      (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_HSH      (0x01021CD4)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_OFF         ( 3)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_WID         ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_MSK         (0x000001F8)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_MIN         (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_MAX         (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_DEF         (0x00000020)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_HSH         (0x06031CD4)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_BubbleCntVal_OFF             ( 9)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_BubbleCntVal_WID             ( 5)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_BubbleCntVal_MSK             (0x00003E00)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_BubbleCntVal_MIN             (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_BubbleCntVal_MAX             (31) // 0x0000001F
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_BubbleCntVal_DEF             (0x0000000B)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_BubbleCntVal_HSH             (0x05091CD4)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicSyncVal_OFF     (14)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicSyncVal_WID     ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicSyncVal_MSK     (0x000FC000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicSyncVal_MIN     (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicSyncVal_MAX     (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicSyncVal_DEF     (0x00000020)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicSyncVal_HSH     (0x060E1CD4)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicCntVal_OFF      (20)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicCntVal_WID      (11)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicCntVal_MSK      (0x7FF00000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicCntVal_MIN      (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicCntVal_MAX      (2047) // 0x000007FF
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicCntVal_DEF      (0x0000010E)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicCntVal_HSH      (0x0B141CD4)

  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicMode_OFF        (31)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicMode_WID        ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicMode_MSK        (0x80000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicMode_MIN        (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicMode_MAX        (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicMode_DEF        (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKCONTROL5_DeterministicMode_HSH        (0x011F1CD4)

#define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS0_REG                        (0x00001CD8)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS0_ClkDccDone_OFF           ( 0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS0_ClkDccDone_WID           ( 3)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS0_ClkDccDone_MSK           (0x00000007)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS0_ClkDccDone_MIN           (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS0_ClkDccDone_MAX           (7) // 0x00000007
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS0_ClkDccDone_DEF           (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS0_ClkDccDone_HSH           (0x03001CD8)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS0_Spare_OFF                ( 3)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS0_Spare_WID                (29)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS0_Spare_MSK                (0xFFFFFFF8)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS0_Spare_MIN                (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS0_Spare_MAX                (536870911) // 0x1FFFFFFF
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS0_Spare_DEF                (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS0_Spare_HSH                (0x1D031CD8)

#define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_REG                        (0x00001CDC)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Spare0_OFF               ( 0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Spare0_WID               (10)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Spare0_MSK               (0x000003FF)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Spare0_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Spare0_MAX               (1023) // 0x000003FF
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Spare0_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Spare0_HSH               (0x0A001CDC)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_CntDone_OFF              (10)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_CntDone_WID              ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_CntDone_MSK              (0x00000400)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_CntDone_MIN              (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_CntDone_MAX              (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_CntDone_DEF              (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_CntDone_HSH              (0x010A1CDC)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_OFF            (11)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_WID            (15)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_MSK            (0x03FFF800)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_MIN            (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_MAX            (32767) // 0x00007FFF
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_DEF            (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_HSH            (0x0F0B1CDC)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Spare1_OFF               (26)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Spare1_WID               ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Spare1_MSK               (0x04000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Spare1_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Spare1_MAX               (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Spare1_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_Spare1_HSH               (0x011A1CDC)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_OFF      (27)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_WID      ( 5)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_MSK      (0xF8000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_MIN      (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_MAX      (31) // 0x0000001F
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_DEF      (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_HSH      (0x051B1CDC)

#define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_REG                        (0x00001CE0)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_AuxCnt_OFF               ( 0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_AuxCnt_WID               (16)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_AuxCnt_MSK               (0x0000FFFF)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_AuxCnt_MIN               (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_AuxCnt_MAX               (65535) // 0x0000FFFF
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_AuxCnt_DEF               (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_AuxCnt_HSH               (0x10001CE0)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_OFF        (16)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_WID        ( 7)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_MSK        (0x007F0000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_MIN        (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_MAX        (127) // 0x0000007F
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_DEF        (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_HSH        (0x07101CE0)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_VTCompOffset_OFF         (23)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_VTCompOffset_WID         ( 7)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_VTCompOffset_MSK         (0x3F800000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_VTCompOffset_MIN         (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_VTCompOffset_MAX         (127) // 0x0000007F
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_VTCompOffset_DEF         (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_VTCompOffset_HSH         (0x07171CE0)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_Spare_OFF                (30)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_Spare_WID                ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_Spare_MSK                (0x40000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_Spare_MIN                (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_Spare_MAX                (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_Spare_DEF                (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_Spare_HSH                (0x011E1CE0)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_CRVALID_OFF              (31)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_CRVALID_WID              ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_CRVALID_MSK              (0x80000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_CRVALID_MIN              (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_CRVALID_MAX              (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_CRVALID_DEF              (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINSTATUS2_CRVALID_HSH              (0x011F1CE0)

#define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_REG                      (0x00001CE4)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_OFF     ( 0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_WID     (11)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_MSK     (0x000007FF)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_MIN     (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_MAX     (2047) // 0x000007FF
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_DEF     (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_HSH     (0x0B001CE4)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_OFF     (11)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_WID     (17)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_MSK     (0x0FFFF800)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_MIN     (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_MAX     (131071) // 0x0001FFFF
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_DEF     (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_HSH     (0x110B1CE4)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_Spare_OFF              (28)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_Spare_WID              ( 4)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_Spare_MSK              (0xF0000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_Spare_MIN              (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_Spare_MAX              (15) // 0x0000000F
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_Spare_DEF              (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINERRSTATUS_Spare_HSH              (0x041C1CE4)

#define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_REG                           (0x00001CE8)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Clk0DccVal_OFF              ( 0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Clk0DccVal_WID              ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Clk0DccVal_MSK              (0x0000003F)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Clk0DccVal_MIN              (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Clk0DccVal_MAX              (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Clk0DccVal_DEF              (0x00000020)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Clk0DccVal_HSH              (0x06001CE8)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Clk1DccVal_OFF              ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Clk1DccVal_WID              ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Clk1DccVal_MSK              (0x00000FC0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Clk1DccVal_MIN              (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Clk1DccVal_MAX              (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Clk1DccVal_DEF              (0x00000020)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Clk1DccVal_HSH              (0x06061CE8)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Spare_OFF                   (12)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Spare_WID                   (17)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Spare_MSK                   (0x1FFFF000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Spare_MIN                   (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Spare_MAX                   (131071) // 0x0001FFFF
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Spare_DEF                   (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Spare_HSH                   (0x110C1CE8)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_CRVALID_OFF                 (29)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_CRVALID_WID                 ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_CRVALID_MSK                 (0x20000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_CRVALID_MIN                 (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_CRVALID_MAX                 (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_CRVALID_DEF                 (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_CRVALID_HSH                 (0x011D1CE8)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_OFF           (30)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_WID           ( 2)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_MSK           (0xC0000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_MIN           (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_MAX           (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_DEF           (0x00000001)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_HSH           (0x021E1CE8)

#define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_REG                           (0x00001CEC)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_OFF     ( 0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_WID     ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_MSK     (0x0000003F)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_MIN     (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_MAX     (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_DEF     (0x00000020)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_HSH     (0x06001CEC)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_Spare_OFF                   ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_Spare_WID                   (20)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_Spare_MSK                   (0x03FFFFC0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_Spare_MIN                   (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_Spare_MAX                   (1048575) // 0x000FFFFF
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_Spare_DEF                   (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_Spare_HSH                   (0x14061CEC)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_OFF    (26)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_WID    ( 3)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_MSK    (0x1C000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_MIN    (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_MAX    (7) // 0x00000007
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_DEF    (0x00000005)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_HSH    (0x031A1CEC)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_OFF (29)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_WID ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_MIN (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_HSH (0x011D1CEC)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_RepDccAipCb_OFF             (30)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_RepDccAipCb_WID             ( 2)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_RepDccAipCb_MSK             (0xC0000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_RepDccAipCb_MIN             (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_RepDccAipCb_MAX             (3) // 0x00000003
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_RepDccAipCb_DEF             (0x00000001)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINVAL1_RepDccAipCb_HSH             (0x021E1CEC)

#define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_REG                       (0x00001CF0)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_OFF   ( 0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_WID   ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_MSK   (0x0000003F)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_MIN   (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_MAX   (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_DEF   (0x00000020)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_HSH   (0x06001CF0)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_OFF   ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_WID   ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_MSK   (0x00000FC0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_MIN   (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_MAX   (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_DEF   (0x00000020)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_HSH   (0x06061CF0)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_OFF   (12)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_WID   ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_MSK   (0x0003F000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_MIN   (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_MAX   (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_DEF   (0x00000020)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_HSH   (0x060C1CF0)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_OFF   (18)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_WID   ( 6)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_MSK   (0x00FC0000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_MIN   (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_MAX   (63) // 0x0000003F
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_DEF   (0x00000020)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_HSH   (0x06121CF0)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_OFF   (24)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_WID   ( 7)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_MSK   (0x7F000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_MIN   (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_MAX   (127) // 0x0000007F
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_DEF   (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_HSH   (0x07181CF0)

  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_CRVALID_OFF             (31)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_CRVALID_WID             ( 1)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_CRVALID_MSK             (0x80000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_CRVALID_MIN             (0)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_CRVALID_MAX             (1) // 0x00000001
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_CRVALID_DEF             (0x00000000)
  #define DDRCTLCLKCKE1_CR_DCCCLKTRAINREPLICA0_CRVALID_HSH             (0x011F1CF0)

#define DDRCMDACH0_CR_DDRCRCMDCOMP_REG                                 (0x00001D00)

  #define DDRCMDACH0_CR_DDRCRCMDCOMP_Scomp_OFF                         ( 0)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_Scomp_WID                         ( 6)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_Scomp_MSK                         (0x0000003F)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_Scomp_MIN                         (0)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_Scomp_MAX                         (63) // 0x0000003F
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_Scomp_DEF                         (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_Scomp_HSH                         (0x06001D00)

  #define DDRCMDACH0_CR_DDRCRCMDCOMP_RcompDrvUp_OFF                    ( 6)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_RcompDrvUp_WID                    ( 6)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_RcompDrvUp_MSK                    (0x00000FC0)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_RcompDrvUp_MIN                    (0)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_RcompDrvUp_MAX                    (63) // 0x0000003F
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_RcompDrvUp_DEF                    (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_RcompDrvUp_HSH                    (0x06061D00)

  #define DDRCMDACH0_CR_DDRCRCMDCOMP_RcompDrvDown_OFF                  (12)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_RcompDrvDown_WID                  ( 6)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_RcompDrvDown_MSK                  (0x0003F000)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_RcompDrvDown_MIN                  (0)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_RcompDrvDown_MAX                  (63) // 0x0000003F
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_RcompDrvDown_DEF                  (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_RcompDrvDown_HSH                  (0x060C1D00)

  #define DDRCMDACH0_CR_DDRCRCMDCOMP_Spare_OFF                         (18)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_Spare_WID                         (14)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_Spare_MSK                         (0xFFFC0000)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_Spare_MIN                         (0)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_Spare_MAX                         (16383) // 0x00003FFF
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_Spare_DEF                         (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCOMP_Spare_HSH                         (0x0E121D00)

#define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_REG                           (0x00001D04)

  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF             ( 0)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID             ( 5)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK             (0x0000001F)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MIN             (-16)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX             (15) // 0x0000000F
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF             (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_ScompOffset_HSH             (0x85001D04)

  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF        ( 5)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID        ( 4)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK        (0x000001E0)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MIN        (-8)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX        (7) // 0x00000007
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF        (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_HSH        (0x84051D04)

  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF      ( 9)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID      ( 4)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK      (0x00001E00)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MIN      (-8)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX      (7) // 0x00000007
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF      (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_HSH      (0x84091D04)

  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_Spare_OFF                   (13)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_Spare_WID                   (19)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_Spare_MSK                   (0xFFFFE000)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_Spare_MIN                   (0)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_Spare_MAX                   (524287) // 0x0007FFFF
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_Spare_DEF                   (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCOMPOFFSET_Spare_HSH                   (0x130D1D04)

#define DDRCMDACH0_CR_DDRCRCMDPICODING_REG                             (0x00001D08)

  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi0Code_OFF                ( 0)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi0Code_WID                ( 7)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi0Code_MSK                (0x0000007F)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi0Code_MIN                (0)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi0Code_MAX                (127) // 0x0000007F
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi0Code_DEF                (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi0Code_HSH                (0x07001D08)

  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi1Code_OFF                ( 7)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi1Code_WID                ( 7)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi1Code_MSK                (0x00003F80)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi1Code_MIN                (0)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi1Code_MAX                (127) // 0x0000007F
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi1Code_DEF                (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi1Code_HSH                (0x07071D08)

  #define DDRCMDACH0_CR_DDRCRCMDPICODING_spare0_OFF                    (14)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_spare0_WID                    ( 2)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_spare0_MSK                    (0x0000C000)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_spare0_MIN                    (0)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_spare0_MAX                    (3) // 0x00000003
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_spare0_DEF                    (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_spare0_HSH                    (0x020E1D08)

  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi2Code_OFF                (16)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi2Code_WID                ( 7)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi2Code_MSK                (0x007F0000)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi2Code_MIN                (0)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi2Code_MAX                (127) // 0x0000007F
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi2Code_DEF                (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_CmdPi2Code_HSH                (0x07101D08)

  #define DDRCMDACH0_CR_DDRCRCMDPICODING_spare1_OFF                    (23)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_spare1_WID                    ( 9)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_spare1_MSK                    (0xFF800000)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_spare1_MIN                    (0)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_spare1_MAX                    (511) // 0x000001FF
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_spare1_DEF                    (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDPICODING_spare1_HSH                    (0x09171D08)

#define DDRCMDACH0_CR_DDRCRCMDCONTROLS_REG                             (0x00001D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_RefPi_OFF                     ( 0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_RefPi_WID                     ( 4)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_RefPi_MSK                     (0x0000000F)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_RefPi_MIN                     (-8)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_RefPi_MAX                     (7) // 0x00000007
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_RefPi_DEF                     (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_RefPi_HSH                     (0x84001D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DllMask_OFF                   ( 4)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DllMask_WID                   ( 2)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DllMask_MSK                   (0x00000030)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DllMask_MIN                   (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DllMask_MAX                   (3) // 0x00000003
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DllMask_DEF                   (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DllMask_HSH                   (0x02041D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_ClkGateDisable_OFF            ( 6)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_ClkGateDisable_WID            ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_ClkGateDisable_MSK            (0x00000040)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_ClkGateDisable_MIN            (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_ClkGateDisable_DEF            (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_ClkGateDisable_HSH            (0x01061D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_TxOn_OFF                      ( 7)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_TxOn_WID                      ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_TxOn_MSK                      (0x00000080)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_TxOn_MIN                      (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_TxOn_MAX                      (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_TxOn_DEF                      (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_TxOn_HSH                      (0x01071D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IntClkOn_OFF                  ( 8)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IntClkOn_WID                  ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IntClkOn_MSK                  (0x00000100)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IntClkOn_MIN                  (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IntClkOn_MAX                  (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IntClkOn_DEF                  (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IntClkOn_HSH                  (0x01081D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_RepClkOn_OFF                  ( 9)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_RepClkOn_WID                  ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_RepClkOn_MSK                  (0x00000200)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_RepClkOn_MIN                  (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_RepClkOn_MAX                  (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_RepClkOn_DEF                  (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_RepClkOn_HSH                  (0x01091D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IolbOrMisr_OFF                (10)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IolbOrMisr_WID                ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IolbOrMisr_MSK                (0x00000400)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IolbOrMisr_MIN                (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IolbOrMisr_MAX                (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IolbOrMisr_DEF                (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IolbOrMisr_HSH                (0x010A1D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IolbHold_OFF                  (11)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IolbHold_WID                  ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IolbHold_MSK                  (0x00000800)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IolbHold_MIN                  (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IolbHold_MAX                  (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IolbHold_DEF                  (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_IolbHold_HSH                  (0x010B1D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_OdtMode_OFF                   (12)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_OdtMode_WID                   ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_OdtMode_MSK                   (0x00001000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_OdtMode_MIN                   (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_OdtMode_MAX                   (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_OdtMode_DEF                   (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_OdtMode_HSH                   (0x010C1D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF                   (13)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CmdTxEq_WID                   ( 2)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK                   (0x00006000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MIN                   (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX                   (3) // 0x00000003
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF                   (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CmdTxEq_HSH                   (0x020D1D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF            (15)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID            ( 2)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK            (0x00018000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MIN            (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX            (3) // 0x00000003
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF            (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_HSH            (0x020F1D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_OFF        (17)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_WID        ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_MSK        (0x00020000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_MIN        (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_MAX        (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_DEF        (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_HSH        (0x01111D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_OFF    (18)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_WID    ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_MSK    (0x00040000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_MIN    (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_MAX    (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_DEF    (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_HSH    (0x01121D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_OFF               (19)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_WID               ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_MSK               (0x00080000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_MIN               (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_MAX               (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_DEF               (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_HSH               (0x01131D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_OFF           (20)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_WID           ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_MSK           (0x00100000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_MIN           (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_MAX           (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_DEF           (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_HSH           (0x01141D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_Spares_OFF                    (21)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_Spares_WID                    ( 6)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_Spares_MSK                    (0x07E00000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_Spares_MIN                    (-32)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_Spares_MAX                    (31) // 0x0000001F
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_Spares_DEF                    (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_Spares_HSH                    (0x86151D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_VccddqHi_OFF                  (27)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_VccddqHi_WID                  ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_VccddqHi_MSK                  (0x08000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_VccddqHi_MIN                  (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_VccddqHi_MAX                  (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_VccddqHi_DEF                  (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_VccddqHi_HSH                  (0x011B1D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF               (28)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DllWeakLock_WID               ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK               (0x10000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MIN               (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX               (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF               (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_DllWeakLock_HSH               (0x011C1D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CMD_Rate_OFF                  (29)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CMD_Rate_WID                  ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CMD_Rate_MSK                  (0x20000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CMD_Rate_MIN                  (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CMD_Rate_MAX                  (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CMD_Rate_DEF                  (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_CMD_Rate_HSH                  (0x011D1D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_OFF       (30)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_WID       ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_MSK       (0x40000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_MIN       (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_MAX       (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_DEF       (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_HSH       (0x011E1D0C)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_OFF         (31)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_WID         ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_MSK         (0x80000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_MIN         (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_MAX         (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_DEF         (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_HSH         (0x011F1D0C)

#define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_REG                            (0x00001D10)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_RxVref_OFF                   ( 0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_RxVref_WID                   ( 8)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_RxVref_MSK                   (0x000000FF)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_RxVref_MIN                   (-128)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_RxVref_MAX                   (127) // 0x0000007F
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_RxVref_DEF                   (0x00000060)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_RxVref_HSH                   (0x88001D10)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_OFF              ( 8)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_WID              ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_MSK              (0x00000100)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_MIN              (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_MAX              (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_DEF              (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_HSH              (0x01081D10)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_Gear1_OFF                    ( 9)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_Gear1_WID                    ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_Gear1_MSK                    (0x00000200)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_Gear1_MIN                    (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_Gear1_MAX                    (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_Gear1_DEF                    (0x00000001)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_Gear1_HSH                    (0x01091D10)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_OFF       (10)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_WID       ( 2)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_MSK       (0x00000C00)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_MIN       (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_MAX       (3) // 0x00000003
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_DEF       (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_HSH       (0x020A1D10)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_OFF           (12)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_WID           ( 4)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_MSK           (0x0000F000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_MIN           (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_MAX           (15) // 0x0000000F
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_DEF           (0x0000000F)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_HSH           (0x040C1D10)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_en_OFF                (16)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_en_WID                ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_en_MSK                (0x00010000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_en_MIN                (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_en_MAX                (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_en_DEF                (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_en_HSH                (0x01101D10)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_OFF            (17)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_WID            ( 1)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_MSK            (0x00020000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_MIN            (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_MAX            (1) // 0x00000001
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_DEF            (0x00000001)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_HSH            (0x01111D10)

  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_Spare_OFF                    (18)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_Spare_WID                    (14)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_Spare_MSK                    (0xFFFC0000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_Spare_MIN                    (0)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_Spare_MAX                    (16383) // 0x00003FFF
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_Spare_DEF                    (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDCONTROLS1_Spare_HSH                    (0x0E121D10)

#define DDRCMDACH0_CR_DDRCRLOOPBACKFEEDBACK_REG                        (0x00001D14)

  #define DDRCMDACH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_OFF    ( 0)
  #define DDRCMDACH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_WID    (10)
  #define DDRCMDACH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MSK    (0x000003FF)
  #define DDRCMDACH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MIN    (0)
  #define DDRCMDACH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MAX    (1023) // 0x000003FF
  #define DDRCMDACH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_DEF    (0x00000000)
  #define DDRCMDACH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_HSH    (0x0A001D14)

  #define DDRCMDACH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_OFF                (10)
  #define DDRCMDACH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_WID                (22)
  #define DDRCMDACH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_MSK                (0xFFFFFC00)
  #define DDRCMDACH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_MIN                (0)
  #define DDRCMDACH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_MAX                (4194303) // 0x003FFFFF
  #define DDRCMDACH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_DEF                (0x00000000)
  #define DDRCMDACH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_HSH                (0x160A1D14)

#define DDRCMDACH0_CR_DDRCRCMDTCOCONTROL0_REG                          (0x00001D18)

  #define DDRCMDACH0_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_OFF             ( 0)
  #define DDRCMDACH0_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_WID             ( 6)
  #define DDRCMDACH0_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_MSK             (0x0000003F)
  #define DDRCMDACH0_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_MIN             (0)
  #define DDRCMDACH0_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_MAX             (63) // 0x0000003F
  #define DDRCMDACH0_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_DEF             (0x00000020)
  #define DDRCMDACH0_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_HSH             (0x06001D18)

  #define DDRCMDACH0_CR_DDRCRCMDTCOCONTROL0_Spare_OFF                  ( 6)
  #define DDRCMDACH0_CR_DDRCRCMDTCOCONTROL0_Spare_WID                  (26)
  #define DDRCMDACH0_CR_DDRCRCMDTCOCONTROL0_Spare_MSK                  (0xFFFFFFC0)
  #define DDRCMDACH0_CR_DDRCRCMDTCOCONTROL0_Spare_MIN                  (0)
  #define DDRCMDACH0_CR_DDRCRCMDTCOCONTROL0_Spare_MAX                  (67108863) // 0x03FFFFFF
  #define DDRCMDACH0_CR_DDRCRCMDTCOCONTROL0_Spare_DEF                  (0x00000000)
  #define DDRCMDACH0_CR_DDRCRCMDTCOCONTROL0_Spare_HSH                  (0x1A061D18)

#define DDRCMDACH1_CR_DDRCRCMDCOMP_REG                                 (0x00001D80)

  #define DDRCMDACH1_CR_DDRCRCMDCOMP_Scomp_OFF                         ( 0)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_Scomp_WID                         ( 6)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_Scomp_MSK                         (0x0000003F)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_Scomp_MIN                         (0)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_Scomp_MAX                         (63) // 0x0000003F
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_Scomp_DEF                         (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_Scomp_HSH                         (0x06001D80)

  #define DDRCMDACH1_CR_DDRCRCMDCOMP_RcompDrvUp_OFF                    ( 6)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_RcompDrvUp_WID                    ( 6)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_RcompDrvUp_MSK                    (0x00000FC0)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_RcompDrvUp_MIN                    (0)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_RcompDrvUp_MAX                    (63) // 0x0000003F
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_RcompDrvUp_DEF                    (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_RcompDrvUp_HSH                    (0x06061D80)

  #define DDRCMDACH1_CR_DDRCRCMDCOMP_RcompDrvDown_OFF                  (12)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_RcompDrvDown_WID                  ( 6)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_RcompDrvDown_MSK                  (0x0003F000)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_RcompDrvDown_MIN                  (0)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_RcompDrvDown_MAX                  (63) // 0x0000003F
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_RcompDrvDown_DEF                  (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_RcompDrvDown_HSH                  (0x060C1D80)

  #define DDRCMDACH1_CR_DDRCRCMDCOMP_Spare_OFF                         (18)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_Spare_WID                         (14)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_Spare_MSK                         (0xFFFC0000)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_Spare_MIN                         (0)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_Spare_MAX                         (16383) // 0x00003FFF
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_Spare_DEF                         (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCOMP_Spare_HSH                         (0x0E121D80)

#define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_REG                           (0x00001D84)

  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_OFF             ( 0)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_WID             ( 5)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MSK             (0x0000001F)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MIN             (-16)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_MAX             (15) // 0x0000000F
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_DEF             (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_ScompOffset_HSH             (0x85001D84)

  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_OFF        ( 5)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_WID        ( 4)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MSK        (0x000001E0)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MIN        (-8)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_MAX        (7) // 0x00000007
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_DEF        (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvUpOffset_HSH        (0x84051D84)

  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_OFF      ( 9)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_WID      ( 4)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MSK      (0x00001E00)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MIN      (-8)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_MAX      (7) // 0x00000007
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_DEF      (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_RcompDrvDownOffset_HSH      (0x84091D84)

  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_Spare_OFF                   (13)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_Spare_WID                   (19)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_Spare_MSK                   (0xFFFFE000)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_Spare_MIN                   (0)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_Spare_MAX                   (524287) // 0x0007FFFF
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_Spare_DEF                   (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCOMPOFFSET_Spare_HSH                   (0x130D1D84)

#define DDRCMDACH1_CR_DDRCRCMDPICODING_REG                             (0x00001D88)

  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi0Code_OFF                ( 0)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi0Code_WID                ( 7)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi0Code_MSK                (0x0000007F)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi0Code_MIN                (0)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi0Code_MAX                (127) // 0x0000007F
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi0Code_DEF                (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi0Code_HSH                (0x07001D88)

  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi1Code_OFF                ( 7)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi1Code_WID                ( 7)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi1Code_MSK                (0x00003F80)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi1Code_MIN                (0)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi1Code_MAX                (127) // 0x0000007F
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi1Code_DEF                (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi1Code_HSH                (0x07071D88)

  #define DDRCMDACH1_CR_DDRCRCMDPICODING_spare0_OFF                    (14)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_spare0_WID                    ( 2)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_spare0_MSK                    (0x0000C000)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_spare0_MIN                    (0)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_spare0_MAX                    (3) // 0x00000003
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_spare0_DEF                    (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_spare0_HSH                    (0x020E1D88)

  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi2Code_OFF                (16)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi2Code_WID                ( 7)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi2Code_MSK                (0x007F0000)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi2Code_MIN                (0)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi2Code_MAX                (127) // 0x0000007F
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi2Code_DEF                (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_CmdPi2Code_HSH                (0x07101D88)

  #define DDRCMDACH1_CR_DDRCRCMDPICODING_spare1_OFF                    (23)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_spare1_WID                    ( 9)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_spare1_MSK                    (0xFF800000)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_spare1_MIN                    (0)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_spare1_MAX                    (511) // 0x000001FF
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_spare1_DEF                    (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDPICODING_spare1_HSH                    (0x09171D88)

#define DDRCMDACH1_CR_DDRCRCMDCONTROLS_REG                             (0x00001D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_RefPi_OFF                     ( 0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_RefPi_WID                     ( 4)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_RefPi_MSK                     (0x0000000F)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_RefPi_MIN                     (-8)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_RefPi_MAX                     (7) // 0x00000007
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_RefPi_DEF                     (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_RefPi_HSH                     (0x84001D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DllMask_OFF                   ( 4)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DllMask_WID                   ( 2)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DllMask_MSK                   (0x00000030)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DllMask_MIN                   (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DllMask_MAX                   (3) // 0x00000003
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DllMask_DEF                   (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DllMask_HSH                   (0x02041D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_ClkGateDisable_OFF            ( 6)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_ClkGateDisable_WID            ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_ClkGateDisable_MSK            (0x00000040)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_ClkGateDisable_MIN            (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_ClkGateDisable_DEF            (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_ClkGateDisable_HSH            (0x01061D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_TxOn_OFF                      ( 7)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_TxOn_WID                      ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_TxOn_MSK                      (0x00000080)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_TxOn_MIN                      (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_TxOn_MAX                      (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_TxOn_DEF                      (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_TxOn_HSH                      (0x01071D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IntClkOn_OFF                  ( 8)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IntClkOn_WID                  ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IntClkOn_MSK                  (0x00000100)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IntClkOn_MIN                  (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IntClkOn_MAX                  (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IntClkOn_DEF                  (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IntClkOn_HSH                  (0x01081D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_RepClkOn_OFF                  ( 9)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_RepClkOn_WID                  ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_RepClkOn_MSK                  (0x00000200)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_RepClkOn_MIN                  (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_RepClkOn_MAX                  (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_RepClkOn_DEF                  (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_RepClkOn_HSH                  (0x01091D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IolbOrMisr_OFF                (10)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IolbOrMisr_WID                ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IolbOrMisr_MSK                (0x00000400)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IolbOrMisr_MIN                (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IolbOrMisr_MAX                (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IolbOrMisr_DEF                (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IolbOrMisr_HSH                (0x010A1D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IolbHold_OFF                  (11)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IolbHold_WID                  ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IolbHold_MSK                  (0x00000800)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IolbHold_MIN                  (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IolbHold_MAX                  (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IolbHold_DEF                  (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_IolbHold_HSH                  (0x010B1D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_OdtMode_OFF                   (12)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_OdtMode_WID                   ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_OdtMode_MSK                   (0x00001000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_OdtMode_MIN                   (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_OdtMode_MAX                   (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_OdtMode_DEF                   (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_OdtMode_HSH                   (0x010C1D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CmdTxEq_OFF                   (13)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CmdTxEq_WID                   ( 2)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MSK                   (0x00006000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MIN                   (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CmdTxEq_MAX                   (3) // 0x00000003
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CmdTxEq_DEF                   (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CmdTxEq_HSH                   (0x020D1D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_OFF            (15)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_WID            ( 2)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MSK            (0x00018000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MIN            (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_MAX            (3) // 0x00000003
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_DEF            (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_EarlyWeakDrive_HSH            (0x020F1D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_OFF        (17)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_WID        ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_MSK        (0x00020000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_MIN        (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_MAX        (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_DEF        (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_dis_lp4_cmd_mirror_HSH        (0x01111D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_OFF    (18)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_WID    ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_MSK    (0x00040000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_MIN    (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_MAX    (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_DEF    (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CmdCriClkGateEnGvBlock_HSH    (0x01121D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_OFF               (19)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_WID               ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_MSK               (0x00080000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_MIN               (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_MAX               (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_DEF               (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_LaDrvEnOvrd_HSH               (0x01131D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_OFF           (20)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_WID           ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_MSK           (0x00100000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_MIN           (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_MAX           (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_DEF           (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DdrCmdSlwDlyByp_HSH           (0x01141D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_Spares_OFF                    (21)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_Spares_WID                    ( 6)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_Spares_MSK                    (0x07E00000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_Spares_MIN                    (-32)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_Spares_MAX                    (31) // 0x0000001F
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_Spares_DEF                    (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_Spares_HSH                    (0x86151D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_VccddqHi_OFF                  (27)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_VccddqHi_WID                  ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_VccddqHi_MSK                  (0x08000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_VccddqHi_MIN                  (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_VccddqHi_MAX                  (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_VccddqHi_DEF                  (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_VccddqHi_HSH                  (0x011B1D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DllWeakLock_OFF               (28)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DllWeakLock_WID               ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MSK               (0x10000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MIN               (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DllWeakLock_MAX               (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DllWeakLock_DEF               (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_DllWeakLock_HSH               (0x011C1D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CMD_Rate_OFF                  (29)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CMD_Rate_WID                  ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CMD_Rate_MSK                  (0x20000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CMD_Rate_MIN                  (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CMD_Rate_MAX                  (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CMD_Rate_DEF                  (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_CMD_Rate_HSH                  (0x011D1D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_OFF       (30)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_WID       ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_MSK       (0x40000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_MIN       (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_MAX       (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_DEF       (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_LPDdrCAA_or_CAB_Dis_HSH       (0x011E1D8C)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_OFF         (31)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_WID         ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_MSK         (0x80000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_MIN         (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_MAX         (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_DEF         (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS_Lp4xVoltageSelect_HSH         (0x011F1D8C)

#define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_REG                            (0x00001D90)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_RxVref_OFF                   ( 0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_RxVref_WID                   ( 8)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_RxVref_MSK                   (0x000000FF)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_RxVref_MIN                   (-128)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_RxVref_MAX                   (127) // 0x0000007F
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_RxVref_DEF                   (0x00000060)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_RxVref_HSH                   (0x88001D90)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_OFF              ( 8)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_WID              ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_MSK              (0x00000100)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_MIN              (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_MAX              (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_DEF              (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_CMDLowsupEn_HSH              (0x01081D90)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_Gear1_OFF                    ( 9)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_Gear1_WID                    ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_Gear1_MSK                    (0x00000200)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_Gear1_MIN                    (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_Gear1_MAX                    (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_Gear1_DEF                    (0x00000001)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_Gear1_HSH                    (0x01091D90)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_OFF       (10)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_WID       ( 2)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_MSK       (0x00000C00)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_MIN       (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_MAX       (3) // 0x00000003
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_DEF       (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_xover_mindelay_ctl_HSH       (0x020A1D90)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_OFF           (12)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_WID           ( 4)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_MSK           (0x0000F000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_MIN           (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_MAX           (15) // 0x0000000F
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_DEF           (0x0000000F)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_strengh_HSH           (0x040C1D90)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_en_OFF                (16)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_en_WID                ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_en_MSK                (0x00010000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_en_MIN                (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_en_MAX                (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_en_DEF                (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_en_HSH                (0x01101D90)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_OFF            (17)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_WID            ( 1)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_MSK            (0x00020000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_MIN            (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_MAX            (1) // 0x00000001
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_DEF            (0x00000001)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_cmd_eq_constz_HSH            (0x01111D90)

  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_Spare_OFF                    (18)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_Spare_WID                    (14)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_Spare_MSK                    (0xFFFC0000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_Spare_MIN                    (0)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_Spare_MAX                    (16383) // 0x00003FFF
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_Spare_DEF                    (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDCONTROLS1_Spare_HSH                    (0x0E121D90)

#define DDRCMDACH1_CR_DDRCRLOOPBACKFEEDBACK_REG                        (0x00001D94)

  #define DDRCMDACH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_OFF    ( 0)
  #define DDRCMDACH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_WID    (10)
  #define DDRCMDACH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MSK    (0x000003FF)
  #define DDRCMDACH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MIN    (0)
  #define DDRCMDACH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MAX    (1023) // 0x000003FF
  #define DDRCMDACH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_DEF    (0x00000000)
  #define DDRCMDACH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_HSH    (0x0A001D94)

  #define DDRCMDACH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_OFF                (10)
  #define DDRCMDACH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_WID                (22)
  #define DDRCMDACH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_MSK                (0xFFFFFC00)
  #define DDRCMDACH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_MIN                (0)
  #define DDRCMDACH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_MAX                (4194303) // 0x003FFFFF
  #define DDRCMDACH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_DEF                (0x00000000)
  #define DDRCMDACH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_HSH                (0x160A1D94)

#define DDRCMDACH1_CR_DDRCRCMDTCOCONTROL0_REG                          (0x00001D98)

  #define DDRCMDACH1_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_OFF             ( 0)
  #define DDRCMDACH1_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_WID             ( 6)
  #define DDRCMDACH1_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_MSK             (0x0000003F)
  #define DDRCMDACH1_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_MIN             (0)
  #define DDRCMDACH1_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_MAX             (63) // 0x0000003F
  #define DDRCMDACH1_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_DEF             (0x00000020)
  #define DDRCMDACH1_CR_DDRCRCMDTCOCONTROL0_CmdTcoComp_HSH             (0x06001D98)

  #define DDRCMDACH1_CR_DDRCRCMDTCOCONTROL0_Spare_OFF                  ( 6)
  #define DDRCMDACH1_CR_DDRCRCMDTCOCONTROL0_Spare_WID                  (26)
  #define DDRCMDACH1_CR_DDRCRCMDTCOCONTROL0_Spare_MSK                  (0xFFFFFFC0)
  #define DDRCMDACH1_CR_DDRCRCMDTCOCONTROL0_Spare_MIN                  (0)
  #define DDRCMDACH1_CR_DDRCRCMDTCOCONTROL0_Spare_MAX                  (67108863) // 0x03FFFFFF
  #define DDRCMDACH1_CR_DDRCRCMDTCOCONTROL0_Spare_DEF                  (0x00000000)
  #define DDRCMDACH1_CR_DDRCRCMDTCOCONTROL0_Spare_HSH                  (0x1A061D98)

#define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_REG                             (0x00001E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_OFF                 ( 0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_WID                 ( 8)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_MSK                 (0x000000FF)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_MIN                 (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_MAX                 (255) // 0x000000FF
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_DEF                 (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_HSH                 (0x08001E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_PiClkEn_OFF                   ( 8)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_PiClkEn_WID                   ( 4)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_PiClkEn_MSK                   (0x00000F00)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_PiClkEn_MIN                   (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_PiClkEn_MAX                   (15) // 0x0000000F
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_PiClkEn_DEF                   (0x0000000F)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_PiClkEn_HSH                   (0x04081E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_OFF        (12)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_WID        ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_MSK        (0x00001000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_MIN        (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_MAX        (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_DEF        (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_HSH        (0x010C1E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_OFF       (13)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_WID       ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_MSK       (0x00002000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_MIN       (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_MAX       (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_DEF       (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_HSH       (0x010D1E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_OFF      (14)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_WID      ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_MSK      (0x00004000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_MIN      (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_MAX      (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_DEF      (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_HSH      (0x010E1E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_OFF             (15)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_WID             ( 2)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_MSK             (0x00018000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_MIN             (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_MAX             (3) // 0x00000003
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_DEF             (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_HSH             (0x020F1E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_OFF          (17)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_WID          ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_MSK          (0x00020000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_MIN          (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_MAX          (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_DEF          (0x00000001)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_HSH          (0x01111E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_OFF          (18)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_WID          ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_MSK          (0x00040000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_MIN          (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_MAX          (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_DEF          (0x00000001)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_HSH          (0x01121E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_OFF            (19)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_WID            ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_MSK            (0x00080000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_MIN            (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_MAX            (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_DEF            (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_HSH            (0x01131E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_OFF            (20)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_WID            ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_MSK            (0x00100000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_MIN            (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_MAX            (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_DEF            (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_HSH            (0x01141E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_OFF            (21)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_WID            ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_MSK            (0x00200000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_MIN            (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_MAX            (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_DEF            (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_HSH            (0x01151E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_OFF            (22)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_WID            ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_MSK            (0x00400000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_MIN            (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_MAX            (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_DEF            (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_HSH            (0x01161E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Gear1_OFF                     (23)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Gear1_WID                     ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Gear1_MSK                     (0x00800000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Gear1_MIN                     (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Gear1_MAX                     (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Gear1_DEF                     (0x00000001)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Gear1_HSH                     (0x01171E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_OFF         (24)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_WID         ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_MSK         (0x01000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_MIN         (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_MAX         (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_DEF         (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_HSH         (0x01181E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_OFF        (25)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_WID        ( 2)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_MSK        (0x06000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_MIN        (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_MAX        (3) // 0x00000003
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_DEF        (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_HSH        (0x02191E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_OFF          (27)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_WID          ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_MSK          (0x08000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_MIN          (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_MAX          (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_DEF          (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_HSH          (0x011B1E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_OFF    (28)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_WID    ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_MSK    (0x10000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_MIN    (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_MAX    (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_DEF    (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_HSH    (0x011C1E00)

  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Spare_OFF                     (29)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Spare_WID                     ( 3)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Spare_MSK                     (0xE0000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Spare_MIN                     (0)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Spare_MAX                     (7) // 0x00000007
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Spare_DEF                     (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLRANKSUSED_Spare_HSH                     (0x031D1E00)

#define DDRCTLCH0_CR_DDRCRCTLCOMP_REG                                  (0x00001E10)

  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Scomp_OFF                          ( 0)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Scomp_WID                          ( 6)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Scomp_MSK                          (0x0000003F)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Scomp_MIN                          (0)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Scomp_MAX                          (63) // 0x0000003F
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Scomp_DEF                          (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Scomp_HSH                          (0x06001E10)

  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_OFF                     ( 6)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_WID                     ( 6)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_MSK                     (0x00000FC0)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_MIN                     (0)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_DEF                     (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvUp_HSH                     (0x06061E10)

  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_OFF                   (12)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_WID                   ( 6)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_MSK                   (0x0003F000)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_MIN                   (0)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_DEF                   (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_RcompDrvDown_HSH                   (0x060C1E10)

  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Spare_OFF                          (18)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Spare_WID                          (14)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Spare_MSK                          (0xFFFC0000)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Spare_MIN                          (0)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Spare_MAX                          (16383) // 0x00003FFF
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Spare_DEF                          (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCOMP_Spare_HSH                          (0x0E121E10)

#define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_REG                            (0x00001E14)

  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF              ( 0)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID              ( 5)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK              (0x0000001F)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MIN              (-16)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX              (15) // 0x0000000F
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF              (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_ScompOffset_HSH              (0x85001E14)

  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF         ( 5)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID         ( 4)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK         (0x000001E0)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MIN         (-8)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX         (7) // 0x00000007
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF         (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_HSH         (0x84051E14)

  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF       ( 9)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID       ( 4)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK       (0x00001E00)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MIN       (-8)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX       (7) // 0x00000007
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF       (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_HSH       (0x84091E14)

  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_OFF                    (13)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_WID                    (19)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_MSK                    (0xFFFFE000)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_MIN                    (0)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_MAX                    (524287) // 0x0007FFFF
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_DEF                    (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCOMPOFFSET_Spare_HSH                    (0x130D1E14)

#define DDRCTLCH0_CR_DDRCRCTLPICODING_REG                              (0x00001E18)

  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_OFF                 ( 0)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_WID                 ( 7)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_MSK                 (0x0000007F)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_MIN                 (0)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_MAX                 (127) // 0x0000007F
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_DEF                 (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode0_HSH                 (0x07001E18)

  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_OFF                 ( 7)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_WID                 ( 7)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_MSK                 (0x00003F80)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_MIN                 (0)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_MAX                 (127) // 0x0000007F
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_DEF                 (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode1_HSH                 (0x07071E18)

  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_OFF                 (14)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_WID                 ( 7)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_MSK                 (0x001FC000)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_MIN                 (0)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_MAX                 (127) // 0x0000007F
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_DEF                 (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode2_HSH                 (0x070E1E18)

  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_OFF                 (21)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_WID                 ( 7)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_MSK                 (0x0FE00000)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_MIN                 (0)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_MAX                 (127) // 0x0000007F
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_DEF                 (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlPiCode3_HSH                 (0x07151E18)

  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF             (28)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_WID             ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK             (0x10000000)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_MIN             (0)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX             (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF             (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_CtlXoverEnable_HSH             (0x011C1E18)

  #define DDRCTLCH0_CR_DDRCRCTLPICODING_Spare_OFF                      (29)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_Spare_WID                      ( 3)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_Spare_MSK                      (0xE0000000)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_Spare_MIN                      (0)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_Spare_MAX                      (7) // 0x00000007
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_Spare_DEF                      (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLPICODING_Spare_HSH                      (0x031D1E18)

#define DDRCTLCH0_CR_DDRCRCTLCONTROLS_REG                              (0x00001E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RefPi_OFF                      ( 0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RefPi_WID                      ( 4)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RefPi_MSK                      (0x0000000F)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RefPi_MIN                      (-8)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RefPi_MAX                      (7) // 0x00000007
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RefPi_DEF                      (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RefPi_HSH                      (0x84001E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllMask_OFF                    ( 4)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllMask_WID                    ( 2)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllMask_MSK                    (0x00000030)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllMask_MIN                    (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllMask_MAX                    (3) // 0x00000003
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllMask_DEF                    (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllMask_HSH                    (0x02041E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_ClkGateDisable_OFF             ( 6)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_ClkGateDisable_WID             ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_ClkGateDisable_MSK             (0x00000040)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_ClkGateDisable_MIN             (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_ClkGateDisable_MAX             (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_ClkGateDisable_DEF             (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_ClkGateDisable_HSH             (0x01061E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_TxOn_OFF                       ( 7)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_TxOn_WID                       ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_TxOn_MSK                       (0x00000080)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_TxOn_MIN                       (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_TxOn_MAX                       (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_TxOn_DEF                       (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_TxOn_HSH                       (0x01071E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_OFF                   ( 8)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_WID                   ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_MSK                   (0x00000100)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_MIN                   (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_MAX                   (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_DEF                   (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IntClkOn_HSH                   (0x01081E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_OFF                   ( 9)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_WID                   ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_MSK                   (0x00000200)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_MIN                   (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_MAX                   (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_DEF                   (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RepClkOn_HSH                   (0x01091E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IolbOrMisr_OFF                 (10)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IolbOrMisr_WID                 ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IolbOrMisr_MSK                 (0x00000400)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IolbOrMisr_MIN                 (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IolbOrMisr_MAX                 (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IolbOrMisr_DEF                 (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IolbOrMisr_HSH                 (0x010A1E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IOLBHold_OFF                   (11)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IOLBHold_WID                   ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IOLBHold_MSK                   (0x00000800)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IOLBHold_MIN                   (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IOLBHold_MAX                   (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IOLBHold_DEF                   (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_IOLBHold_HSH                   (0x010B1E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_OFF                    (12)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_WID                    ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_MSK                    (0x00001000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_MIN                    (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_MAX                    (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_DEF                    (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_OdtMode_HSH                    (0x010C1E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF                    (13)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_WID                    ( 2)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK                    (0x00006000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_MIN                    (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX                    (3) // 0x00000003
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF                    (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CmdTxEq_HSH                    (0x020D1E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF             (15)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID             ( 2)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK             (0x00018000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MIN             (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX             (3) // 0x00000003
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF             (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_HSH             (0x020F1E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF                    (17)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_WID                    ( 2)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK                    (0x00060000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_MIN                    (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX                    (3) // 0x00000003
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF                    (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlTxEq_HSH                    (0x02111E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF                   (19)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID                   ( 2)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK                   (0x00180000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MIN                   (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX                   (3) // 0x00000003
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF                   (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CtlSRDrv_HSH                   (0x02131E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RxVref_OFF                     (21)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RxVref_WID                     ( 6)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RxVref_MSK                     (0x07E00000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RxVref_MIN                     (-32)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RxVref_MAX                     (31) // 0x0000001F
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RxVref_DEF                     (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_RxVref_HSH                     (0x86151E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_OFF                   (27)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_WID                   ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_MSK                   (0x08000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_MIN                   (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_MAX                   (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_DEF                   (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_VccddqHi_HSH                   (0x011B1E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF                (28)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_WID                ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK                (0x10000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_MIN                (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX                (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF                (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_DllWeakLock_HSH                (0x011C1E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CMD_Rate_OFF                   (29)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CMD_Rate_WID                   ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CMD_Rate_MSK                   (0x20000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CMD_Rate_MIN                   (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CMD_Rate_MAX                   (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CMD_Rate_DEF                   (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_CMD_Rate_HSH                   (0x011D1E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF                (30)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID                ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK                (0x40000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MIN                (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX                (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF                (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_HSH                (0x011E1E1C)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_OFF            (31)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_WID            ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_MSK            (0x80000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_MIN            (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_MAX            (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_DEF            (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_HSH            (0x011F1E1C)

#define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_REG                             (0x00001E20)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_RxVref_OFF                    ( 0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_RxVref_WID                    ( 8)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_RxVref_MSK                    (0x000000FF)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_RxVref_MIN                    (-128)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_RxVref_MAX                    (127) // 0x0000007F
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_RxVref_DEF                    (0x00000060)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_RxVref_HSH                    (0x88001E20)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_OFF            ( 8)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_WID            (18)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_MSK            (0x03FFFF00)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_MIN            (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_MAX            (262143) // 0x0003FFFF
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_DEF            (0x00010458)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_HSH            (0x12081E20)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_OFF               (26)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_WID               ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_MSK               (0x04000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_MIN               (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_MAX               (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_DEF               (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_HSH               (0x011A1E20)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CKELowsupEn_OFF               (27)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CKELowsupEn_WID               ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CKELowsupEn_MSK               (0x08000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CKELowsupEn_MIN               (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CKELowsupEn_MAX               (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CKELowsupEn_DEF               (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CKELowsupEn_HSH               (0x011B1E20)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_OFF               (28)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_WID               ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_MSK               (0x10000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_MIN               (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_MAX               (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_DEF               (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_HSH               (0x011C1E20)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_OFF               (29)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_WID               ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_MSK               (0x20000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_MIN               (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_MAX               (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_DEF               (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_HSH               (0x011D1E20)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_OFF         (30)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_WID         ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_MSK         (0x40000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_MIN         (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_MAX         (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_DEF         (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_HSH         (0x011E1E20)

  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_OFF        (31)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_WID        ( 1)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_MSK        (0x80000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_MIN        (0)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_MAX        (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_DEF        (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_HSH        (0x011F1E20)

#define DDRCTLCH0_CR_DDRCRLOOPBACKFEEDBACK_REG                         (0x00001E24)

  #define DDRCTLCH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_OFF     ( 0)
  #define DDRCTLCH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_WID     (10)
  #define DDRCTLCH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MSK     (0x000003FF)
  #define DDRCTLCH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MIN     (0)
  #define DDRCTLCH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MAX     (1023) // 0x000003FF
  #define DDRCTLCH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_DEF     (0x00000000)
  #define DDRCTLCH0_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_HSH     (0x0A001E24)

  #define DDRCTLCH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_OFF                 (10)
  #define DDRCTLCH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_WID                 (22)
  #define DDRCTLCH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_MSK                 (0xFFFFFC00)
  #define DDRCTLCH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_MIN                 (0)
  #define DDRCTLCH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_MAX                 (4194303) // 0x003FFFFF
  #define DDRCTLCH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_DEF                 (0x00000000)
  #define DDRCTLCH0_CR_DDRCRLOOPBACKFEEDBACK_Spare_HSH                 (0x160A1E24)

#define DDRCTLCH0_CR_DDRCMDMISR_REG                                    (0x00001E28)

  #define DDRCTLCH0_CR_DDRCMDMISR_shift_16_OFF                         ( 0)
  #define DDRCTLCH0_CR_DDRCMDMISR_shift_16_WID                         ( 1)
  #define DDRCTLCH0_CR_DDRCMDMISR_shift_16_MSK                         (0x00000001)
  #define DDRCTLCH0_CR_DDRCMDMISR_shift_16_MIN                         (0)
  #define DDRCTLCH0_CR_DDRCMDMISR_shift_16_MAX                         (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCMDMISR_shift_16_DEF                         (0x00000000)
  #define DDRCTLCH0_CR_DDRCMDMISR_shift_16_HSH                         (0x01001E28)

  #define DDRCTLCH0_CR_DDRCMDMISR_clken_pulse_mode_OFF                 ( 1)
  #define DDRCTLCH0_CR_DDRCMDMISR_clken_pulse_mode_WID                 ( 1)
  #define DDRCTLCH0_CR_DDRCMDMISR_clken_pulse_mode_MSK                 (0x00000002)
  #define DDRCTLCH0_CR_DDRCMDMISR_clken_pulse_mode_MIN                 (0)
  #define DDRCTLCH0_CR_DDRCMDMISR_clken_pulse_mode_MAX                 (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCMDMISR_clken_pulse_mode_DEF                 (0x00000000)
  #define DDRCTLCH0_CR_DDRCMDMISR_clken_pulse_mode_HSH                 (0x01011E28)

  #define DDRCTLCH0_CR_DDRCMDMISR_reg_clken_mode_OFF                   ( 2)
  #define DDRCTLCH0_CR_DDRCMDMISR_reg_clken_mode_WID                   ( 1)
  #define DDRCTLCH0_CR_DDRCMDMISR_reg_clken_mode_MSK                   (0x00000004)
  #define DDRCTLCH0_CR_DDRCMDMISR_reg_clken_mode_MIN                   (0)
  #define DDRCTLCH0_CR_DDRCMDMISR_reg_clken_mode_MAX                   (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCMDMISR_reg_clken_mode_DEF                   (0x00000000)
  #define DDRCTLCH0_CR_DDRCMDMISR_reg_clken_mode_HSH                   (0x01021E28)

  #define DDRCTLCH0_CR_DDRCMDMISR_reg_clken_OFF                        ( 3)
  #define DDRCTLCH0_CR_DDRCMDMISR_reg_clken_WID                        ( 1)
  #define DDRCTLCH0_CR_DDRCMDMISR_reg_clken_MSK                        (0x00000008)
  #define DDRCTLCH0_CR_DDRCMDMISR_reg_clken_MIN                        (0)
  #define DDRCTLCH0_CR_DDRCMDMISR_reg_clken_MAX                        (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCMDMISR_reg_clken_DEF                        (0x00000000)
  #define DDRCTLCH0_CR_DDRCMDMISR_reg_clken_HSH                        (0x01031E28)

  #define DDRCTLCH0_CR_DDRCMDMISR_feedback_en_OFF                      ( 4)
  #define DDRCTLCH0_CR_DDRCMDMISR_feedback_en_WID                      ( 1)
  #define DDRCTLCH0_CR_DDRCMDMISR_feedback_en_MSK                      (0x00000010)
  #define DDRCTLCH0_CR_DDRCMDMISR_feedback_en_MIN                      (0)
  #define DDRCTLCH0_CR_DDRCMDMISR_feedback_en_MAX                      (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCMDMISR_feedback_en_DEF                      (0x00000000)
  #define DDRCTLCH0_CR_DDRCMDMISR_feedback_en_HSH                      (0x01041E28)

  #define DDRCTLCH0_CR_DDRCMDMISR_event_mode_OFF                       ( 5)
  #define DDRCTLCH0_CR_DDRCMDMISR_event_mode_WID                       ( 1)
  #define DDRCTLCH0_CR_DDRCMDMISR_event_mode_MSK                       (0x00000020)
  #define DDRCTLCH0_CR_DDRCMDMISR_event_mode_MIN                       (0)
  #define DDRCTLCH0_CR_DDRCMDMISR_event_mode_MAX                       (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCMDMISR_event_mode_DEF                       (0x00000000)
  #define DDRCTLCH0_CR_DDRCMDMISR_event_mode_HSH                       (0x01051E28)

  #define DDRCTLCH0_CR_DDRCMDMISR_lfsr_reset_OFF                       ( 6)
  #define DDRCTLCH0_CR_DDRCMDMISR_lfsr_reset_WID                       ( 1)
  #define DDRCTLCH0_CR_DDRCMDMISR_lfsr_reset_MSK                       (0x00000040)
  #define DDRCTLCH0_CR_DDRCMDMISR_lfsr_reset_MIN                       (0)
  #define DDRCTLCH0_CR_DDRCMDMISR_lfsr_reset_MAX                       (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCMDMISR_lfsr_reset_DEF                       (0x00000000)
  #define DDRCTLCH0_CR_DDRCMDMISR_lfsr_reset_HSH                       (0x01061E28)

  #define DDRCTLCH0_CR_DDRCMDMISR_sdo_en_OFF                           ( 7)
  #define DDRCTLCH0_CR_DDRCMDMISR_sdo_en_WID                           ( 1)
  #define DDRCTLCH0_CR_DDRCMDMISR_sdo_en_MSK                           (0x00000080)
  #define DDRCTLCH0_CR_DDRCMDMISR_sdo_en_MIN                           (0)
  #define DDRCTLCH0_CR_DDRCMDMISR_sdo_en_MAX                           (1) // 0x00000001
  #define DDRCTLCH0_CR_DDRCMDMISR_sdo_en_DEF                           (0x00000000)
  #define DDRCTLCH0_CR_DDRCMDMISR_sdo_en_HSH                           (0x01071E28)

  #define DDRCTLCH0_CR_DDRCMDMISR_reserved0_OFF                        ( 8)
  #define DDRCTLCH0_CR_DDRCMDMISR_reserved0_WID                        ( 8)
  #define DDRCTLCH0_CR_DDRCMDMISR_reserved0_MSK                        (0x0000FF00)
  #define DDRCTLCH0_CR_DDRCMDMISR_reserved0_MIN                        (0)
  #define DDRCTLCH0_CR_DDRCMDMISR_reserved0_MAX                        (255) // 0x000000FF
  #define DDRCTLCH0_CR_DDRCMDMISR_reserved0_DEF                        (0x00000000)
  #define DDRCTLCH0_CR_DDRCMDMISR_reserved0_HSH                        (0x08081E28)

  #define DDRCTLCH0_CR_DDRCMDMISR_cr_rd_data_OFF                       (16)
  #define DDRCTLCH0_CR_DDRCMDMISR_cr_rd_data_WID                       (16)
  #define DDRCTLCH0_CR_DDRCMDMISR_cr_rd_data_MSK                       (0xFFFF0000)
  #define DDRCTLCH0_CR_DDRCMDMISR_cr_rd_data_MIN                       (0)
  #define DDRCTLCH0_CR_DDRCMDMISR_cr_rd_data_MAX                       (65535) // 0x0000FFFF
  #define DDRCTLCH0_CR_DDRCMDMISR_cr_rd_data_DEF                       (0x00000000)
  #define DDRCTLCH0_CR_DDRCMDMISR_cr_rd_data_HSH                       (0x10101E28)

#define DDRCTLCH0_CR_DDRCRCTLTCOCONTROL0_REG                           (0x00001E2C)

  #define DDRCTLCH0_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_OFF              ( 0)
  #define DDRCTLCH0_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_WID              ( 6)
  #define DDRCTLCH0_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_MSK              (0x0000003F)
  #define DDRCTLCH0_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_MIN              (0)
  #define DDRCTLCH0_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_MAX              (63) // 0x0000003F
  #define DDRCTLCH0_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_DEF              (0x00000020)
  #define DDRCTLCH0_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_HSH              (0x06001E2C)

  #define DDRCTLCH0_CR_DDRCRCTLTCOCONTROL0_Spare_OFF                   ( 6)
  #define DDRCTLCH0_CR_DDRCRCTLTCOCONTROL0_Spare_WID                   (26)
  #define DDRCTLCH0_CR_DDRCRCTLTCOCONTROL0_Spare_MSK                   (0xFFFFFFC0)
  #define DDRCTLCH0_CR_DDRCRCTLTCOCONTROL0_Spare_MIN                   (0)
  #define DDRCTLCH0_CR_DDRCRCTLTCOCONTROL0_Spare_MAX                   (67108863) // 0x03FFFFFF
  #define DDRCTLCH0_CR_DDRCRCTLTCOCONTROL0_Spare_DEF                   (0x00000000)
  #define DDRCTLCH0_CR_DDRCRCTLTCOCONTROL0_Spare_HSH                   (0x1A061E2C)

#define DDRCLKCH0_CR_DDRCRCLKCOMP_REG                                  (0x00001E30)

  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Scomp_OFF                          ( 0)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Scomp_WID                          ( 5)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Scomp_MSK                          (0x0000001F)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Scomp_MIN                          (0)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Scomp_MAX                          (31) // 0x0000001F
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Scomp_DEF                          (0x00000000)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Scomp_HSH                          (0x05001E30)

  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvUp_OFF                     ( 5)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvUp_WID                     ( 6)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvUp_MSK                     (0x000007E0)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvUp_MIN                     (0)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvUp_DEF                     (0x00000000)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvUp_HSH                     (0x06051E30)

  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvDown_OFF                   (11)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvDown_WID                   ( 6)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvDown_MSK                   (0x0001F800)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvDown_MIN                   (0)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvDown_DEF                   (0x00000000)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_RcompDrvDown_HSH                   (0x060B1E30)

  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Spare_OFF                          (17)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Spare_WID                          (15)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Spare_MSK                          (0xFFFE0000)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Spare_MIN                          (0)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Spare_MAX                          (32767) // 0x00007FFF
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Spare_DEF                          (0x00000000)
  #define DDRCLKCH0_CR_DDRCRCLKCOMP_Spare_HSH                          (0x0F111E30)

#define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_REG                            (0x00001E34)

  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_OFF              ( 0)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_WID              ( 4)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MSK              (0x0000000F)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MIN              (-8)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MAX              (7) // 0x00000007
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_DEF              (0x00000000)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ScompOffset_HSH              (0x84001E34)

  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_OFF         ( 4)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_WID         ( 4)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MSK         (0x000000F0)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MIN         (-8)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MAX         (7) // 0x00000007
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_DEF         (0x00000000)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_HSH         (0x84041E34)

  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_OFF       ( 8)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_WID       ( 4)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MSK       (0x00000F00)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MIN       (-8)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MAX       (7) // 0x00000007
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_DEF       (0x00000000)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_HSH       (0x84081E34)

  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_OFF    (12)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_WID    ( 1)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_MSK    (0x00001000)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_MIN    (0)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_MAX    (1) // 0x00000001
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_DEF    (0x00000000)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_HSH    (0x010C1E34)

  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_Spare_OFF                    (13)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_Spare_WID                    (19)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_Spare_MSK                    (0xFFFFE000)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_Spare_MIN                    (0)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_Spare_MAX                    (524287) // 0x0007FFFF
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_Spare_DEF                    (0x00000000)
  #define DDRCLKCH0_CR_DDRCRCLKCOMPOFFSET_Spare_HSH                    (0x130D1E34)

#define DDRCLKCH0_CR_DDR4CRBSCANDATA_REG                               (0x00001E38)

  #define DDRCLKCH0_CR_DDR4CRBSCANDATA_Spare_OFF                       ( 0)
  #define DDRCLKCH0_CR_DDR4CRBSCANDATA_Spare_WID                       (32)
  #define DDRCLKCH0_CR_DDR4CRBSCANDATA_Spare_MSK                       (0xFFFFFFFF)
  #define DDRCLKCH0_CR_DDR4CRBSCANDATA_Spare_MIN                       (0)
  #define DDRCLKCH0_CR_DDR4CRBSCANDATA_Spare_MAX                       (4294967295) // 0xFFFFFFFF
  #define DDRCLKCH0_CR_DDR4CRBSCANDATA_Spare_DEF                       (0x00000000)
  #define DDRCLKCH0_CR_DDR4CRBSCANDATA_Spare_HSH                       (0x20001E38)

#define DDRCLKCH0_CR_DCCCLKCONTROL0_REG                                (0x00001E3C)

  #define DDRCLKCH0_CR_DCCCLKCONTROL0_CRVALID_OFF                      ( 0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_CRVALID_WID                      ( 1)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_CRVALID_MSK                      (0x00000001)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_CRVALID_MIN                      (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_CRVALID_MAX                      (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_CRVALID_DEF                      (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_CRVALID_HSH                      (0x01001E3C)

  #define DDRCLKCH0_CR_DCCCLKCONTROL0_GVPointG2_OFF                    ( 1)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_GVPointG2_WID                    ( 2)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_GVPointG2_MSK                    (0x00000006)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_GVPointG2_MIN                    (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_GVPointG2_MAX                    (3) // 0x00000003
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_GVPointG2_DEF                    (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_GVPointG2_HSH                    (0x02011E3C)

  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ReplicaOffsetUse_OFF             ( 3)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ReplicaOffsetUse_WID             ( 1)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ReplicaOffsetUse_MSK             (0x00000008)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ReplicaOffsetUse_MIN             (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ReplicaOffsetUse_MAX             (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ReplicaOffsetUse_DEF             (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ReplicaOffsetUse_HSH             (0x01031E3C)

  #define DDRCLKCH0_CR_DCCCLKCONTROL0_VTCompOffsetUse_OFF              ( 4)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_VTCompOffsetUse_WID              ( 2)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_VTCompOffsetUse_MSK              (0x00000030)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_VTCompOffsetUse_MIN              (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_VTCompOffsetUse_MAX              (3) // 0x00000003
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_VTCompOffsetUse_DEF              (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_VTCompOffsetUse_HSH              (0x02041E3C)

  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ExtOffset_OFF                    ( 6)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ExtOffset_WID                    ( 7)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ExtOffset_MSK                    (0x00001FC0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ExtOffset_MIN                    (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ExtOffset_MAX                    (127) // 0x0000007F
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ExtOffset_DEF                    (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ExtOffset_HSH                    (0x07061E3C)

  #define DDRCLKCH0_CR_DCCCLKCONTROL0_BiasOffset_OFF                   (13)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_BiasOffset_WID                   (15)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_BiasOffset_MSK                   (0x0FFFE000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_BiasOffset_MIN                   (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_BiasOffset_MAX                   (32767) // 0x00007FFF
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_BiasOffset_DEF                   (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_BiasOffset_HSH                   (0x0F0D1E3C)

  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ActiveRanks_OFF                  (28)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ActiveRanks_WID                  ( 4)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ActiveRanks_MSK                  (0xF0000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ActiveRanks_MIN                  (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ActiveRanks_MAX                  (15) // 0x0000000F
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ActiveRanks_DEF                  (0x00000001)
  #define DDRCLKCH0_CR_DCCCLKCONTROL0_ActiveRanks_HSH                  (0x041C1E3C)

#define DDRCLKCH0_CR_DCCCLKCONTROL1_REG                                (0x00001E40)

  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DccCodeOvrd_OFF                  ( 0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DccCodeOvrd_WID                  ( 6)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DccCodeOvrd_MSK                  (0x0000003F)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DccCodeOvrd_MIN                  (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DccCodeOvrd_MAX                  (63) // 0x0000003F
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DccCodeOvrd_DEF                  (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DccCodeOvrd_HSH                  (0x06001E40)

  #define DDRCLKCH0_CR_DCCCLKCONTROL1_Rank0DccAipCb_OFF                ( 6)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_Rank0DccAipCb_WID                ( 2)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_Rank0DccAipCb_MSK                (0x000000C0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_Rank0DccAipCb_MIN                (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_Rank0DccAipCb_MAX                (3) // 0x00000003
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_Rank0DccAipCb_DEF                (0x00000001)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_Rank0DccAipCb_HSH                (0x02061E40)

  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DccPtrOvrd_OFF                   ( 8)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DccPtrOvrd_WID                   ( 4)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DccPtrOvrd_MSK                   (0x00000F00)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DccPtrOvrd_MIN                   (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DccPtrOvrd_MAX                   (15) // 0x0000000F
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DccPtrOvrd_DEF                   (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DccPtrOvrd_HSH                   (0x04081E40)

  #define DDRCLKCH0_CR_DCCCLKCONTROL1_RnkPtrOvrd_OFF                   (12)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_RnkPtrOvrd_WID                   ( 2)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_RnkPtrOvrd_MSK                   (0x00003000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_RnkPtrOvrd_MIN                   (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_RnkPtrOvrd_MAX                   (3) // 0x00000003
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_RnkPtrOvrd_DEF                   (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_RnkPtrOvrd_HSH                   (0x020C1E40)

  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdDigEnOvrd_OFF                 (14)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdDigEnOvrd_WID                 ( 1)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdDigEnOvrd_MSK                 (0x00004000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdDigEnOvrd_MIN                 (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdDigEnOvrd_MAX                 (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdDigEnOvrd_DEF                 (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdDigEnOvrd_HSH                 (0x010E1E40)

  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_OFF                 (15)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_WID                 ( 1)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_MSK                 (0x00008000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_MIN                 (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_MAX                 (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_DEF                 (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_HSH                 (0x010F1E40)

  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdWindow_OFF                    (16)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdWindow_WID                    (15)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdWindow_MSK                    (0x7FFF0000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdWindow_MIN                    (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdWindow_MAX                    (32767) // 0x00007FFF
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdWindow_DEF                    (0x00000800)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_DcdWindow_HSH                    (0x0F101E40)

  #define DDRCLKCH0_CR_DCCCLKCONTROL1_Spare_OFF                        (31)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_Spare_WID                        ( 1)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_Spare_MSK                        (0x80000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_Spare_MIN                        (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_Spare_MAX                        (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_Spare_DEF                        (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL1_Spare_HSH                        (0x011F1E40)

#define DDRCLKCH0_CR_DCCCLKCONTROL2_REG                                (0x00001E44)

  #define DDRCLKCH0_CR_DCCCLKCONTROL2_StartBinCode_OFF                 ( 0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_StartBinCode_WID                 ( 6)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_StartBinCode_MSK                 (0x0000003F)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_StartBinCode_MIN                 (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_StartBinCode_MAX                 (63) // 0x0000003F
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_StartBinCode_DEF                 (0x00000020)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_StartBinCode_HSH                 (0x06001E44)

  #define DDRCLKCH0_CR_DCCCLKCONTROL2_CodePtrStartBit_OFF              ( 6)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_CodePtrStartBit_WID              ( 3)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_CodePtrStartBit_MSK              (0x000001C0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_CodePtrStartBit_MIN              (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_CodePtrStartBit_MAX              (7) // 0x00000007
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_CodePtrStartBit_DEF              (0x00000005)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_CodePtrStartBit_HSH              (0x03061E44)

  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DccTrshOld_OFF                   ( 9)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DccTrshOld_WID                   (13)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DccTrshOld_MSK                   (0x003FFE00)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DccTrshOld_MIN                   (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DccTrshOld_MAX                   (8191) // 0x00001FFF
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DccTrshOld_DEF                   (0x00000008)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DccTrshOld_HSH                   (0x0D091E44)

  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DcdCntsStartDiff_OFF             (22)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DcdCntsStartDiff_WID             ( 5)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DcdCntsStartDiff_MSK             (0x07C00000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DcdCntsStartDiff_MIN             (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DcdCntsStartDiff_MAX             (31) // 0x0000001F
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DcdCntsStartDiff_DEF             (0x00000003)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DcdCntsStartDiff_HSH             (0x05161E44)

  #define DDRCLKCH0_CR_DCCCLKCONTROL2_ClkGateDisable_OFF               (27)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_ClkGateDisable_WID               ( 1)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_ClkGateDisable_MSK               (0x08000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_ClkGateDisable_MIN               (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_ClkGateDisable_MAX               (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_ClkGateDisable_DEF               (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_ClkGateDisable_HSH               (0x011B1E44)

  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DccClkViewSelect0_OFF            (28)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DccClkViewSelect0_WID            ( 4)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DccClkViewSelect0_MSK            (0xF0000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DccClkViewSelect0_MIN            (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DccClkViewSelect0_MAX            (15) // 0x0000000F
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DccClkViewSelect0_DEF            (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL2_DccClkViewSelect0_HSH            (0x041C1E44)

#define DDRCLKCH0_CR_DCCCLKCONTROL3_REG                                (0x00001E48)

  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank0_OFF               ( 0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank0_WID               (11)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank0_MSK               (0x000007FF)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank0_MIN               (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank0_MAX               (2047) // 0x000007FF
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank0_DEF               (0x00000007)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank0_HSH               (0x0B001E48)

  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank1_OFF               (11)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank1_WID               ( 9)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank1_MSK               (0x000FF800)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank1_MIN               (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank1_MAX               (511) // 0x000001FF
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank1_DEF               (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank1_HSH               (0x090B1E48)

  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank2_OFF               (20)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank2_WID               ( 9)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank2_MSK               (0x1FF00000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank2_MIN               (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank2_MAX               (511) // 0x000001FF
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank2_DEF               (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_ActiveDccRank2_HSH               (0x09141E48)

  #define DDRCLKCH0_CR_DCCCLKCONTROL3_clkdccupdateoldpath_OFF          (29)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_clkdccupdateoldpath_WID          ( 1)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_clkdccupdateoldpath_MSK          (0x20000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_clkdccupdateoldpath_MIN          (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_clkdccupdateoldpath_MAX          (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_clkdccupdateoldpath_DEF          (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_clkdccupdateoldpath_HSH          (0x011D1E48)

  #define DDRCLKCH0_CR_DCCCLKCONTROL3_clkdcccfgbypass_OFF              (30)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_clkdcccfgbypass_WID              ( 1)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_clkdcccfgbypass_MSK              (0x40000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_clkdcccfgbypass_MIN              (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_clkdcccfgbypass_MAX              (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_clkdcccfgbypass_DEF              (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_clkdcccfgbypass_HSH              (0x011E1E48)

  #define DDRCLKCH0_CR_DCCCLKCONTROL3_Spare_OFF                        (31)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_Spare_WID                        ( 1)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_Spare_MSK                        (0x80000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_Spare_MIN                        (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_Spare_MAX                        (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_Spare_DEF                        (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL3_Spare_HSH                        (0x011F1E48)

#define DDRCLKCH0_CR_DCCCLKCONTROL4_REG                                (0x00001E4C)

  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ActiveDccRank3_OFF               ( 0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ActiveDccRank3_WID               ( 9)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ActiveDccRank3_MSK               (0x000001FF)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ActiveDccRank3_MIN               (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ActiveDccRank3_MAX               (511) // 0x000001FF
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ActiveDccRank3_DEF               (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ActiveDccRank3_HSH               (0x09001E4C)

  #define DDRCLKCH0_CR_DCCCLKCONTROL4_Spare_OFF                        ( 9)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_Spare_WID                        ( 1)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_Spare_MSK                        (0x00000200)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_Spare_MIN                        (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_Spare_MAX                        (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_Spare_DEF                        (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_Spare_HSH                        (0x01091E4C)

  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_OFF             (10)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_WID             ( 6)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_MSK             (0x0000FC00)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_MIN             (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_MAX             (63) // 0x0000003F
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_DEF             (0x00000020)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_HSH             (0x060A1E4C)

  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_OFF             (16)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_WID             ( 6)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_MSK             (0x003F0000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_MIN             (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_MAX             (63) // 0x0000003F
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_DEF             (0x00000020)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_HSH             (0x06101E4C)

  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_OFF             (22)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_WID             ( 6)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_MSK             (0x0FC00000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_MIN             (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_MAX             (63) // 0x0000003F
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_DEF             (0x00000020)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_HSH             (0x06161E4C)

  #define DDRCLKCH0_CR_DCCCLKCONTROL4_DccClkViewSelect1_OFF            (28)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_DccClkViewSelect1_WID            ( 4)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_DccClkViewSelect1_MSK            (0xF0000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_DccClkViewSelect1_MIN            (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_DccClkViewSelect1_MAX            (15) // 0x0000000F
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_DccClkViewSelect1_DEF            (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL4_DccClkViewSelect1_HSH            (0x041C1E4C)

#define DDRCLKCH0_CR_DCCCLKCONTROL5_REG                                (0x00001E50)

  #define DDRCLKCH0_CR_DCCCLKCONTROL5_dccclkupdtstepsize_OFF           ( 0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_dccclkupdtstepsize_WID           ( 2)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_dccclkupdtstepsize_MSK           (0x00000003)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_dccclkupdtstepsize_MIN           (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_dccclkupdtstepsize_MAX           (3) // 0x00000003
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_dccclkupdtstepsize_DEF           (0x00000002)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_dccclkupdtstepsize_HSH           (0x02001E50)

  #define DDRCLKCH0_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_OFF          ( 2)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_WID          ( 1)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_MSK          (0x00000004)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_MIN          (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_MAX          (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_DEF          (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_HSH          (0x01021E50)

  #define DDRCLKCH0_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_OFF             ( 3)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_WID             ( 6)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_MSK             (0x000001F8)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_MIN             (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_MAX             (63) // 0x0000003F
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_DEF             (0x00000020)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_HSH             (0x06031E50)

  #define DDRCLKCH0_CR_DCCCLKCONTROL5_BubbleCntVal_OFF                 ( 9)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_BubbleCntVal_WID                 ( 5)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_BubbleCntVal_MSK                 (0x00003E00)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_BubbleCntVal_MIN                 (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_BubbleCntVal_MAX                 (31) // 0x0000001F
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_BubbleCntVal_DEF                 (0x0000000B)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_BubbleCntVal_HSH                 (0x05091E50)

  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicSyncVal_OFF         (14)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicSyncVal_WID         ( 6)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicSyncVal_MSK         (0x000FC000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicSyncVal_MIN         (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicSyncVal_MAX         (63) // 0x0000003F
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicSyncVal_DEF         (0x00000020)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicSyncVal_HSH         (0x060E1E50)

  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicCntVal_OFF          (20)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicCntVal_WID          (11)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicCntVal_MSK          (0x7FF00000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicCntVal_MIN          (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicCntVal_MAX          (2047) // 0x000007FF
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicCntVal_DEF          (0x0000010E)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicCntVal_HSH          (0x0B141E50)

  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicMode_OFF            (31)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicMode_WID            ( 1)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicMode_MSK            (0x80000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicMode_MIN            (0)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicMode_MAX            (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicMode_DEF            (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKCONTROL5_DeterministicMode_HSH            (0x011F1E50)

#define DDRCLKCH0_CR_DCCCLKTRAINSTATUS0_REG                            (0x00001E54)

  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS0_ClkDccDone_OFF               ( 0)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS0_ClkDccDone_WID               ( 3)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS0_ClkDccDone_MSK               (0x00000007)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS0_ClkDccDone_MIN               (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS0_ClkDccDone_MAX               (7) // 0x00000007
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS0_ClkDccDone_DEF               (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS0_ClkDccDone_HSH               (0x03001E54)

  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS0_Spare_OFF                    ( 3)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS0_Spare_WID                    (29)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS0_Spare_MSK                    (0xFFFFFFF8)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS0_Spare_MIN                    (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS0_Spare_MAX                    (536870911) // 0x1FFFFFFF
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS0_Spare_DEF                    (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS0_Spare_HSH                    (0x1D031E54)

#define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_REG                            (0x00001E58)

  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Spare0_OFF                   ( 0)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Spare0_WID                   (10)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Spare0_MSK                   (0x000003FF)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Spare0_MIN                   (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Spare0_MAX                   (1023) // 0x000003FF
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Spare0_DEF                   (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Spare0_HSH                   (0x0A001E58)

  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_CntDone_OFF                  (10)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_CntDone_WID                  ( 1)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_CntDone_MSK                  (0x00000400)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_CntDone_MIN                  (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_CntDone_MAX                  (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_CntDone_DEF                  (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_CntDone_HSH                  (0x010A1E58)

  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_OFF                (11)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_WID                (15)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_MSK                (0x03FFF800)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_MIN                (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_MAX                (32767) // 0x00007FFF
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_DEF                (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_HSH                (0x0F0B1E58)

  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Spare1_OFF                   (26)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Spare1_WID                   ( 1)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Spare1_MSK                   (0x04000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Spare1_MIN                   (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Spare1_MAX                   (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Spare1_DEF                   (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_Spare1_HSH                   (0x011A1E58)

  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_OFF          (27)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_WID          ( 5)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_MSK          (0xF8000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_MIN          (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_MAX          (31) // 0x0000001F
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_DEF          (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_HSH          (0x051B1E58)

#define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_REG                            (0x00001E5C)

  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_AuxCnt_OFF                   ( 0)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_AuxCnt_WID                   (16)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_AuxCnt_MSK                   (0x0000FFFF)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_AuxCnt_MIN                   (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_AuxCnt_MAX                   (65535) // 0x0000FFFF
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_AuxCnt_DEF                   (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_AuxCnt_HSH                   (0x10001E5C)

  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_OFF            (16)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_WID            ( 7)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_MSK            (0x007F0000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_MIN            (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_MAX            (127) // 0x0000007F
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_DEF            (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_HSH            (0x07101E5C)

  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_VTCompOffset_OFF             (23)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_VTCompOffset_WID             ( 7)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_VTCompOffset_MSK             (0x3F800000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_VTCompOffset_MIN             (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_VTCompOffset_MAX             (127) // 0x0000007F
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_VTCompOffset_DEF             (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_VTCompOffset_HSH             (0x07171E5C)

  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_Spare_OFF                    (30)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_Spare_WID                    ( 1)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_Spare_MSK                    (0x40000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_Spare_MIN                    (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_Spare_MAX                    (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_Spare_DEF                    (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_Spare_HSH                    (0x011E1E5C)

  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_CRVALID_OFF                  (31)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_CRVALID_WID                  ( 1)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_CRVALID_MSK                  (0x80000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_CRVALID_MIN                  (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_CRVALID_MAX                  (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_CRVALID_DEF                  (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINSTATUS2_CRVALID_HSH                  (0x011F1E5C)

#define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_REG                          (0x00001E60)

  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_OFF         ( 0)
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_WID         (11)
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_MSK         (0x000007FF)
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_MIN         (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_MAX         (2047) // 0x000007FF
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_DEF         (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_HSH         (0x0B001E60)

  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_OFF         (11)
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_WID         (17)
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_MSK         (0x0FFFF800)
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_MIN         (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_MAX         (131071) // 0x0001FFFF
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_DEF         (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_HSH         (0x110B1E60)

  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_Spare_OFF                  (28)
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_Spare_WID                  ( 4)
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_Spare_MSK                  (0xF0000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_Spare_MIN                  (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_Spare_MAX                  (15) // 0x0000000F
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_Spare_DEF                  (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINERRSTATUS_Spare_HSH                  (0x041C1E60)

#define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_REG                           (0x00001E64)

  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_OFF       ( 0)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_WID       ( 6)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_MSK       (0x0000003F)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_MIN       (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_MAX       (63) // 0x0000003F
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_DEF       (0x00000020)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_HSH       (0x06001E64)

  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_OFF       ( 6)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_WID       ( 6)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_MSK       (0x00000FC0)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_MIN       (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_MAX       (63) // 0x0000003F
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_DEF       (0x00000020)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_HSH       (0x06061E64)

  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_OFF       (12)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_WID       ( 6)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_MSK       (0x0003F000)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_MIN       (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_MAX       (63) // 0x0000003F
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_DEF       (0x00000020)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_HSH       (0x060C1E64)

  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_OFF       (18)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_WID       ( 6)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_MSK       (0x00FC0000)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_MIN       (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_MAX       (63) // 0x0000003F
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_DEF       (0x00000020)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_HSH       (0x06121E64)

  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_OFF       (24)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_WID       ( 7)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_MSK       (0x7F000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_MIN       (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_MAX       (127) // 0x0000007F
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_DEF       (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_HSH       (0x07181E64)

  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_CRVALID_OFF                 (31)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_CRVALID_WID                 ( 1)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_CRVALID_MSK                 (0x80000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_CRVALID_MIN                 (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_CRVALID_MAX                 (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_CRVALID_DEF                 (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINREPLICA0_CRVALID_HSH                 (0x011F1E64)

#define DDRCLKCH0_CR_DCCCLKTRAINVAL0_REG                               (0x00001E68)

  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Clk0DccVal_OFF                  ( 0)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Clk0DccVal_WID                  ( 6)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Clk0DccVal_MSK                  (0x0000003F)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Clk0DccVal_MIN                  (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Clk0DccVal_MAX                  (63) // 0x0000003F
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Clk0DccVal_DEF                  (0x00000020)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Clk0DccVal_HSH                  (0x06001E68)

  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Clk1DccVal_OFF                  ( 6)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Clk1DccVal_WID                  ( 6)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Clk1DccVal_MSK                  (0x00000FC0)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Clk1DccVal_MIN                  (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Clk1DccVal_MAX                  (63) // 0x0000003F
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Clk1DccVal_DEF                  (0x00000020)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Clk1DccVal_HSH                  (0x06061E68)

  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Spare_OFF                       (12)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Spare_WID                       (17)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Spare_MSK                       (0x1FFFF000)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Spare_MIN                       (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Spare_MAX                       (131071) // 0x0001FFFF
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Spare_DEF                       (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Spare_HSH                       (0x110C1E68)

  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_CRVALID_OFF                     (29)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_CRVALID_WID                     ( 1)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_CRVALID_MSK                     (0x20000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_CRVALID_MIN                     (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_CRVALID_MAX                     (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_CRVALID_DEF                     (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_CRVALID_HSH                     (0x011D1E68)

  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_OFF               (30)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_WID               ( 2)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_MSK               (0xC0000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_MIN               (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_MAX               (3) // 0x00000003
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_DEF               (0x00000001)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_HSH               (0x021E1E68)

#define DDRCLKCH0_CR_DCCCLKTRAINVAL1_REG                               (0x00001E6C)

  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_OFF         ( 0)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_WID         ( 6)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_MSK         (0x0000003F)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_MIN         (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_MAX         (63) // 0x0000003F
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_DEF         (0x00000020)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_HSH         (0x06001E6C)

  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_Spare_OFF                       ( 6)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_Spare_WID                       (20)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_Spare_MSK                       (0x03FFFFC0)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_Spare_MIN                       (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_Spare_MAX                       (1048575) // 0x000FFFFF
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_Spare_DEF                       (0x00000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_Spare_HSH                       (0x14061E6C)

  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_OFF        (26)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_WID        ( 3)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_MSK        (0x1C000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_MIN        (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_MAX        (7) // 0x00000007
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_DEF        (0x00000005)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_HSH        (0x031A1E6C)

  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_OFF     (29)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_WID     ( 1)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_MSK     (0x20000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_MIN     (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_MAX     (1) // 0x00000001
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_DEF     (0x00000001)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_HSH     (0x011D1E6C)

  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_RepDccAipCb_OFF                 (30)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_RepDccAipCb_WID                 ( 2)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_RepDccAipCb_MSK                 (0xC0000000)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_RepDccAipCb_MIN                 (0)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_RepDccAipCb_MAX                 (3) // 0x00000003
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_RepDccAipCb_DEF                 (0x00000001)
  #define DDRCLKCH0_CR_DCCCLKTRAINVAL1_RepDccAipCb_HSH                 (0x021E1E6C)

#define DDRCLKCH0_CR_DDRCRCLKTCOCONTROL0_REG                           (0x00001E70)

  #define DDRCLKCH0_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_OFF              ( 0)
  #define DDRCLKCH0_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_WID              ( 6)
  #define DDRCLKCH0_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_MSK              (0x0000003F)
  #define DDRCLKCH0_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_MIN              (0)
  #define DDRCLKCH0_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_MAX              (63) // 0x0000003F
  #define DDRCLKCH0_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_DEF              (0x00000020)
  #define DDRCLKCH0_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_HSH              (0x06001E70)

  #define DDRCLKCH0_CR_DDRCRCLKTCOCONTROL0_Spare_OFF                   ( 6)
  #define DDRCLKCH0_CR_DDRCRCLKTCOCONTROL0_Spare_WID                   (26)
  #define DDRCLKCH0_CR_DDRCRCLKTCOCONTROL0_Spare_MSK                   (0xFFFFFFC0)
  #define DDRCLKCH0_CR_DDRCRCLKTCOCONTROL0_Spare_MIN                   (0)
  #define DDRCLKCH0_CR_DDRCRCLKTCOCONTROL0_Spare_MAX                   (67108863) // 0x03FFFFFF
  #define DDRCLKCH0_CR_DDRCRCLKTCOCONTROL0_Spare_DEF                   (0x00000000)
  #define DDRCLKCH0_CR_DDRCRCLKTCOCONTROL0_Spare_HSH                   (0x1A061E70)

#define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_REG                             (0x00001E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_OFF                 ( 0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_WID                 ( 8)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_MSK                 (0x000000FF)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_MIN                 (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_MAX                 (255) // 0x000000FF
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_DEF                 (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CtlCkTxEn_HSH                 (0x08001E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_PiClkEn_OFF                   ( 8)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_PiClkEn_WID                   ( 4)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_PiClkEn_MSK                   (0x00000F00)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_PiClkEn_MIN                   (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_PiClkEn_MAX                   (15) // 0x0000000F
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_PiClkEn_DEF                   (0x0000000F)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_PiClkEn_HSH                   (0x04081E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_OFF        (12)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_WID        ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_MSK        (0x00001000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_MIN        (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_MAX        (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_DEF        (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_DdrCtlCkeSlwDlyByp_HSH        (0x010C1E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_OFF       (13)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_WID       ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_MSK       (0x00002000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_MIN       (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_MAX       (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_DEF       (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_cs_all_clk_gate_dis_HSH       (0x010D1E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_OFF      (14)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_WID      ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_MSK      (0x00004000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_MIN      (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_MAX      (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_DEF      (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsClkGateDis_in_idle_HSH      (0x010E1E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_OFF             (15)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_WID             ( 2)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_MSK             (0x00018000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_MIN             (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_MAX             (3) // 0x00000003
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_DEF             (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsPiClkGateEn_HSH             (0x020F1E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_OFF          (17)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_WID          ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_MSK          (0x00020000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_MIN          (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_MAX          (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_DEF          (0x00000001)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_1_HSH          (0x01111E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_OFF          (18)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_WID          ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_MSK          (0x00040000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_MIN          (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_MAX          (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_DEF          (0x00000001)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_ODT_0_HSH          (0x01121E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_OFF            (19)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_WID            ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_MSK            (0x00080000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_MIN            (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_MAX            (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_DEF            (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_3_HSH            (0x01131E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_OFF            (20)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_WID            ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_MSK            (0x00100000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_MIN            (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_MAX            (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_DEF            (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_2_HSH            (0x01141E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_OFF            (21)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_WID            ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_MSK            (0x00200000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_MIN            (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_MAX            (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_DEF            (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_1_HSH            (0x01151E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_OFF            (22)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_WID            ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_MSK            (0x00400000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_MIN            (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_MAX            (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_DEF            (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CsOdtForCS_N_0_HSH            (0x01161E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Gear1_OFF                     (23)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Gear1_WID                     ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Gear1_MSK                     (0x00800000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Gear1_MIN                     (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Gear1_MAX                     (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Gear1_DEF                     (0x00000001)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Gear1_HSH                     (0x01171E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_OFF         (24)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_WID         ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_MSK         (0x01000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_MIN         (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_MAX         (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_DEF         (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_lp4xvoltageselect_HSH         (0x01181E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_OFF        (25)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_WID        ( 2)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_MSK        (0x06000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_MIN        (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_MAX        (3) // 0x00000003
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_DEF        (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_xover_mindelay_ctl_HSH        (0x02191E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_OFF          (27)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_WID          ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_MSK          (0x08000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_MIN          (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_MAX          (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_DEF          (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_ClkSlewDlyByPass_HSH          (0x011B1E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_OFF    (28)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_WID    ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_MSK    (0x10000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_MIN    (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_MAX    (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_DEF    (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_CtlCriClkGateEnGvBlock_HSH    (0x011C1E80)

  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Spare_OFF                     (29)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Spare_WID                     ( 3)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Spare_MSK                     (0xE0000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Spare_MIN                     (0)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Spare_MAX                     (7) // 0x00000007
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Spare_DEF                     (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLRANKSUSED_Spare_HSH                     (0x031D1E80)

#define DDRCTLCH1_CR_DDRCRCTLCOMP_REG                                  (0x00001E90)

  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Scomp_OFF                          ( 0)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Scomp_WID                          ( 6)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Scomp_MSK                          (0x0000003F)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Scomp_MIN                          (0)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Scomp_MAX                          (63) // 0x0000003F
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Scomp_DEF                          (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Scomp_HSH                          (0x06001E90)

  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_OFF                     ( 6)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_WID                     ( 6)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_MSK                     (0x00000FC0)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_MIN                     (0)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_DEF                     (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvUp_HSH                     (0x06061E90)

  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_OFF                   (12)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_WID                   ( 6)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_MSK                   (0x0003F000)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_MIN                   (0)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_DEF                   (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_RcompDrvDown_HSH                   (0x060C1E90)

  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Spare_OFF                          (18)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Spare_WID                          (14)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Spare_MSK                          (0xFFFC0000)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Spare_MIN                          (0)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Spare_MAX                          (16383) // 0x00003FFF
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Spare_DEF                          (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCOMP_Spare_HSH                          (0x0E121E90)

#define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_REG                            (0x00001E94)

  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_OFF              ( 0)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_WID              ( 5)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MSK              (0x0000001F)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MIN              (-16)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_MAX              (15) // 0x0000000F
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_DEF              (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_ScompOffset_HSH              (0x85001E94)

  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_OFF         ( 5)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_WID         ( 4)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MSK         (0x000001E0)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MIN         (-8)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_MAX         (7) // 0x00000007
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_DEF         (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvUpOffset_HSH         (0x84051E94)

  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_OFF       ( 9)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_WID       ( 4)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MSK       (0x00001E00)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MIN       (-8)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_MAX       (7) // 0x00000007
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_DEF       (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_RcompDrvDownOffset_HSH       (0x84091E94)

  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_OFF                    (13)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_WID                    (19)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_MSK                    (0xFFFFE000)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_MIN                    (0)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_MAX                    (524287) // 0x0007FFFF
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_DEF                    (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCOMPOFFSET_Spare_HSH                    (0x130D1E94)

#define DDRCTLCH1_CR_DDRCRCTLPICODING_REG                              (0x00001E98)

  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_OFF                 ( 0)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_WID                 ( 7)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_MSK                 (0x0000007F)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_MIN                 (0)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_MAX                 (127) // 0x0000007F
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_DEF                 (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode0_HSH                 (0x07001E98)

  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_OFF                 ( 7)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_WID                 ( 7)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_MSK                 (0x00003F80)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_MIN                 (0)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_MAX                 (127) // 0x0000007F
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_DEF                 (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode1_HSH                 (0x07071E98)

  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_OFF                 (14)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_WID                 ( 7)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_MSK                 (0x001FC000)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_MIN                 (0)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_MAX                 (127) // 0x0000007F
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_DEF                 (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode2_HSH                 (0x070E1E98)

  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_OFF                 (21)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_WID                 ( 7)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_MSK                 (0x0FE00000)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_MIN                 (0)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_MAX                 (127) // 0x0000007F
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_DEF                 (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlPiCode3_HSH                 (0x07151E98)

  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_OFF             (28)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_WID             ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_MSK             (0x10000000)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_MIN             (0)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_MAX             (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_DEF             (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_CtlXoverEnable_HSH             (0x011C1E98)

  #define DDRCTLCH1_CR_DDRCRCTLPICODING_Spare_OFF                      (29)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_Spare_WID                      ( 3)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_Spare_MSK                      (0xE0000000)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_Spare_MIN                      (0)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_Spare_MAX                      (7) // 0x00000007
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_Spare_DEF                      (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLPICODING_Spare_HSH                      (0x031D1E98)

#define DDRCTLCH1_CR_DDRCRCTLCONTROLS_REG                              (0x00001E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RefPi_OFF                      ( 0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RefPi_WID                      ( 4)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RefPi_MSK                      (0x0000000F)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RefPi_MIN                      (-8)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RefPi_MAX                      (7) // 0x00000007
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RefPi_DEF                      (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RefPi_HSH                      (0x84001E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllMask_OFF                    ( 4)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllMask_WID                    ( 2)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllMask_MSK                    (0x00000030)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllMask_MIN                    (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllMask_MAX                    (3) // 0x00000003
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllMask_DEF                    (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllMask_HSH                    (0x02041E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_ClkGateDisable_OFF             ( 6)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_ClkGateDisable_WID             ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_ClkGateDisable_MSK             (0x00000040)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_ClkGateDisable_MIN             (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_ClkGateDisable_MAX             (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_ClkGateDisable_DEF             (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_ClkGateDisable_HSH             (0x01061E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_TxOn_OFF                       ( 7)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_TxOn_WID                       ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_TxOn_MSK                       (0x00000080)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_TxOn_MIN                       (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_TxOn_MAX                       (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_TxOn_DEF                       (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_TxOn_HSH                       (0x01071E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_OFF                   ( 8)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_WID                   ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_MSK                   (0x00000100)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_MIN                   (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_MAX                   (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_DEF                   (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IntClkOn_HSH                   (0x01081E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_OFF                   ( 9)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_WID                   ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_MSK                   (0x00000200)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_MIN                   (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_MAX                   (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_DEF                   (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RepClkOn_HSH                   (0x01091E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IolbOrMisr_OFF                 (10)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IolbOrMisr_WID                 ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IolbOrMisr_MSK                 (0x00000400)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IolbOrMisr_MIN                 (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IolbOrMisr_MAX                 (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IolbOrMisr_DEF                 (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IolbOrMisr_HSH                 (0x010A1E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IOLBHold_OFF                   (11)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IOLBHold_WID                   ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IOLBHold_MSK                   (0x00000800)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IOLBHold_MIN                   (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IOLBHold_MAX                   (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IOLBHold_DEF                   (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_IOLBHold_HSH                   (0x010B1E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_OFF                    (12)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_WID                    ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_MSK                    (0x00001000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_MIN                    (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_MAX                    (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_DEF                    (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_OdtMode_HSH                    (0x010C1E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_OFF                    (13)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_WID                    ( 2)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_MSK                    (0x00006000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_MIN                    (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_MAX                    (3) // 0x00000003
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_DEF                    (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CmdTxEq_HSH                    (0x020D1E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_OFF             (15)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_WID             ( 2)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MSK             (0x00018000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MIN             (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_MAX             (3) // 0x00000003
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_DEF             (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_EarlyWeakDrive_HSH             (0x020F1E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_OFF                    (17)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_WID                    ( 2)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_MSK                    (0x00060000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_MIN                    (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_MAX                    (3) // 0x00000003
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_DEF                    (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlTxEq_HSH                    (0x02111E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_OFF                   (19)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_WID                   ( 2)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MSK                   (0x00180000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MIN                   (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_MAX                   (3) // 0x00000003
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_DEF                   (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CtlSRDrv_HSH                   (0x02131E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RxVref_OFF                     (21)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RxVref_WID                     ( 6)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RxVref_MSK                     (0x07E00000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RxVref_MIN                     (-32)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RxVref_MAX                     (31) // 0x0000001F
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RxVref_DEF                     (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_RxVref_HSH                     (0x86151E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_OFF                   (27)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_WID                   ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_MSK                   (0x08000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_MIN                   (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_MAX                   (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_DEF                   (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_VccddqHi_HSH                   (0x011B1E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_OFF                (28)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_WID                ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_MSK                (0x10000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_MIN                (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_MAX                (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_DEF                (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_DllWeakLock_HSH                (0x011C1E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CMD_Rate_OFF                   (29)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CMD_Rate_WID                   ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CMD_Rate_MSK                   (0x20000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CMD_Rate_MIN                   (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CMD_Rate_MAX                   (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CMD_Rate_DEF                   (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_CMD_Rate_HSH                   (0x011D1E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_OFF                (30)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_WID                ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MSK                (0x40000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MIN                (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_MAX                (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_DEF                (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_LaDrvEnOvrd_HSH                (0x011E1E9C)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_OFF            (31)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_WID            ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_MSK            (0x80000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_MIN            (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_MAX            (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_DEF            (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS_ma3_ma4_par_dis_HSH            (0x011F1E9C)

#define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_REG                             (0x00001EA0)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_RxVref_OFF                    ( 0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_RxVref_WID                    ( 8)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_RxVref_MSK                    (0x000000FF)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_RxVref_MIN                    (-128)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_RxVref_MAX                    (127) // 0x0000007F
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_RxVref_DEF                    (0x00000060)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_RxVref_HSH                    (0x88001EA0)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_OFF            ( 8)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_WID            (18)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_MSK            (0x03FFFF00)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_MIN            (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_MAX            (262143) // 0x0003FFFF
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_DEF            (0x00010458)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_MapCkeForScOdt_HSH            (0x12081EA0)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_OFF               (26)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_WID               ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_MSK               (0x04000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_MIN               (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_MAX               (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_DEF               (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CMDLowsupEn_HSH               (0x011A1EA0)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CKELowsupEn_OFF               (27)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CKELowsupEn_WID               ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CKELowsupEn_MSK               (0x08000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CKELowsupEn_MIN               (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CKELowsupEn_MAX               (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CKELowsupEn_DEF               (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CKELowsupEn_HSH               (0x011B1EA0)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_OFF               (28)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_WID               ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_MSK               (0x10000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_MIN               (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_MAX               (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_DEF               (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CTLLowsupEn_HSH               (0x011C1EA0)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_OFF               (29)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_WID               ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_MSK               (0x20000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_MIN               (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_MAX               (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_DEF               (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_CLKLowsupEn_HSH               (0x011D1EA0)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_OFF         (30)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_WID         ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_MSK         (0x40000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_MIN         (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_MAX         (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_DEF         (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_en_sr_mode_to_cke_HSH         (0x011E1EA0)

  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_OFF        (31)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_WID        ( 1)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_MSK        (0x80000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_MIN        (0)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_MAX        (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_DEF        (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLCONTROLS1_c3segsel_b_for_cke_HSH        (0x011F1EA0)

#define DDRCTLCH1_CR_DDRCRLOOPBACKFEEDBACK_REG                         (0x00001EA4)

  #define DDRCTLCH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_OFF     ( 0)
  #define DDRCTLCH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_WID     (10)
  #define DDRCTLCH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MSK     (0x000003FF)
  #define DDRCTLCH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MIN     (0)
  #define DDRCTLCH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_MAX     (1023) // 0x000003FF
  #define DDRCTLCH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_DEF     (0x00000000)
  #define DDRCTLCH1_CR_DDRCRLOOPBACKFEEDBACK_datatrainfeedback_HSH     (0x0A001EA4)

  #define DDRCTLCH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_OFF                 (10)
  #define DDRCTLCH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_WID                 (22)
  #define DDRCTLCH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_MSK                 (0xFFFFFC00)
  #define DDRCTLCH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_MIN                 (0)
  #define DDRCTLCH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_MAX                 (4194303) // 0x003FFFFF
  #define DDRCTLCH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_DEF                 (0x00000000)
  #define DDRCTLCH1_CR_DDRCRLOOPBACKFEEDBACK_Spare_HSH                 (0x160A1EA4)

#define DDRCTLCH1_CR_DDRCMDMISR_REG                                    (0x00001EA8)

  #define DDRCTLCH1_CR_DDRCMDMISR_shift_16_OFF                         ( 0)
  #define DDRCTLCH1_CR_DDRCMDMISR_shift_16_WID                         ( 1)
  #define DDRCTLCH1_CR_DDRCMDMISR_shift_16_MSK                         (0x00000001)
  #define DDRCTLCH1_CR_DDRCMDMISR_shift_16_MIN                         (0)
  #define DDRCTLCH1_CR_DDRCMDMISR_shift_16_MAX                         (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCMDMISR_shift_16_DEF                         (0x00000000)
  #define DDRCTLCH1_CR_DDRCMDMISR_shift_16_HSH                         (0x01001EA8)

  #define DDRCTLCH1_CR_DDRCMDMISR_clken_pulse_mode_OFF                 ( 1)
  #define DDRCTLCH1_CR_DDRCMDMISR_clken_pulse_mode_WID                 ( 1)
  #define DDRCTLCH1_CR_DDRCMDMISR_clken_pulse_mode_MSK                 (0x00000002)
  #define DDRCTLCH1_CR_DDRCMDMISR_clken_pulse_mode_MIN                 (0)
  #define DDRCTLCH1_CR_DDRCMDMISR_clken_pulse_mode_MAX                 (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCMDMISR_clken_pulse_mode_DEF                 (0x00000000)
  #define DDRCTLCH1_CR_DDRCMDMISR_clken_pulse_mode_HSH                 (0x01011EA8)

  #define DDRCTLCH1_CR_DDRCMDMISR_reg_clken_mode_OFF                   ( 2)
  #define DDRCTLCH1_CR_DDRCMDMISR_reg_clken_mode_WID                   ( 1)
  #define DDRCTLCH1_CR_DDRCMDMISR_reg_clken_mode_MSK                   (0x00000004)
  #define DDRCTLCH1_CR_DDRCMDMISR_reg_clken_mode_MIN                   (0)
  #define DDRCTLCH1_CR_DDRCMDMISR_reg_clken_mode_MAX                   (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCMDMISR_reg_clken_mode_DEF                   (0x00000000)
  #define DDRCTLCH1_CR_DDRCMDMISR_reg_clken_mode_HSH                   (0x01021EA8)

  #define DDRCTLCH1_CR_DDRCMDMISR_reg_clken_OFF                        ( 3)
  #define DDRCTLCH1_CR_DDRCMDMISR_reg_clken_WID                        ( 1)
  #define DDRCTLCH1_CR_DDRCMDMISR_reg_clken_MSK                        (0x00000008)
  #define DDRCTLCH1_CR_DDRCMDMISR_reg_clken_MIN                        (0)
  #define DDRCTLCH1_CR_DDRCMDMISR_reg_clken_MAX                        (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCMDMISR_reg_clken_DEF                        (0x00000000)
  #define DDRCTLCH1_CR_DDRCMDMISR_reg_clken_HSH                        (0x01031EA8)

  #define DDRCTLCH1_CR_DDRCMDMISR_feedback_en_OFF                      ( 4)
  #define DDRCTLCH1_CR_DDRCMDMISR_feedback_en_WID                      ( 1)
  #define DDRCTLCH1_CR_DDRCMDMISR_feedback_en_MSK                      (0x00000010)
  #define DDRCTLCH1_CR_DDRCMDMISR_feedback_en_MIN                      (0)
  #define DDRCTLCH1_CR_DDRCMDMISR_feedback_en_MAX                      (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCMDMISR_feedback_en_DEF                      (0x00000000)
  #define DDRCTLCH1_CR_DDRCMDMISR_feedback_en_HSH                      (0x01041EA8)

  #define DDRCTLCH1_CR_DDRCMDMISR_event_mode_OFF                       ( 5)
  #define DDRCTLCH1_CR_DDRCMDMISR_event_mode_WID                       ( 1)
  #define DDRCTLCH1_CR_DDRCMDMISR_event_mode_MSK                       (0x00000020)
  #define DDRCTLCH1_CR_DDRCMDMISR_event_mode_MIN                       (0)
  #define DDRCTLCH1_CR_DDRCMDMISR_event_mode_MAX                       (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCMDMISR_event_mode_DEF                       (0x00000000)
  #define DDRCTLCH1_CR_DDRCMDMISR_event_mode_HSH                       (0x01051EA8)

  #define DDRCTLCH1_CR_DDRCMDMISR_lfsr_reset_OFF                       ( 6)
  #define DDRCTLCH1_CR_DDRCMDMISR_lfsr_reset_WID                       ( 1)
  #define DDRCTLCH1_CR_DDRCMDMISR_lfsr_reset_MSK                       (0x00000040)
  #define DDRCTLCH1_CR_DDRCMDMISR_lfsr_reset_MIN                       (0)
  #define DDRCTLCH1_CR_DDRCMDMISR_lfsr_reset_MAX                       (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCMDMISR_lfsr_reset_DEF                       (0x00000000)
  #define DDRCTLCH1_CR_DDRCMDMISR_lfsr_reset_HSH                       (0x01061EA8)

  #define DDRCTLCH1_CR_DDRCMDMISR_sdo_en_OFF                           ( 7)
  #define DDRCTLCH1_CR_DDRCMDMISR_sdo_en_WID                           ( 1)
  #define DDRCTLCH1_CR_DDRCMDMISR_sdo_en_MSK                           (0x00000080)
  #define DDRCTLCH1_CR_DDRCMDMISR_sdo_en_MIN                           (0)
  #define DDRCTLCH1_CR_DDRCMDMISR_sdo_en_MAX                           (1) // 0x00000001
  #define DDRCTLCH1_CR_DDRCMDMISR_sdo_en_DEF                           (0x00000000)
  #define DDRCTLCH1_CR_DDRCMDMISR_sdo_en_HSH                           (0x01071EA8)

  #define DDRCTLCH1_CR_DDRCMDMISR_reserved0_OFF                        ( 8)
  #define DDRCTLCH1_CR_DDRCMDMISR_reserved0_WID                        ( 8)
  #define DDRCTLCH1_CR_DDRCMDMISR_reserved0_MSK                        (0x0000FF00)
  #define DDRCTLCH1_CR_DDRCMDMISR_reserved0_MIN                        (0)
  #define DDRCTLCH1_CR_DDRCMDMISR_reserved0_MAX                        (255) // 0x000000FF
  #define DDRCTLCH1_CR_DDRCMDMISR_reserved0_DEF                        (0x00000000)
  #define DDRCTLCH1_CR_DDRCMDMISR_reserved0_HSH                        (0x08081EA8)

  #define DDRCTLCH1_CR_DDRCMDMISR_cr_rd_data_OFF                       (16)
  #define DDRCTLCH1_CR_DDRCMDMISR_cr_rd_data_WID                       (16)
  #define DDRCTLCH1_CR_DDRCMDMISR_cr_rd_data_MSK                       (0xFFFF0000)
  #define DDRCTLCH1_CR_DDRCMDMISR_cr_rd_data_MIN                       (0)
  #define DDRCTLCH1_CR_DDRCMDMISR_cr_rd_data_MAX                       (65535) // 0x0000FFFF
  #define DDRCTLCH1_CR_DDRCMDMISR_cr_rd_data_DEF                       (0x00000000)
  #define DDRCTLCH1_CR_DDRCMDMISR_cr_rd_data_HSH                       (0x10101EA8)

#define DDRCTLCH1_CR_DDRCRCTLTCOCONTROL0_REG                           (0x00001EAC)

  #define DDRCTLCH1_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_OFF              ( 0)
  #define DDRCTLCH1_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_WID              ( 6)
  #define DDRCTLCH1_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_MSK              (0x0000003F)
  #define DDRCTLCH1_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_MIN              (0)
  #define DDRCTLCH1_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_MAX              (63) // 0x0000003F
  #define DDRCTLCH1_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_DEF              (0x00000020)
  #define DDRCTLCH1_CR_DDRCRCTLTCOCONTROL0_CtlTcoComp_HSH              (0x06001EAC)

  #define DDRCTLCH1_CR_DDRCRCTLTCOCONTROL0_Spare_OFF                   ( 6)
  #define DDRCTLCH1_CR_DDRCRCTLTCOCONTROL0_Spare_WID                   (26)
  #define DDRCTLCH1_CR_DDRCRCTLTCOCONTROL0_Spare_MSK                   (0xFFFFFFC0)
  #define DDRCTLCH1_CR_DDRCRCTLTCOCONTROL0_Spare_MIN                   (0)
  #define DDRCTLCH1_CR_DDRCRCTLTCOCONTROL0_Spare_MAX                   (67108863) // 0x03FFFFFF
  #define DDRCTLCH1_CR_DDRCRCTLTCOCONTROL0_Spare_DEF                   (0x00000000)
  #define DDRCTLCH1_CR_DDRCRCTLTCOCONTROL0_Spare_HSH                   (0x1A061EAC)

#define DDRCLKCH1_CR_DDRCRCLKCOMP_REG                                  (0x00001EB0)

  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Scomp_OFF                          ( 0)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Scomp_WID                          ( 5)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Scomp_MSK                          (0x0000001F)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Scomp_MIN                          (0)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Scomp_MAX                          (31) // 0x0000001F
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Scomp_DEF                          (0x00000000)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Scomp_HSH                          (0x05001EB0)

  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvUp_OFF                     ( 5)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvUp_WID                     ( 6)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvUp_MSK                     (0x000007E0)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvUp_MIN                     (0)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvUp_DEF                     (0x00000000)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvUp_HSH                     (0x06051EB0)

  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvDown_OFF                   (11)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvDown_WID                   ( 6)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvDown_MSK                   (0x0001F800)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvDown_MIN                   (0)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvDown_DEF                   (0x00000000)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_RcompDrvDown_HSH                   (0x060B1EB0)

  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Spare_OFF                          (17)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Spare_WID                          (15)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Spare_MSK                          (0xFFFE0000)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Spare_MIN                          (0)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Spare_MAX                          (32767) // 0x00007FFF
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Spare_DEF                          (0x00000000)
  #define DDRCLKCH1_CR_DDRCRCLKCOMP_Spare_HSH                          (0x0F111EB0)

#define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_REG                            (0x00001EB4)

  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_OFF              ( 0)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_WID              ( 4)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MSK              (0x0000000F)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MIN              (-8)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_MAX              (7) // 0x00000007
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_DEF              (0x00000000)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ScompOffset_HSH              (0x84001EB4)

  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_OFF         ( 4)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_WID         ( 4)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MSK         (0x000000F0)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MIN         (-8)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_MAX         (7) // 0x00000007
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_DEF         (0x00000000)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvUpOffset_HSH         (0x84041EB4)

  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_OFF       ( 8)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_WID       ( 4)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MSK       (0x00000F00)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MIN       (-8)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_MAX       (7) // 0x00000007
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_DEF       (0x00000000)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_RcompDrvDownOffset_HSH       (0x84081EB4)

  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_OFF    (12)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_WID    ( 1)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_MSK    (0x00001000)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_MIN    (0)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_MAX    (1) // 0x00000001
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_DEF    (0x00000000)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_ClkCompOnTheFlyUpdtEn_HSH    (0x010C1EB4)

  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_Spare_OFF                    (13)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_Spare_WID                    (19)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_Spare_MSK                    (0xFFFFE000)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_Spare_MIN                    (0)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_Spare_MAX                    (524287) // 0x0007FFFF
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_Spare_DEF                    (0x00000000)
  #define DDRCLKCH1_CR_DDRCRCLKCOMPOFFSET_Spare_HSH                    (0x130D1EB4)

#define DDRCLKCH1_CR_DDR4CRBSCANDATA_REG                               (0x00001EB8)

  #define DDRCLKCH1_CR_DDR4CRBSCANDATA_Spare_OFF                       ( 0)
  #define DDRCLKCH1_CR_DDR4CRBSCANDATA_Spare_WID                       (32)
  #define DDRCLKCH1_CR_DDR4CRBSCANDATA_Spare_MSK                       (0xFFFFFFFF)
  #define DDRCLKCH1_CR_DDR4CRBSCANDATA_Spare_MIN                       (0)
  #define DDRCLKCH1_CR_DDR4CRBSCANDATA_Spare_MAX                       (4294967295) // 0xFFFFFFFF
  #define DDRCLKCH1_CR_DDR4CRBSCANDATA_Spare_DEF                       (0x00000000)
  #define DDRCLKCH1_CR_DDR4CRBSCANDATA_Spare_HSH                       (0x20001EB8)

#define DDRCLKCH1_CR_DCCCLKCONTROL0_REG                                (0x00001EBC)

  #define DDRCLKCH1_CR_DCCCLKCONTROL0_CRVALID_OFF                      ( 0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_CRVALID_WID                      ( 1)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_CRVALID_MSK                      (0x00000001)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_CRVALID_MIN                      (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_CRVALID_MAX                      (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_CRVALID_DEF                      (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_CRVALID_HSH                      (0x01001EBC)

  #define DDRCLKCH1_CR_DCCCLKCONTROL0_GVPointG2_OFF                    ( 1)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_GVPointG2_WID                    ( 2)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_GVPointG2_MSK                    (0x00000006)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_GVPointG2_MIN                    (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_GVPointG2_MAX                    (3) // 0x00000003
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_GVPointG2_DEF                    (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_GVPointG2_HSH                    (0x02011EBC)

  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ReplicaOffsetUse_OFF             ( 3)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ReplicaOffsetUse_WID             ( 1)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ReplicaOffsetUse_MSK             (0x00000008)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ReplicaOffsetUse_MIN             (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ReplicaOffsetUse_MAX             (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ReplicaOffsetUse_DEF             (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ReplicaOffsetUse_HSH             (0x01031EBC)

  #define DDRCLKCH1_CR_DCCCLKCONTROL0_VTCompOffsetUse_OFF              ( 4)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_VTCompOffsetUse_WID              ( 2)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_VTCompOffsetUse_MSK              (0x00000030)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_VTCompOffsetUse_MIN              (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_VTCompOffsetUse_MAX              (3) // 0x00000003
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_VTCompOffsetUse_DEF              (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_VTCompOffsetUse_HSH              (0x02041EBC)

  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ExtOffset_OFF                    ( 6)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ExtOffset_WID                    ( 7)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ExtOffset_MSK                    (0x00001FC0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ExtOffset_MIN                    (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ExtOffset_MAX                    (127) // 0x0000007F
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ExtOffset_DEF                    (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ExtOffset_HSH                    (0x07061EBC)

  #define DDRCLKCH1_CR_DCCCLKCONTROL0_BiasOffset_OFF                   (13)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_BiasOffset_WID                   (15)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_BiasOffset_MSK                   (0x0FFFE000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_BiasOffset_MIN                   (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_BiasOffset_MAX                   (32767) // 0x00007FFF
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_BiasOffset_DEF                   (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_BiasOffset_HSH                   (0x0F0D1EBC)

  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ActiveRanks_OFF                  (28)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ActiveRanks_WID                  ( 4)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ActiveRanks_MSK                  (0xF0000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ActiveRanks_MIN                  (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ActiveRanks_MAX                  (15) // 0x0000000F
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ActiveRanks_DEF                  (0x00000001)
  #define DDRCLKCH1_CR_DCCCLKCONTROL0_ActiveRanks_HSH                  (0x041C1EBC)

#define DDRCLKCH1_CR_DCCCLKCONTROL1_REG                                (0x00001EC0)

  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DccCodeOvrd_OFF                  ( 0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DccCodeOvrd_WID                  ( 6)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DccCodeOvrd_MSK                  (0x0000003F)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DccCodeOvrd_MIN                  (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DccCodeOvrd_MAX                  (63) // 0x0000003F
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DccCodeOvrd_DEF                  (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DccCodeOvrd_HSH                  (0x06001EC0)

  #define DDRCLKCH1_CR_DCCCLKCONTROL1_Rank0DccAipCb_OFF                ( 6)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_Rank0DccAipCb_WID                ( 2)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_Rank0DccAipCb_MSK                (0x000000C0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_Rank0DccAipCb_MIN                (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_Rank0DccAipCb_MAX                (3) // 0x00000003
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_Rank0DccAipCb_DEF                (0x00000001)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_Rank0DccAipCb_HSH                (0x02061EC0)

  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DccPtrOvrd_OFF                   ( 8)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DccPtrOvrd_WID                   ( 4)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DccPtrOvrd_MSK                   (0x00000F00)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DccPtrOvrd_MIN                   (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DccPtrOvrd_MAX                   (15) // 0x0000000F
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DccPtrOvrd_DEF                   (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DccPtrOvrd_HSH                   (0x04081EC0)

  #define DDRCLKCH1_CR_DCCCLKCONTROL1_RnkPtrOvrd_OFF                   (12)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_RnkPtrOvrd_WID                   ( 2)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_RnkPtrOvrd_MSK                   (0x00003000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_RnkPtrOvrd_MIN                   (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_RnkPtrOvrd_MAX                   (3) // 0x00000003
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_RnkPtrOvrd_DEF                   (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_RnkPtrOvrd_HSH                   (0x020C1EC0)

  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdDigEnOvrd_OFF                 (14)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdDigEnOvrd_WID                 ( 1)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdDigEnOvrd_MSK                 (0x00004000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdDigEnOvrd_MIN                 (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdDigEnOvrd_MAX                 (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdDigEnOvrd_DEF                 (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdDigEnOvrd_HSH                 (0x010E1EC0)

  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_OFF                 (15)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_WID                 ( 1)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_MSK                 (0x00008000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_MIN                 (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_MAX                 (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_DEF                 (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdAnaEnOvrd_HSH                 (0x010F1EC0)

  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdWindow_OFF                    (16)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdWindow_WID                    (15)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdWindow_MSK                    (0x7FFF0000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdWindow_MIN                    (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdWindow_MAX                    (32767) // 0x00007FFF
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdWindow_DEF                    (0x00000800)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_DcdWindow_HSH                    (0x0F101EC0)

  #define DDRCLKCH1_CR_DCCCLKCONTROL1_Spare_OFF                        (31)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_Spare_WID                        ( 1)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_Spare_MSK                        (0x80000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_Spare_MIN                        (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_Spare_MAX                        (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_Spare_DEF                        (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL1_Spare_HSH                        (0x011F1EC0)

#define DDRCLKCH1_CR_DCCCLKCONTROL2_REG                                (0x00001EC4)

  #define DDRCLKCH1_CR_DCCCLKCONTROL2_StartBinCode_OFF                 ( 0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_StartBinCode_WID                 ( 6)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_StartBinCode_MSK                 (0x0000003F)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_StartBinCode_MIN                 (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_StartBinCode_MAX                 (63) // 0x0000003F
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_StartBinCode_DEF                 (0x00000020)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_StartBinCode_HSH                 (0x06001EC4)

  #define DDRCLKCH1_CR_DCCCLKCONTROL2_CodePtrStartBit_OFF              ( 6)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_CodePtrStartBit_WID              ( 3)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_CodePtrStartBit_MSK              (0x000001C0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_CodePtrStartBit_MIN              (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_CodePtrStartBit_MAX              (7) // 0x00000007
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_CodePtrStartBit_DEF              (0x00000005)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_CodePtrStartBit_HSH              (0x03061EC4)

  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DccTrshOld_OFF                   ( 9)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DccTrshOld_WID                   (13)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DccTrshOld_MSK                   (0x003FFE00)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DccTrshOld_MIN                   (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DccTrshOld_MAX                   (8191) // 0x00001FFF
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DccTrshOld_DEF                   (0x00000008)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DccTrshOld_HSH                   (0x0D091EC4)

  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DcdCntsStartDiff_OFF             (22)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DcdCntsStartDiff_WID             ( 5)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DcdCntsStartDiff_MSK             (0x07C00000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DcdCntsStartDiff_MIN             (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DcdCntsStartDiff_MAX             (31) // 0x0000001F
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DcdCntsStartDiff_DEF             (0x00000003)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DcdCntsStartDiff_HSH             (0x05161EC4)

  #define DDRCLKCH1_CR_DCCCLKCONTROL2_ClkGateDisable_OFF               (27)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_ClkGateDisable_WID               ( 1)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_ClkGateDisable_MSK               (0x08000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_ClkGateDisable_MIN               (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_ClkGateDisable_MAX               (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_ClkGateDisable_DEF               (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_ClkGateDisable_HSH               (0x011B1EC4)

  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DccClkViewSelect0_OFF            (28)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DccClkViewSelect0_WID            ( 4)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DccClkViewSelect0_MSK            (0xF0000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DccClkViewSelect0_MIN            (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DccClkViewSelect0_MAX            (15) // 0x0000000F
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DccClkViewSelect0_DEF            (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL2_DccClkViewSelect0_HSH            (0x041C1EC4)

#define DDRCLKCH1_CR_DCCCLKCONTROL3_REG                                (0x00001EC8)

  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank0_OFF               ( 0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank0_WID               (11)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank0_MSK               (0x000007FF)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank0_MIN               (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank0_MAX               (2047) // 0x000007FF
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank0_DEF               (0x00000007)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank0_HSH               (0x0B001EC8)

  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank1_OFF               (11)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank1_WID               ( 9)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank1_MSK               (0x000FF800)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank1_MIN               (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank1_MAX               (511) // 0x000001FF
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank1_DEF               (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank1_HSH               (0x090B1EC8)

  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank2_OFF               (20)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank2_WID               ( 9)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank2_MSK               (0x1FF00000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank2_MIN               (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank2_MAX               (511) // 0x000001FF
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank2_DEF               (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_ActiveDccRank2_HSH               (0x09141EC8)

  #define DDRCLKCH1_CR_DCCCLKCONTROL3_clkdccupdateoldpath_OFF          (29)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_clkdccupdateoldpath_WID          ( 1)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_clkdccupdateoldpath_MSK          (0x20000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_clkdccupdateoldpath_MIN          (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_clkdccupdateoldpath_MAX          (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_clkdccupdateoldpath_DEF          (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_clkdccupdateoldpath_HSH          (0x011D1EC8)

  #define DDRCLKCH1_CR_DCCCLKCONTROL3_clkdcccfgbypass_OFF              (30)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_clkdcccfgbypass_WID              ( 1)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_clkdcccfgbypass_MSK              (0x40000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_clkdcccfgbypass_MIN              (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_clkdcccfgbypass_MAX              (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_clkdcccfgbypass_DEF              (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_clkdcccfgbypass_HSH              (0x011E1EC8)

  #define DDRCLKCH1_CR_DCCCLKCONTROL3_Spare_OFF                        (31)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_Spare_WID                        ( 1)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_Spare_MSK                        (0x80000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_Spare_MIN                        (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_Spare_MAX                        (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_Spare_DEF                        (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL3_Spare_HSH                        (0x011F1EC8)

#define DDRCLKCH1_CR_DCCCLKCONTROL4_REG                                (0x00001ECC)

  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ActiveDccRank3_OFF               ( 0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ActiveDccRank3_WID               ( 9)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ActiveDccRank3_MSK               (0x000001FF)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ActiveDccRank3_MIN               (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ActiveDccRank3_MAX               (511) // 0x000001FF
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ActiveDccRank3_DEF               (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ActiveDccRank3_HSH               (0x09001ECC)

  #define DDRCLKCH1_CR_DCCCLKCONTROL4_Spare_OFF                        ( 9)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_Spare_WID                        ( 1)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_Spare_MSK                        (0x00000200)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_Spare_MIN                        (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_Spare_MAX                        (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_Spare_DEF                        (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_Spare_HSH                        (0x01091ECC)

  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_OFF             (10)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_WID             ( 6)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_MSK             (0x0000FC00)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_MIN             (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_MAX             (63) // 0x0000003F
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_DEF             (0x00000020)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp0_HSH             (0x060A1ECC)

  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_OFF             (16)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_WID             ( 6)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_MSK             (0x003F0000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_MIN             (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_MAX             (63) // 0x0000003F
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_DEF             (0x00000020)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp1_HSH             (0x06101ECC)

  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_OFF             (22)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_WID             ( 6)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_MSK             (0x0FC00000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_MIN             (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_MAX             (63) // 0x0000003F
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_DEF             (0x00000020)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_ReplicaPrev_GVp2_HSH             (0x06161ECC)

  #define DDRCLKCH1_CR_DCCCLKCONTROL4_DccClkViewSelect1_OFF            (28)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_DccClkViewSelect1_WID            ( 4)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_DccClkViewSelect1_MSK            (0xF0000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_DccClkViewSelect1_MIN            (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_DccClkViewSelect1_MAX            (15) // 0x0000000F
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_DccClkViewSelect1_DEF            (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL4_DccClkViewSelect1_HSH            (0x041C1ECC)

#define DDRCLKCH1_CR_DCCCLKCONTROL5_REG                                (0x00001ED0)

  #define DDRCLKCH1_CR_DCCCLKCONTROL5_dccclkupdtstepsize_OFF           ( 0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_dccclkupdtstepsize_WID           ( 2)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_dccclkupdtstepsize_MSK           (0x00000003)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_dccclkupdtstepsize_MIN           (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_dccclkupdtstepsize_MAX           (3) // 0x00000003
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_dccclkupdtstepsize_DEF           (0x00000002)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_dccclkupdtstepsize_HSH           (0x02001ED0)

  #define DDRCLKCH1_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_OFF          ( 2)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_WID          ( 1)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_MSK          (0x00000004)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_MIN          (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_MAX          (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_DEF          (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_vtcompoffsetmsgwren_HSH          (0x01021ED0)

  #define DDRCLKCH1_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_OFF             ( 3)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_WID             ( 6)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_MSK             (0x000001F8)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_MIN             (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_MAX             (63) // 0x0000003F
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_DEF             (0x00000020)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_ReplicaPrev_GVp3_HSH             (0x06031ED0)

  #define DDRCLKCH1_CR_DCCCLKCONTROL5_BubbleCntVal_OFF                 ( 9)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_BubbleCntVal_WID                 ( 5)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_BubbleCntVal_MSK                 (0x00003E00)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_BubbleCntVal_MIN                 (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_BubbleCntVal_MAX                 (31) // 0x0000001F
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_BubbleCntVal_DEF                 (0x0000000B)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_BubbleCntVal_HSH                 (0x05091ED0)

  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicSyncVal_OFF         (14)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicSyncVal_WID         ( 6)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicSyncVal_MSK         (0x000FC000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicSyncVal_MIN         (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicSyncVal_MAX         (63) // 0x0000003F
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicSyncVal_DEF         (0x00000020)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicSyncVal_HSH         (0x060E1ED0)

  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicCntVal_OFF          (20)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicCntVal_WID          (11)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicCntVal_MSK          (0x7FF00000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicCntVal_MIN          (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicCntVal_MAX          (2047) // 0x000007FF
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicCntVal_DEF          (0x0000010E)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicCntVal_HSH          (0x0B141ED0)

  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicMode_OFF            (31)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicMode_WID            ( 1)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicMode_MSK            (0x80000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicMode_MIN            (0)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicMode_MAX            (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicMode_DEF            (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKCONTROL5_DeterministicMode_HSH            (0x011F1ED0)

#define DDRCLKCH1_CR_DCCCLKTRAINSTATUS0_REG                            (0x00001ED4)

  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS0_ClkDccDone_OFF               ( 0)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS0_ClkDccDone_WID               ( 3)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS0_ClkDccDone_MSK               (0x00000007)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS0_ClkDccDone_MIN               (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS0_ClkDccDone_MAX               (7) // 0x00000007
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS0_ClkDccDone_DEF               (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS0_ClkDccDone_HSH               (0x03001ED4)

  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS0_Spare_OFF                    ( 3)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS0_Spare_WID                    (29)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS0_Spare_MSK                    (0xFFFFFFF8)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS0_Spare_MIN                    (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS0_Spare_MAX                    (536870911) // 0x1FFFFFFF
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS0_Spare_DEF                    (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS0_Spare_HSH                    (0x1D031ED4)

#define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_REG                            (0x00001ED8)

  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Spare0_OFF                   ( 0)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Spare0_WID                   (10)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Spare0_MSK                   (0x000003FF)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Spare0_MIN                   (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Spare0_MAX                   (1023) // 0x000003FF
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Spare0_DEF                   (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Spare0_HSH                   (0x0A001ED8)

  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_CntDone_OFF                  (10)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_CntDone_WID                  ( 1)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_CntDone_MSK                  (0x00000400)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_CntDone_MIN                  (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_CntDone_MAX                  (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_CntDone_DEF                  (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_CntDone_HSH                  (0x010A1ED8)

  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_OFF                (11)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_WID                (15)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_MSK                (0x03FFF800)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_MIN                (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_MAX                (32767) // 0x00007FFF
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_DEF                (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Dcd_O_Cnt_HSH                (0x0F0B1ED8)

  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Spare1_OFF                   (26)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Spare1_WID                   ( 1)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Spare1_MSK                   (0x04000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Spare1_MIN                   (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Spare1_MAX                   (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Spare1_DEF                   (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_Spare1_HSH                   (0x011A1ED8)

  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_OFF          (27)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_WID          ( 5)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_MSK          (0xF8000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_MIN          (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_MAX          (31) // 0x0000001F
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_DEF          (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS1_BinFsmCurrState_HSH          (0x051B1ED8)

#define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_REG                            (0x00001EDC)

  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_AuxCnt_OFF                   ( 0)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_AuxCnt_WID                   (16)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_AuxCnt_MSK                   (0x0000FFFF)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_AuxCnt_MIN                   (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_AuxCnt_MAX                   (65535) // 0x0000FFFF
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_AuxCnt_DEF                   (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_AuxCnt_HSH                   (0x10001EDC)

  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_OFF            (16)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_WID            ( 7)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_MSK            (0x007F0000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_MIN            (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_MAX            (127) // 0x0000007F
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_DEF            (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_ReplicaOffset_HSH            (0x07101EDC)

  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_VTCompOffset_OFF             (23)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_VTCompOffset_WID             ( 7)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_VTCompOffset_MSK             (0x3F800000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_VTCompOffset_MIN             (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_VTCompOffset_MAX             (127) // 0x0000007F
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_VTCompOffset_DEF             (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_VTCompOffset_HSH             (0x07171EDC)

  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_Spare_OFF                    (30)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_Spare_WID                    ( 1)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_Spare_MSK                    (0x40000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_Spare_MIN                    (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_Spare_MAX                    (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_Spare_DEF                    (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_Spare_HSH                    (0x011E1EDC)

  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_CRVALID_OFF                  (31)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_CRVALID_WID                  ( 1)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_CRVALID_MSK                  (0x80000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_CRVALID_MIN                  (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_CRVALID_MAX                  (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_CRVALID_DEF                  (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINSTATUS2_CRVALID_HSH                  (0x011F1EDC)

#define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_REG                          (0x00001EE0)

  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_OFF         ( 0)
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_WID         (11)
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_MSK         (0x000007FF)
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_MIN         (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_MAX         (2047) // 0x000007FF
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_DEF         (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_DccConvergeErr_HSH         (0x0B001EE0)

  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_OFF         (11)
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_WID         (17)
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_MSK         (0x0FFFF800)
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_MIN         (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_MAX         (131071) // 0x0001FFFF
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_DEF         (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_MaxConvergeErr_HSH         (0x110B1EE0)

  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_Spare_OFF                  (28)
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_Spare_WID                  ( 4)
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_Spare_MSK                  (0xF0000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_Spare_MIN                  (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_Spare_MAX                  (15) // 0x0000000F
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_Spare_DEF                  (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINERRSTATUS_Spare_HSH                  (0x041C1EE0)

#define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_REG                           (0x00001EE4)

  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_OFF       ( 0)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_WID       ( 6)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_MSK       (0x0000003F)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_MIN       (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_MAX       (63) // 0x0000003F
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_DEF       (0x00000020)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp0_HSH       (0x06001EE4)

  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_OFF       ( 6)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_WID       ( 6)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_MSK       (0x00000FC0)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_MIN       (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_MAX       (63) // 0x0000003F
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_DEF       (0x00000020)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp1_HSH       (0x06061EE4)

  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_OFF       (12)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_WID       ( 6)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_MSK       (0x0003F000)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_MIN       (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_MAX       (63) // 0x0000003F
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_DEF       (0x00000020)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp2_HSH       (0x060C1EE4)

  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_OFF       (18)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_WID       ( 6)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_MSK       (0x00FC0000)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_MIN       (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_MAX       (63) // 0x0000003F
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_DEF       (0x00000020)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaTrain_GVp3_HSH       (0x06121EE4)

  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_OFF       (24)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_WID       ( 7)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_MSK       (0x7F000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_MIN       (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_MAX       (127) // 0x0000007F
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_DEF       (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_ReplicaOffsetPrev_HSH       (0x07181EE4)

  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_CRVALID_OFF                 (31)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_CRVALID_WID                 ( 1)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_CRVALID_MSK                 (0x80000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_CRVALID_MIN                 (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_CRVALID_MAX                 (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_CRVALID_DEF                 (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINREPLICA0_CRVALID_HSH                 (0x011F1EE4)

#define DDRCLKCH1_CR_DCCCLKTRAINVAL0_REG                               (0x00001EE8)

  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Clk0DccVal_OFF                  ( 0)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Clk0DccVal_WID                  ( 6)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Clk0DccVal_MSK                  (0x0000003F)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Clk0DccVal_MIN                  (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Clk0DccVal_MAX                  (63) // 0x0000003F
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Clk0DccVal_DEF                  (0x00000020)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Clk0DccVal_HSH                  (0x06001EE8)

  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Clk1DccVal_OFF                  ( 6)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Clk1DccVal_WID                  ( 6)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Clk1DccVal_MSK                  (0x00000FC0)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Clk1DccVal_MIN                  (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Clk1DccVal_MAX                  (63) // 0x0000003F
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Clk1DccVal_DEF                  (0x00000020)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Clk1DccVal_HSH                  (0x06061EE8)

  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Spare_OFF                       (12)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Spare_WID                       (17)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Spare_MSK                       (0x1FFFF000)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Spare_MIN                       (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Spare_MAX                       (131071) // 0x0001FFFF
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Spare_DEF                       (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Spare_HSH                       (0x110C1EE8)

  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_CRVALID_OFF                     (29)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_CRVALID_WID                     ( 1)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_CRVALID_MSK                     (0x20000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_CRVALID_MIN                     (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_CRVALID_MAX                     (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_CRVALID_DEF                     (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_CRVALID_HSH                     (0x011D1EE8)

  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_OFF               (30)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_WID               ( 2)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_MSK               (0xC0000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_MIN               (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_MAX               (3) // 0x00000003
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_DEF               (0x00000001)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL0_Rank1DccAipCb_HSH               (0x021E1EE8)

#define DDRCLKCH1_CR_DCCCLKTRAINVAL1_REG                               (0x00001EEC)

  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_OFF         ( 0)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_WID         ( 6)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_MSK         (0x0000003F)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_MIN         (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_MAX         (63) // 0x0000003F
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_DEF         (0x00000020)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_ReplicaShadowDccVal_HSH         (0x06001EEC)

  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_Spare_OFF                       ( 6)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_Spare_WID                       (20)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_Spare_MSK                       (0x03FFFFC0)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_Spare_MIN                       (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_Spare_MAX                       (1048575) // 0x000FFFFF
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_Spare_DEF                       (0x00000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_Spare_HSH                       (0x14061EEC)

  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_OFF        (26)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_WID        ( 3)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_MSK        (0x1C000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_MIN        (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_MAX        (7) // 0x00000007
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_DEF        (0x00000005)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_binfsmsteptosavecnts_HSH        (0x031A1EEC)

  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_OFF     (29)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_WID     ( 1)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_MSK     (0x20000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_MIN     (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_MAX     (1) // 0x00000001
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_DEF     (0x00000001)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_savecntsatchosenbinstep_HSH     (0x011D1EEC)

  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_RepDccAipCb_OFF                 (30)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_RepDccAipCb_WID                 ( 2)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_RepDccAipCb_MSK                 (0xC0000000)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_RepDccAipCb_MIN                 (0)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_RepDccAipCb_MAX                 (3) // 0x00000003
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_RepDccAipCb_DEF                 (0x00000001)
  #define DDRCLKCH1_CR_DCCCLKTRAINVAL1_RepDccAipCb_HSH                 (0x021E1EEC)

#define DDRCLKCH1_CR_DDRCRCLKTCOCONTROL0_REG                           (0x00001EF0)

  #define DDRCLKCH1_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_OFF              ( 0)
  #define DDRCLKCH1_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_WID              ( 6)
  #define DDRCLKCH1_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_MSK              (0x0000003F)
  #define DDRCLKCH1_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_MIN              (0)
  #define DDRCLKCH1_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_MAX              (63) // 0x0000003F
  #define DDRCLKCH1_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_DEF              (0x00000020)
  #define DDRCLKCH1_CR_DDRCRCLKTCOCONTROL0_ClkTcoComp_HSH              (0x06001EF0)

  #define DDRCLKCH1_CR_DDRCRCLKTCOCONTROL0_Spare_OFF                   ( 6)
  #define DDRCLKCH1_CR_DDRCRCLKTCOCONTROL0_Spare_WID                   (26)
  #define DDRCLKCH1_CR_DDRCRCLKTCOCONTROL0_Spare_MSK                   (0xFFFFFFC0)
  #define DDRCLKCH1_CR_DDRCRCLKTCOCONTROL0_Spare_MIN                   (0)
  #define DDRCLKCH1_CR_DDRCRCLKTCOCONTROL0_Spare_MAX                   (67108863) // 0x03FFFFFF
  #define DDRCLKCH1_CR_DDRCRCLKTCOCONTROL0_Spare_DEF                   (0x00000000)
  #define DDRCLKCH1_CR_DDRCRCLKTCOCONTROL0_Spare_HSH                   (0x1A061EF0)

#define DDRPHY_COMP_CR_DDRCRDATACOMP0_REG                              (0x00001F00)

  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_RcompDrvUp_OFF                 ( 0)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_RcompDrvUp_WID                 ( 6)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_RcompDrvUp_MSK                 (0x0000003F)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_RcompDrvUp_MIN                 (0)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_RcompDrvUp_MAX                 (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_RcompDrvUp_DEF                 (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_RcompDrvUp_HSH                 (0x06001F00)

  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_Rsvd_OFF                       ( 6)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_Rsvd_WID                       ( 8)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_Rsvd_MSK                       (0x00003FC0)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_Rsvd_MIN                       (0)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_Rsvd_MAX                       (255) // 0x000000FF
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_Rsvd_DEF                       (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_Rsvd_HSH                       (0x08061F00)

  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_RcompDrvDown_OFF               (14)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_RcompDrvDown_WID               ( 6)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_RcompDrvDown_MSK               (0x000FC000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_RcompDrvDown_MIN               (0)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_RcompDrvDown_MAX               (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_RcompDrvDown_DEF               (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_RcompDrvDown_HSH               (0x060E1F00)

  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_SlewRateComp_OFF               (20)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_SlewRateComp_WID               ( 5)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_SlewRateComp_MSK               (0x01F00000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_SlewRateComp_MIN               (0)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_SlewRateComp_MAX               (31) // 0x0000001F
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_SlewRateComp_DEF               (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_SlewRateComp_HSH               (0x05141F00)

  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_Spare_OFF                      (25)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_Spare_WID                      ( 7)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_Spare_MSK                      (0xFE000000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_Spare_MIN                      (0)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_Spare_MAX                      (127) // 0x0000007F
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_Spare_DEF                      (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP0_Spare_HSH                      (0x07191F00)

#define DDRPHY_COMP_CR_DDRCRDATACOMP1_REG                              (0x00001F04)

  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_RcompOdtUp_OFF                 ( 0)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_RcompOdtUp_WID                 ( 6)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_RcompOdtUp_MSK                 (0x0000003F)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_RcompOdtUp_MIN                 (0)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_RcompOdtUp_MAX                 (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_RcompOdtUp_DEF                 (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_RcompOdtUp_HSH                 (0x06001F04)

  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_spare_OFF                      ( 6)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_spare_WID                      (20)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_spare_MSK                      (0x03FFFFC0)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_spare_MIN                      (0)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_spare_MAX                      (1048575) // 0x000FFFFF
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_spare_DEF                      (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_spare_HSH                      (0x14061F04)

  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_RcompOdtDown_OFF               (26)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_RcompOdtDown_WID               ( 6)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_RcompOdtDown_MSK               (0xFC000000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_RcompOdtDown_MIN               (0)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_RcompOdtDown_MAX               (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_RcompOdtDown_DEF               (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP1_RcompOdtDown_HSH               (0x061A1F04)

#define DDRPHY_COMP_CR_DDRCRCMDCOMP_REG                                (0x00001F08)

  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_Scomp_OFF                        ( 0)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_Scomp_WID                        ( 6)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_Scomp_MSK                        (0x0000003F)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_Scomp_MIN                        (0)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_Scomp_MAX                        (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_Scomp_DEF                        (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_Scomp_HSH                        (0x06001F08)

  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_RcompDrvUp_OFF                   ( 6)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_RcompDrvUp_WID                   ( 6)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_RcompDrvUp_MSK                   (0x00000FC0)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_RcompDrvUp_MIN                   (0)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_RcompDrvUp_MAX                   (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_RcompDrvUp_DEF                   (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_RcompDrvUp_HSH                   (0x06061F08)

  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_RcompDrvDown_OFF                 (12)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_RcompDrvDown_WID                 ( 6)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_RcompDrvDown_MSK                 (0x0003F000)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_RcompDrvDown_MIN                 (0)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_RcompDrvDown_MAX                 (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_RcompDrvDown_DEF                 (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_RcompDrvDown_HSH                 (0x060C1F08)

  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_Spare_OFF                        (18)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_Spare_WID                        (14)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_Spare_MSK                        (0xFFFC0000)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_Spare_MIN                        (0)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_Spare_MAX                        (16383) // 0x00003FFF
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_Spare_DEF                        (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCMDCOMP_Spare_HSH                        (0x0E121F08)

#define DDRPHY_COMP_CR_DDRCRCTLCOMP_REG                                (0x00001F0C)

  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_Scomp_OFF                        ( 0)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_Scomp_WID                        ( 6)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_Scomp_MSK                        (0x0000003F)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_Scomp_MIN                        (0)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_Scomp_MAX                        (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_Scomp_DEF                        (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_Scomp_HSH                        (0x06001F0C)

  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_RcompDrvUp_OFF                   ( 6)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_RcompDrvUp_WID                   ( 6)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_RcompDrvUp_MSK                   (0x00000FC0)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_RcompDrvUp_MIN                   (0)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_RcompDrvUp_MAX                   (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_RcompDrvUp_DEF                   (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_RcompDrvUp_HSH                   (0x06061F0C)

  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_RcompDrvDown_OFF                 (12)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_RcompDrvDown_WID                 ( 6)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_RcompDrvDown_MSK                 (0x0003F000)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_RcompDrvDown_MIN                 (0)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_RcompDrvDown_MAX                 (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_RcompDrvDown_DEF                 (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_RcompDrvDown_HSH                 (0x060C1F0C)

  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_Spare_OFF                        (18)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_Spare_WID                        (14)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_Spare_MSK                        (0xFFFC0000)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_Spare_MIN                        (0)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_Spare_MAX                        (16383) // 0x00003FFF
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_Spare_DEF                        (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCTLCOMP_Spare_HSH                        (0x0E121F0C)

#define DDRPHY_COMP_CR_DDRCRCLKCOMP_REG                                (0x00001F10)

  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_Scomp_OFF                        ( 0)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_Scomp_WID                        ( 5)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_Scomp_MSK                        (0x0000001F)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_Scomp_MIN                        (0)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_Scomp_MAX                        (31) // 0x0000001F
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_Scomp_DEF                        (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_Scomp_HSH                        (0x05001F10)

  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_RcompDrvUp_OFF                   ( 5)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_RcompDrvUp_WID                   ( 6)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_RcompDrvUp_MSK                   (0x000007E0)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_RcompDrvUp_MIN                   (0)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_RcompDrvUp_MAX                   (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_RcompDrvUp_DEF                   (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_RcompDrvUp_HSH                   (0x06051F10)

  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_RcompDrvDown_OFF                 (11)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_RcompDrvDown_WID                 ( 6)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_RcompDrvDown_MSK                 (0x0001F800)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_RcompDrvDown_MIN                 (0)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_RcompDrvDown_MAX                 (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_RcompDrvDown_DEF                 (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_RcompDrvDown_HSH                 (0x060B1F10)

  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_Spare_OFF                        (17)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_Spare_WID                        (15)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_Spare_MSK                        (0xFFFE0000)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_Spare_MIN                        (0)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_Spare_MAX                        (32767) // 0x00007FFF
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_Spare_DEF                        (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCLKCOMP_Spare_HSH                        (0x0F111F10)

#define DDRPHY_COMP_CR_DDRCRCOMPCTL0_REG                               (0x00001F14)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_En200ohmVsshiPncUp_OFF          ( 0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_En200ohmVsshiPncUp_WID          ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_En200ohmVsshiPncUp_MSK          (0x00000001)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_En200ohmVsshiPncUp_MIN          (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_En200ohmVsshiPncUp_MAX          (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_En200ohmVsshiPncUp_DEF          (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_En200ohmVsshiPncUp_HSH          (0x01001F14)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_Spare0_OFF                      ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_Spare0_WID                      ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_Spare0_MSK                      (0x00000002)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_Spare0_MIN                      (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_Spare0_MAX                      (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_Spare0_DEF                      (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_Spare0_HSH                      (0x01011F14)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DisableCompRotate_OFF           ( 2)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DisableCompRotate_WID           ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DisableCompRotate_MSK           (0x00000004)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DisableCompRotate_MIN           (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DisableCompRotate_MAX           (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DisableCompRotate_DEF           (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DisableCompRotate_HSH           (0x01021F14)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DisableOdtStatic_OFF            ( 3)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DisableOdtStatic_WID            ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DisableOdtStatic_MSK            (0x00000008)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DisableOdtStatic_MIN            (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DisableOdtStatic_MAX            (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DisableOdtStatic_DEF            (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DisableOdtStatic_HSH            (0x01031F14)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqOdtUpDnOff_OFF                ( 4)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqOdtUpDnOff_WID                ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqOdtUpDnOff_MSK                (0x000003F0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqOdtUpDnOff_MIN                (-32)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqOdtUpDnOff_MAX                (31) // 0x0000001F
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqOdtUpDnOff_DEF                (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqOdtUpDnOff_HSH                (0x86041F14)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_FixOdtD_OFF                     (10)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_FixOdtD_WID                     ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_FixOdtD_MSK                     (0x00000400)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_FixOdtD_MIN                     (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_FixOdtD_MAX                     (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_FixOdtD_DEF                     (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_FixOdtD_HSH                     (0x010A1F14)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqDrvVref_OFF                   (11)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqDrvVref_WID                   ( 8)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqDrvVref_MSK                   (0x0007F800)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqDrvVref_MIN                   (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqDrvVref_MAX                   (255) // 0x000000FF
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqDrvVref_DEF                   (0x00000060)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqDrvVref_HSH                   (0x080B1F14)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqOdtVref_OFF                   (19)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqOdtVref_WID                   ( 8)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqOdtVref_MSK                   (0x07F80000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqOdtVref_MIN                   (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqOdtVref_MAX                   (255) // 0x000000FF
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqOdtVref_DEF                   (0x00000060)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_DqOdtVref_HSH                   (0x08131F14)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_Spare1_OFF                      (27)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_Spare1_WID                      ( 5)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_Spare1_MSK                      (0xF8000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_Spare1_MIN                      (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_Spare1_MAX                      (31) // 0x0000001F
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_Spare1_DEF                      (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL0_Spare1_HSH                      (0x051B1F14)

#define DDRPHY_COMP_CR_DDRCRCOMPCTL1_REG                               (0x00001F18)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqScompCells_OFF                ( 0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqScompCells_WID                ( 4)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqScompCells_MSK                (0x0000000F)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqScompCells_MIN                (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqScompCells_MAX                (15) // 0x0000000F
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqScompCells_DEF                (0x00000006)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqScompCells_HSH                (0x04001F18)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqScompPC_OFF                   ( 4)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqScompPC_WID                   ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqScompPC_MSK                   (0x00000010)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqScompPC_MIN                   (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqScompPC_MAX                   (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqScompPC_DEF                   (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqScompPC_HSH                   (0x01041F18)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CmdScompCells_OFF               ( 5)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CmdScompCells_WID               ( 4)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CmdScompCells_MSK               (0x000001E0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CmdScompCells_MIN               (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CmdScompCells_MAX               (15) // 0x0000000F
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CmdScompCells_DEF               (0x00000006)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CmdScompCells_HSH               (0x04051F18)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CmdScompPC_OFF                  ( 9)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CmdScompPC_WID                  ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CmdScompPC_MSK                  (0x00000200)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CmdScompPC_MIN                  (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CmdScompPC_MAX                  (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CmdScompPC_DEF                  (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CmdScompPC_HSH                  (0x01091F18)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CtlScompCells_OFF               (10)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CtlScompCells_WID               ( 4)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CtlScompCells_MSK               (0x00003C00)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CtlScompCells_MIN               (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CtlScompCells_MAX               (15) // 0x0000000F
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CtlScompCells_DEF               (0x00000006)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CtlScompCells_HSH               (0x040A1F18)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CtlScompPC_OFF                  (14)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CtlScompPC_WID                  ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CtlScompPC_MSK                  (0x00004000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CtlScompPC_MIN                  (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CtlScompPC_MAX                  (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CtlScompPC_DEF                  (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CtlScompPC_HSH                  (0x010E1F18)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_ClkScompCells_OFF               (15)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_ClkScompCells_WID               ( 4)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_ClkScompCells_MSK               (0x00078000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_ClkScompCells_MIN               (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_ClkScompCells_MAX               (15) // 0x0000000F
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_ClkScompCells_DEF               (0x00000006)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_ClkScompCells_HSH               (0x040F1F18)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_ClkScompPC_OFF                  (19)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_ClkScompPC_WID                  ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_ClkScompPC_MSK                  (0x00080000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_ClkScompPC_MIN                  (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_ClkScompPC_MAX                  (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_ClkScompPC_DEF                  (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_ClkScompPC_HSH                  (0x01131F18)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CompClkOn_OFF                   (20)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CompClkOn_WID                   ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CompClkOn_MSK                   (0x00100000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CompClkOn_MIN                   (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CompClkOn_MAX                   (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CompClkOn_DEF                   (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_CompClkOn_HSH                   (0x01141F18)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_Spare_OFF                       (21)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_Spare_WID                       ( 5)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_Spare_MSK                       (0x03E00000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_Spare_MIN                       (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_Spare_MAX                       (31) // 0x0000001F
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_Spare_DEF                       (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_Spare_HSH                       (0x05151F18)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_VccddqLo_OFF                    (26)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_VccddqLo_WID                    ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_VccddqLo_MSK                    (0x04000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_VccddqLo_MIN                    (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_VccddqLo_MAX                    (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_VccddqLo_DEF                    (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_VccddqLo_HSH                    (0x011A1F18)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqRcompStatLegs_OFF             (27)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqRcompStatLegs_WID             ( 2)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqRcompStatLegs_MSK             (0x18000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqRcompStatLegs_MIN             (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqRcompStatLegs_MAX             (3) // 0x00000003
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqRcompStatLegs_DEF             (0x00000003)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DqRcompStatLegs_HSH             (0x021B1F18)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DisableQuickComp_OFF            (29)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DisableQuickComp_WID            ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DisableQuickComp_MSK            (0x20000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DisableQuickComp_MIN            (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DisableQuickComp_MAX            (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DisableQuickComp_DEF            (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_DisableQuickComp_HSH            (0x011D1F18)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_SinStep_OFF                     (30)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_SinStep_WID                     ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_SinStep_MSK                     (0x40000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_SinStep_MIN                     (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_SinStep_MAX                     (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_SinStep_DEF                     (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_SinStep_HSH                     (0x011E1F18)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_SinStepAdv_OFF                  (31)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_SinStepAdv_WID                  ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_SinStepAdv_MSK                  (0x80000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_SinStepAdv_MIN                  (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_SinStepAdv_MAX                  (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_SinStepAdv_DEF                  (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL1_SinStepAdv_HSH                  (0x011F1F18)

#define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_REG                              (0x00001F1C)

  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_Spare1_OFF                     ( 0)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_Spare1_WID                     ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_Spare1_MSK                     (0x0000003F)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_Spare1_MIN                     (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_Spare1_MAX                     (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_Spare1_DEF                     (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_Spare1_HSH                     (0x06001F1C)

  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtOffset_OFF                   ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtOffset_WID                   ( 5)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtOffset_MSK                   (0x000007C0)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtOffset_MIN                   (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtOffset_MAX                   (31) // 0x0000001F
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtOffset_DEF                   (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtOffset_HSH                   (0x05061F1C)

  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtSlopeA_OFF                   (11)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtSlopeA_WID                   ( 3)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtSlopeA_MSK                   (0x00003800)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtSlopeA_MIN                   (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtSlopeA_MAX                   (7) // 0x00000007
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtSlopeA_DEF                   (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtSlopeA_HSH                   (0x030B1F1C)

  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtSlopeB_OFF                   (14)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtSlopeB_WID                   ( 3)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtSlopeB_MSK                   (0x0001C000)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtSlopeB_MIN                   (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtSlopeB_MAX                   (7) // 0x00000007
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtSlopeB_DEF                   (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_VtSlopeB_HSH                   (0x030E1F1C)

  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_PanicCompUpMult_OFF            (17)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_PanicCompUpMult_WID            ( 7)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_PanicCompUpMult_MSK            (0x00FE0000)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_PanicCompUpMult_MIN            (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_PanicCompUpMult_MAX            (127) // 0x0000007F
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_PanicCompUpMult_DEF            (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_PanicCompUpMult_HSH            (0x07111F1C)

  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_PanicCompDnMult_OFF            (24)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_PanicCompDnMult_WID            ( 7)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_PanicCompDnMult_MSK            (0x7F000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_PanicCompDnMult_MIN            (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_PanicCompDnMult_MAX            (127) // 0x0000007F
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_PanicCompDnMult_DEF            (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_PanicCompDnMult_HSH            (0x07181F1C)

  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_Spare_OFF                      (31)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_Spare_WID                      ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_Spare_MSK                      (0x80000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_Spare_MIN                      (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_Spare_MAX                      (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_Spare_DEF                      (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPVSSHI_Spare_HSH                      (0x011F1F1C)

#define DDRPHY_COMP_CR_DDRCRCOMPOVR_REG                                (0x00001F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqDrvU_OFF                       ( 0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqDrvU_WID                       ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqDrvU_MSK                       (0x00000001)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqDrvU_MIN                       (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqDrvU_MAX                       (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqDrvU_DEF                       (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqDrvU_HSH                       (0x01001F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqDrvD_OFF                       ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqDrvD_WID                       ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqDrvD_MSK                       (0x00000002)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqDrvD_MIN                       (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqDrvD_MAX                       (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqDrvD_DEF                       (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqDrvD_HSH                       (0x01011F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqOdtU_OFF                       ( 2)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqOdtU_WID                       ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqOdtU_MSK                       (0x00000004)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqOdtU_MIN                       (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqOdtU_MAX                       (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqOdtU_DEF                       (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqOdtU_HSH                       (0x01021F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqOdtD_OFF                       ( 3)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqOdtD_WID                       ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqOdtD_MSK                       (0x00000008)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqOdtD_MIN                       (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqOdtD_MAX                       (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqOdtD_DEF                       (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqOdtD_HSH                       (0x01031F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDrvU_OFF                      ( 4)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDrvU_WID                      ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDrvU_MSK                      (0x00000010)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDrvU_MIN                      (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDrvU_MAX                      (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDrvU_DEF                      (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDrvU_HSH                      (0x01041F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDrvD_OFF                      ( 5)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDrvD_WID                      ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDrvD_MSK                      (0x00000020)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDrvD_MIN                      (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDrvD_MAX                      (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDrvD_DEF                      (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDrvD_HSH                      (0x01051F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlDrvU_OFF                      ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlDrvU_WID                      ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlDrvU_MSK                      (0x00000040)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlDrvU_MIN                      (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlDrvU_MAX                      (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlDrvU_DEF                      (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlDrvU_HSH                      (0x01061F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlDrvD_OFF                      ( 7)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlDrvD_WID                      ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlDrvD_MSK                      (0x00000080)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlDrvD_MIN                      (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlDrvD_MAX                      (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlDrvD_DEF                      (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlDrvD_HSH                      (0x01071F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkDrvU_OFF                      ( 8)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkDrvU_WID                      ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkDrvU_MSK                      (0x00000100)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkDrvU_MIN                      (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkDrvU_MAX                      (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkDrvU_DEF                      (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkDrvU_HSH                      (0x01081F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkDrvD_OFF                      ( 9)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkDrvD_WID                      ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkDrvD_MSK                      (0x00000200)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkDrvD_MIN                      (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkDrvD_MAX                      (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkDrvD_DEF                      (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkDrvD_HSH                      (0x01091F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqSR_OFF                         (10)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqSR_WID                         ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqSR_MSK                         (0x00000400)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqSR_MIN                         (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqSR_MAX                         (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqSR_DEF                         (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_DqSR_HSH                         (0x010A1F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdSR_OFF                        (11)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdSR_WID                        ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdSR_MSK                        (0x00000800)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdSR_MIN                        (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdSR_MAX                        (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdSR_DEF                        (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdSR_HSH                        (0x010B1F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlSR_OFF                        (12)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlSR_WID                        ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlSR_MSK                        (0x00001000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlSR_MIN                        (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlSR_MAX                        (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlSR_DEF                        (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CtlSR_HSH                        (0x010C1F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkSR_OFF                        (13)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkSR_WID                        ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkSR_MSK                        (0x00002000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkSR_MIN                        (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkSR_MAX                        (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkSR_DEF                        (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_ClkSR_HSH                        (0x010D1F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_Spare_OFF                        (14)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_Spare_WID                        ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_Spare_MSK                        (0x000FC000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_Spare_MIN                        (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_Spare_MAX                        (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_Spare_DEF                        (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_Spare_HSH                        (0x060E1F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDn200_OFF                     (20)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDn200_WID                     ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDn200_MSK                     (0x00100000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDn200_MIN                     (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDn200_MAX                     (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDn200_DEF                     (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_CmdDn200_HSH                     (0x01141F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicDrvUp_OFF                   (21)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicDrvUp_WID                   ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicDrvUp_MSK                   (0x00200000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicDrvUp_MIN                   (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicDrvUp_MAX                   (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicDrvUp_DEF                   (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicDrvUp_HSH                   (0x01151F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicDrvDn_OFF                   (22)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicDrvDn_WID                   ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicDrvDn_MSK                   (0x00400000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicDrvDn_MIN                   (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicDrvDn_MAX                   (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicDrvDn_DEF                   (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicDrvDn_HSH                   (0x01161F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_VTComp_OFF                       (23)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_VTComp_WID                       ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_VTComp_MSK                       (0x00800000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_VTComp_MIN                       (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_VTComp_MAX                       (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_VTComp_DEF                       (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_VTComp_HSH                       (0x01171F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_LsComp_OFF                       (24)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_LsComp_WID                       ( 3)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_LsComp_MSK                       (0x07000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_LsComp_MIN                       (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_LsComp_MAX                       (7) // 0x00000007
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_LsComp_DEF                       (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_LsComp_HSH                       (0x03181F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicVttUp_OFF                   (27)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicVttUp_WID                   ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicVttUp_MSK                   (0x08000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicVttUp_MIN                   (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicVttUp_MAX                   (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicVttUp_DEF                   (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicVttUp_HSH                   (0x011B1F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicVttDn_OFF                   (28)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicVttDn_WID                   ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicVttDn_MSK                   (0x10000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicVttDn_MIN                   (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicVttDn_MAX                   (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicVttDn_DEF                   (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_PanicVttDn_HSH                   (0x011C1F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_RcompCheckEn_OFF                 (29)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_RcompCheckEn_WID                 ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_RcompCheckEn_MSK                 (0x20000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_RcompCheckEn_MIN                 (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_RcompCheckEn_MAX                 (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_RcompCheckEn_DEF                 (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_RcompCheckEn_HSH                 (0x011D1F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_RcompSwapEn_OFF                  (30)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_RcompSwapEn_WID                  ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_RcompSwapEn_MSK                  (0x40000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_RcompSwapEn_MIN                  (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_RcompSwapEn_MAX                  (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_RcompSwapEn_DEF                  (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_RcompSwapEn_HSH                  (0x011E1F20)

  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_VtDmVrefFsm_OFF                  (31)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_VtDmVrefFsm_WID                  ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_VtDmVrefFsm_MSK                  (0x80000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_VtDmVrefFsm_MIN                  (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_VtDmVrefFsm_MAX                  (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_VtDmVrefFsm_DEF                  (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPOVR_VtDmVrefFsm_HSH                  (0x011F1F20)

#define DDRPHY_COMP_CR_DDRCRCOMPCTL2_REG                               (0x00001F28)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_EnVddqOdt_OFF                   ( 0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_EnVddqOdt_WID                   ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_EnVddqOdt_MSK                   (0x00000001)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_EnVddqOdt_MIN                   (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_EnVddqOdt_MAX                   (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_EnVddqOdt_DEF                   (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_EnVddqOdt_HSH                   (0x01001F28)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_EnVttOdt_OFF                    ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_EnVttOdt_WID                    ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_EnVttOdt_MSK                    (0x00000002)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_EnVttOdt_MIN                    (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_EnVttOdt_MAX                    (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_EnVttOdt_DEF                    (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_EnVttOdt_HSH                    (0x01011F28)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_Spare_OFF                       ( 2)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_Spare_WID                       ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_Spare_MSK                       (0x000000FC)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_Spare_MIN                       (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_Spare_MAX                       (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_Spare_DEF                       (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_Spare_HSH                       (0x06021F28)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_VttPanicCompUpMult_OFF          ( 8)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_VttPanicCompUpMult_WID          ( 4)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_VttPanicCompUpMult_MSK          (0x00000F00)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_VttPanicCompUpMult_MIN          (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_VttPanicCompUpMult_MAX          (15) // 0x0000000F
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_VttPanicCompUpMult_DEF          (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_VttPanicCompUpMult_HSH          (0x04081F28)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_VttPanicCompDnMult_OFF          (12)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_VttPanicCompDnMult_WID          ( 5)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_VttPanicCompDnMult_MSK          (0x0001F000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_VttPanicCompDnMult_MIN          (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_VttPanicCompDnMult_MAX          (31) // 0x0000001F
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_VttPanicCompDnMult_DEF          (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_VttPanicCompDnMult_HSH          (0x050C1F28)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_DisableFallingPD_OFF            (17)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_DisableFallingPD_WID            ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_DisableFallingPD_MSK            (0x00020000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_DisableFallingPD_MIN            (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_DisableFallingPD_MAX            (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_DisableFallingPD_DEF            (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_DisableFallingPD_HSH            (0x01111F28)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_SinStepAdvBin_OFF               (18)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_SinStepAdvBin_WID               ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_SinStepAdvBin_MSK               (0x00040000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_SinStepAdvBin_MIN               (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_SinStepAdvBin_MAX               (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_SinStepAdvBin_DEF               (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_SinStepAdvBin_HSH               (0x01121F28)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_SinStepBin_OFF                  (19)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_SinStepBin_WID                  ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_SinStepBin_MSK                  (0x00080000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_SinStepBin_MIN                  (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_SinStepBin_MAX                  (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_SinStepBin_DEF                  (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_SinStepBin_HSH                  (0x01131F28)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CMDLowsupEn_OFF                 (20)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CMDLowsupEn_WID                 ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CMDLowsupEn_MSK                 (0x00100000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CMDLowsupEn_MIN                 (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CMDLowsupEn_MAX                 (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CMDLowsupEn_DEF                 (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CMDLowsupEn_HSH                 (0x01141F28)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CTLLowsupEn_OFF                 (21)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CTLLowsupEn_WID                 ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CTLLowsupEn_MSK                 (0x00200000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CTLLowsupEn_MIN                 (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CTLLowsupEn_MAX                 (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CTLLowsupEn_DEF                 (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CTLLowsupEn_HSH                 (0x01151F28)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_DQDQSLowsupEn_OFF               (22)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_DQDQSLowsupEn_WID               ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_DQDQSLowsupEn_MSK               (0x00400000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_DQDQSLowsupEn_MIN               (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_DQDQSLowsupEn_MAX               (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_DQDQSLowsupEn_DEF               (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_DQDQSLowsupEn_HSH               (0x01161F28)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CLKLowsupEn_OFF                 (23)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CLKLowsupEn_WID                 ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CLKLowsupEn_MSK                 (0x00800000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CLKLowsupEn_MIN                 (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CLKLowsupEn_MAX                 (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CLKLowsupEn_DEF                 (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_CLKLowsupEn_HSH                 (0x01171F28)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_PanicDrvUpVref_OFF              (24)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_PanicDrvUpVref_WID              ( 8)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_PanicDrvUpVref_MSK              (0xFF000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_PanicDrvUpVref_MIN              (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_PanicDrvUpVref_MAX              (255) // 0x000000FF
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_PanicDrvUpVref_DEF              (0x0000004C)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL2_PanicDrvUpVref_HSH              (0x08181F28)

#define DDRPHY_COMP_CR_DDRCRDATACOMP2_REG                              (0x00001F2C)

  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_PanicVttUp_OFF                 ( 0)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_PanicVttUp_WID                 ( 8)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_PanicVttUp_MSK                 (0x000000FF)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_PanicVttUp_MIN                 (0)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_PanicVttUp_MAX                 (255) // 0x000000FF
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_PanicVttUp_DEF                 (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_PanicVttUp_HSH                 (0x08001F2C)

  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_PanicVttDn_OFF                 ( 8)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_PanicVttDn_WID                 ( 8)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_PanicVttDn_MSK                 (0x0000FF00)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_PanicVttDn_MIN                 (0)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_PanicVttDn_MAX                 (255) // 0x000000FF
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_PanicVttDn_DEF                 (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_PanicVttDn_HSH                 (0x08081F2C)

  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_RcompCmdDn200ohm_OFF           (16)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_RcompCmdDn200ohm_WID           ( 6)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_RcompCmdDn200ohm_MSK           (0x003F0000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_RcompCmdDn200ohm_MIN           (0)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_RcompCmdDn200ohm_MAX           (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_RcompCmdDn200ohm_DEF           (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_RcompCmdDn200ohm_HSH           (0x06101F2C)

  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_Spare_OFF                      (22)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_Spare_WID                      (10)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_Spare_MSK                      (0xFFC00000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_Spare_MIN                      (0)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_Spare_MAX                      (1023) // 0x000003FF
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_Spare_DEF                      (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDATACOMP2_Spare_HSH                      (0x0A161F2C)

#define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_REG                             (0x00001F30)

  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_DqRcompDrvUp_Previous_OFF     ( 0)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_DqRcompDrvUp_Previous_WID     ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_DqRcompDrvUp_Previous_MSK     (0x0000003F)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_DqRcompDrvUp_Previous_MIN     (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_DqRcompDrvUp_Previous_MAX     (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_DqRcompDrvUp_Previous_DEF     (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_DqRcompDrvUp_Previous_HSH     (0x06001F30)

  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_DqRcompDrvDn_Previous_OFF     ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_DqRcompDrvDn_Previous_WID     ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_DqRcompDrvDn_Previous_MSK     (0x00000FC0)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_DqRcompDrvDn_Previous_MIN     (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_DqRcompDrvDn_Previous_MAX     (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_DqRcompDrvDn_Previous_DEF     (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_DqRcompDrvDn_Previous_HSH     (0x06061F30)

  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_OdtRcompDrvUp_Previous_OFF    (12)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_OdtRcompDrvUp_Previous_WID    ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_OdtRcompDrvUp_Previous_MSK    (0x0003F000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_OdtRcompDrvUp_Previous_MIN    (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_OdtRcompDrvUp_Previous_MAX    (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_OdtRcompDrvUp_Previous_DEF    (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_OdtRcompDrvUp_Previous_HSH    (0x060C1F30)

  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_OdtRcompDrvDn_Previous_OFF    (18)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_OdtRcompDrvDn_Previous_WID    ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_OdtRcompDrvDn_Previous_MSK    (0x00FC0000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_OdtRcompDrvDn_Previous_MIN    (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_OdtRcompDrvDn_Previous_MAX    (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_OdtRcompDrvDn_Previous_DEF    (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_OdtRcompDrvDn_Previous_HSH    (0x06121F30)

  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_ClkRcompDrvUp_Previous_OFF    (24)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_ClkRcompDrvUp_Previous_WID    ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_ClkRcompDrvUp_Previous_MSK    (0x3F000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_ClkRcompDrvUp_Previous_MIN    (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_ClkRcompDrvUp_Previous_MAX    (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_ClkRcompDrvUp_Previous_DEF    (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_ClkRcompDrvUp_Previous_HSH    (0x06181F30)

  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_Rcomp_DriftLimit_OFF          (30)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_Rcomp_DriftLimit_WID          ( 2)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_Rcomp_DriftLimit_MSK          (0xC0000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_Rcomp_DriftLimit_MIN          (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_Rcomp_DriftLimit_MAX          (3) // 0x00000003
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_Rcomp_DriftLimit_DEF          (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG0_Rcomp_DriftLimit_HSH          (0x021E1F30)

#define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_REG                             (0x00001F34)

  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_ClkRcompDrvDn_Previous_OFF    ( 0)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_ClkRcompDrvDn_Previous_WID    ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_ClkRcompDrvDn_Previous_MSK    (0x0000003F)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_ClkRcompDrvDn_Previous_MIN    (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_ClkRcompDrvDn_Previous_MAX    (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_ClkRcompDrvDn_Previous_DEF    (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_ClkRcompDrvDn_Previous_HSH    (0x06001F34)

  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CmdRcompDrvUp_Previous_OFF    ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CmdRcompDrvUp_Previous_WID    ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CmdRcompDrvUp_Previous_MSK    (0x00000FC0)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CmdRcompDrvUp_Previous_MIN    (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CmdRcompDrvUp_Previous_MAX    (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CmdRcompDrvUp_Previous_DEF    (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CmdRcompDrvUp_Previous_HSH    (0x06061F34)

  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CmdRcompDrvDn_Previous_OFF    (12)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CmdRcompDrvDn_Previous_WID    ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CmdRcompDrvDn_Previous_MSK    (0x0003F000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CmdRcompDrvDn_Previous_MIN    (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CmdRcompDrvDn_Previous_MAX    (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CmdRcompDrvDn_Previous_DEF    (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CmdRcompDrvDn_Previous_HSH    (0x060C1F34)

  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CtlRcompDrvUp_Previous_OFF    (18)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CtlRcompDrvUp_Previous_WID    ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CtlRcompDrvUp_Previous_MSK    (0x00FC0000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CtlRcompDrvUp_Previous_MIN    (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CtlRcompDrvUp_Previous_MAX    (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CtlRcompDrvUp_Previous_DEF    (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CtlRcompDrvUp_Previous_HSH    (0x06121F34)

  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CtlRcompDrvDn_Previous_OFF    (24)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CtlRcompDrvDn_Previous_WID    ( 6)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CtlRcompDrvDn_Previous_MSK    (0x3F000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CtlRcompDrvDn_Previous_MIN    (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CtlRcompDrvDn_Previous_MAX    (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CtlRcompDrvDn_Previous_DEF    (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_CtlRcompDrvDn_Previous_HSH    (0x06181F34)

  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_Drift_detected_OFF            (30)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_Drift_detected_WID            ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_Drift_detected_MSK            (0x40000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_Drift_detected_MIN            (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_Drift_detected_MAX            (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_Drift_detected_DEF            (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_Drift_detected_HSH            (0x011E1F34)

  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_Spare_OFF                     (31)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_Spare_WID                     ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_Spare_MSK                     (0x80000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_Spare_MIN                     (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_Spare_MAX                     (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_Spare_DEF                     (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPDEBUG1_Spare_HSH                     (0x011F1F34)

#define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_REG                        (0x00001F38)

  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_DDRIORssRcompDef_OFF     ( 0)
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_DDRIORssRcompDef_WID     ( 6)
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_DDRIORssRcompDef_MSK     (0x0000003F)
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_DDRIORssRcompDef_MIN     (0)
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_DDRIORssRcompDef_MAX     (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_DDRIORssRcompDef_DEF     (0x0000001F)
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_DDRIORssRcompDef_HSH     (0x06001F38)

  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_DDRIORttRcompDef_OFF     ( 6)
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_DDRIORttRcompDef_WID     ( 6)
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_DDRIORttRcompDef_MSK     (0x00000FC0)
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_DDRIORttRcompDef_MIN     (0)
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_DDRIORttRcompDef_MAX     (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_DDRIORttRcompDef_DEF     (0x0000001F)
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_DDRIORttRcompDef_HSH     (0x06061F38)

  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_Spare_OFF                (12)
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_Spare_WID                (20)
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_Spare_MSK                (0xFFFFF000)
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_Spare_MIN                (0)
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_Spare_MAX                (1048575) // 0x000FFFFF
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_Spare_DEF                (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDIGVIEWRCOMPCTL_Spare_HSH                (0x140C1F38)

#define DDRPHY_COMP_CR_DDRCRCOMPCTL3_REG                               (0x00001F3C)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CmdDrvVref_OFF                  ( 0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CmdDrvVref_WID                  ( 8)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CmdDrvVref_MSK                  (0x000000FF)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CmdDrvVref_MIN                  (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CmdDrvVref_MAX                  (255) // 0x000000FF
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CmdDrvVref_DEF                  (0x00000060)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CmdDrvVref_HSH                  (0x08001F3C)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CtlDrvVref_OFF                  ( 8)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CtlDrvVref_WID                  ( 8)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CtlDrvVref_MSK                  (0x0000FF00)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CtlDrvVref_MIN                  (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CtlDrvVref_MAX                  (255) // 0x000000FF
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CtlDrvVref_DEF                  (0x00000060)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CtlDrvVref_HSH                  (0x08081F3C)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_ClkDrvVref_OFF                  (16)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_ClkDrvVref_WID                  ( 8)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_ClkDrvVref_MSK                  (0x00FF0000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_ClkDrvVref_MIN                  (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_ClkDrvVref_MAX                  (255) // 0x000000FF
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_ClkDrvVref_DEF                  (0x00000060)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_ClkDrvVref_HSH                  (0x08101F3C)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CmdDrvVrefForVttPanicComp_OFF   (24)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CmdDrvVrefForVttPanicComp_WID   ( 8)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CmdDrvVrefForVttPanicComp_MSK   (0xFF000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CmdDrvVrefForVttPanicComp_MIN   (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CmdDrvVrefForVttPanicComp_MAX   (255) // 0x000000FF
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CmdDrvVrefForVttPanicComp_DEF   (0x00000080)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL3_CmdDrvVrefForVttPanicComp_HSH   (0x08181F3C)

#define DDRPHY_COMP_CR_DDRCRVSSICOMP_REG                               (0x00001F40)

  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_PanicDrvDn_OFF                  ( 0)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_PanicDrvDn_WID                  (10)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_PanicDrvDn_MSK                  (0x000003FF)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_PanicDrvDn_MIN                  (0)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_PanicDrvDn_MAX                  (1023) // 0x000003FF
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_PanicDrvDn_DEF                  (0x00000094)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_PanicDrvDn_HSH                  (0x0A001F40)

  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_PanicDrvUp_OFF                  (10)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_PanicDrvUp_WID                  (10)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_PanicDrvUp_MSK                  (0x000FFC00)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_PanicDrvUp_MIN                  (0)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_PanicDrvUp_MAX                  (1023) // 0x000003FF
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_PanicDrvUp_DEF                  (0x00000094)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_PanicDrvUp_HSH                  (0x0A0A1F40)

  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_VTComp_OFF                      (20)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_VTComp_WID                      ( 5)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_VTComp_MSK                      (0x01F00000)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_VTComp_MIN                      (0)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_VTComp_MAX                      (31) // 0x0000001F
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_VTComp_DEF                      (0x00000005)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_VTComp_HSH                      (0x05141F40)

  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_spare_OFF                       (25)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_spare_WID                       ( 7)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_spare_MSK                       (0xFE000000)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_spare_MIN                       (0)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_spare_MAX                       (127) // 0x0000007F
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_spare_DEF                       (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRVSSICOMP_spare_HSH                       (0x07191F40)

#define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_REG                             (0x00001F44)

  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_VTComp_OFF                    ( 0)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_VTComp_WID                    ( 6)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_VTComp_MSK                    (0x0000003F)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_VTComp_MIN                    (0)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_VTComp_MAX                    (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_VTComp_DEF                    (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_VTComp_HSH                    (0x06001F44)

  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_NxtVTCompValidForDcc_OFF      ( 6)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_NxtVTCompValidForDcc_WID      ( 1)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_NxtVTCompValidForDcc_MSK      (0x00000040)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_NxtVTCompValidForDcc_MIN      (0)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_NxtVTCompValidForDcc_MAX      (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_NxtVTCompValidForDcc_DEF      (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_NxtVTCompValidForDcc_HSH      (0x01061F44)

  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_CompLoopsNumForDcc_OFF        ( 7)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_CompLoopsNumForDcc_WID        ( 5)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_CompLoopsNumForDcc_MSK        (0x00000F80)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_CompLoopsNumForDcc_MIN        (0)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_CompLoopsNumForDcc_MAX        (31) // 0x0000001F
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_CompLoopsNumForDcc_DEF        (0x00000001)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_CompLoopsNumForDcc_HSH        (0x05071F44)

  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_ActivateCompLoopsCntForDcc_OFF (12)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_ActivateCompLoopsCntForDcc_WID ( 1)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_ActivateCompLoopsCntForDcc_MSK (0x00001000)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_ActivateCompLoopsCntForDcc_MIN (0)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_ActivateCompLoopsCntForDcc_MAX (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_ActivateCompLoopsCntForDcc_DEF (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_ActivateCompLoopsCntForDcc_HSH (0x010C1F44)

  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_KfactorForDccVtCompOffsetCalc_OFF (13)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_KfactorForDccVtCompOffsetCalc_WID ( 2)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_KfactorForDccVtCompOffsetCalc_MSK (0x00006000)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_KfactorForDccVtCompOffsetCalc_MIN (0)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_KfactorForDccVtCompOffsetCalc_MAX (3) // 0x00000003
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_KfactorForDccVtCompOffsetCalc_DEF (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_KfactorForDccVtCompOffsetCalc_HSH (0x020D1F44)

  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_Spare_OFF                     (15)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_Spare_WID                     (17)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_Spare_MSK                     (0xFFFF8000)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_Spare_MIN                     (0)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_Spare_MAX                     (131071) // 0x0001FFFF
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_Spare_DEF                     (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRDMVREFCOMP_Spare_HSH                     (0x110F1F44)

#define DDRPHY_COMP_CR_DDRCRCOMPCTL4_REG                               (0x00001F48)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_CmdDrvVrefDn_OFF                ( 0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_CmdDrvVrefDn_WID                ( 8)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_CmdDrvVrefDn_MSK                (0x000000FF)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_CmdDrvVrefDn_MIN                (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_CmdDrvVrefDn_MAX                (255) // 0x000000FF
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_CmdDrvVrefDn_DEF                (0x00000060)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_CmdDrvVrefDn_HSH                (0x08001F48)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_CtlDrvVrefDn_OFF                ( 8)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_CtlDrvVrefDn_WID                ( 8)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_CtlDrvVrefDn_MSK                (0x0000FF00)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_CtlDrvVrefDn_MIN                (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_CtlDrvVrefDn_MAX                (255) // 0x000000FF
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_CtlDrvVrefDn_DEF                (0x00000060)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_CtlDrvVrefDn_HSH                (0x08081F48)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_ClkDrvVrefDn_OFF                (16)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_ClkDrvVrefDn_WID                ( 8)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_ClkDrvVrefDn_MSK                (0x00FF0000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_ClkDrvVrefDn_MIN                (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_ClkDrvVrefDn_MAX                (255) // 0x000000FF
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_ClkDrvVrefDn_DEF                (0x00000060)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_ClkDrvVrefDn_HSH                (0x08101F48)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_DqDrvVrefDn_OFF                 (24)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_DqDrvVrefDn_WID                 ( 8)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_DqDrvVrefDn_MSK                 (0xFF000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_DqDrvVrefDn_MIN                 (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_DqDrvVrefDn_MAX                 (255) // 0x000000FF
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_DqDrvVrefDn_DEF                 (0x00000060)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL4_DqDrvVrefDn_HSH                 (0x08181F48)

#define DDRPHY_COMP_CR_DDRCRCOMPCTL5_REG                               (0x00001F4C)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_DqOdtVrefDn_OFF                 ( 0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_DqOdtVrefDn_WID                 ( 8)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_DqOdtVrefDn_MSK                 (0x000000FF)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_DqOdtVrefDn_MIN                 (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_DqOdtVrefDn_MAX                 (255) // 0x000000FF
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_DqOdtVrefDn_DEF                 (0x00000060)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_DqOdtVrefDn_HSH                 (0x08001F4C)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_view_pins_status_OFF            ( 8)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_view_pins_status_WID            ( 2)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_view_pins_status_MSK            (0x00000300)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_view_pins_status_MIN            (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_view_pins_status_MAX            (3) // 0x00000003
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_view_pins_status_DEF            (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_view_pins_status_HSH            (0x02081F4C)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_Lp4xVoltageSelect_OFF           (10)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_Lp4xVoltageSelect_WID           ( 1)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_Lp4xVoltageSelect_MSK           (0x00000400)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_Lp4xVoltageSelect_MIN           (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_Lp4xVoltageSelect_MAX           (1) // 0x00000001
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_Lp4xVoltageSelect_DEF           (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_Lp4xVoltageSelect_HSH           (0x010A1F4C)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_VttTargetCode1stLevel_OFF       (11)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_VttTargetCode1stLevel_WID       ( 5)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_VttTargetCode1stLevel_MSK       (0x0000F800)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_VttTargetCode1stLevel_MIN       (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_VttTargetCode1stLevel_MAX       (31) // 0x0000001F
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_VttTargetCode1stLevel_DEF       (0x0000001C)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_VttTargetCode1stLevel_HSH       (0x050B1F4C)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_VttTargetCode2ndLevel_OFF       (16)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_VttTargetCode2ndLevel_WID       ( 3)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_VttTargetCode2ndLevel_MSK       (0x00070000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_VttTargetCode2ndLevel_MIN       (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_VttTargetCode2ndLevel_MAX       (7) // 0x00000007
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_VttTargetCode2ndLevel_DEF       (0x00000005)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_VttTargetCode2ndLevel_HSH       (0x03101F4C)

  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_Spare_OFF                       (19)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_Spare_WID                       (13)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_Spare_MSK                       (0xFFF80000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_Spare_MIN                       (0)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_Spare_MAX                       (8191) // 0x00001FFF
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_Spare_DEF                       (0x00000000)
  #define DDRPHY_COMP_CR_DDRCRCOMPCTL5_Spare_HSH                       (0x0D131F4C)

#define DDRPHY_COMP_CR_DCCDCOCONTROL0_REG                              (0x00001F50)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PreLfsrDiv_OFF                 ( 0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PreLfsrDiv_WID                 ( 2)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PreLfsrDiv_MSK                 (0x00000003)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PreLfsrDiv_MIN                 (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PreLfsrDiv_MAX                 (3) // 0x00000003
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PreLfsrDiv_DEF                 (0x00000003)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PreLfsrDiv_HSH                 (0x02001F50)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDivInitVal_OFF             ( 2)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDivInitVal_WID             ( 4)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDivInitVal_MSK             (0x0000003C)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDivInitVal_MIN             (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDivInitVal_MAX             (15) // 0x0000000F
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDivInitVal_DEF             (0x0000000F)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDivInitVal_HSH             (0x04021F50)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PreDiv_OFF                     ( 6)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PreDiv_WID                     ( 2)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PreDiv_MSK                     (0x000000C0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PreDiv_MIN                     (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PreDiv_MAX                     (3) // 0x00000003
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PreDiv_DEF                     (0x00000003)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PreDiv_HSH                     (0x02061F50)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDiv_OFF                    ( 8)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDiv_WID                    ( 4)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDiv_MSK                    (0x00000F00)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDiv_MIN                    (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDiv_MAX                    (15) // 0x0000000F
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDiv_DEF                    (0x0000000F)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDiv_HSH                    (0x04081F50)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDivCntWindow_OFF           (12)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDivCntWindow_WID           (11)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDivCntWindow_MSK           (0x007FF000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDivCntWindow_MIN           (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDivCntWindow_MAX           (2047) // 0x000007FF
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDivCntWindow_DEF           (0x0000005B)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_PostDivCntWindow_HSH           (0x0B0C1F50)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_Spare_OFF                      (23)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_Spare_WID                      ( 9)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_Spare_MSK                      (0xFF800000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_Spare_MIN                      (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_Spare_MAX                      (511) // 0x000001FF
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_Spare_DEF                      (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL0_Spare_HSH                      (0x09171F50)

#define DDRPHY_COMP_CR_DCCDCOCONTROL1_REG                              (0x00001F54)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_PreDivCntWindow_OFF            ( 0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_PreDivCntWindow_WID            (11)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_PreDivCntWindow_MSK            (0x000007FF)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_PreDivCntWindow_MIN            (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_PreDivCntWindow_MAX            (2047) // 0x000007FF
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_PreDivCntWindow_DEF            (0x000000BB)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_PreDivCntWindow_HSH            (0x0B001F54)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_RefCntWindow_OFF               (11)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_RefCntWindow_WID               (12)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_RefCntWindow_MSK               (0x007FF800)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_RefCntWindow_MIN               (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_RefCntWindow_MAX               (4095) // 0x00000FFF
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_RefCntWindow_DEF               (0x00000300)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_RefCntWindow_HSH               (0x0C0B1F54)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_DcoViewSelect0_OFF             (23)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_DcoViewSelect0_WID             ( 4)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_DcoViewSelect0_MSK             (0x07800000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_DcoViewSelect0_MIN             (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_DcoViewSelect0_MAX             (15) // 0x0000000F
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_DcoViewSelect0_DEF             (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_DcoViewSelect0_HSH             (0x04171F54)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_DcoViewSelect1_OFF             (27)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_DcoViewSelect1_WID             ( 4)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_DcoViewSelect1_MSK             (0x78000000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_DcoViewSelect1_MIN             (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_DcoViewSelect1_MAX             (15) // 0x0000000F
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_DcoViewSelect1_DEF             (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_DcoViewSelect1_HSH             (0x041B1F54)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_ClkGateDisable_OFF             (31)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_ClkGateDisable_WID             ( 1)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_ClkGateDisable_MSK             (0x80000000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_ClkGateDisable_MIN             (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_ClkGateDisable_MAX             (1) // 0x00000001
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_ClkGateDisable_DEF             (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL1_ClkGateDisable_HSH             (0x011F1F54)

#define DDRPHY_COMP_CR_DCCDCOSTATUS0_REG                               (0x00001F58)

  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_RefCntDone_OFF                  ( 0)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_RefCntDone_WID                  ( 1)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_RefCntDone_MSK                  (0x00000001)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_RefCntDone_MIN                  (0)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_RefCntDone_MAX                  (1) // 0x00000001
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_RefCntDone_DEF                  (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_RefCntDone_HSH                  (0x01001F58)

  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivCntDone_OFF               ( 1)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivCntDone_WID               ( 1)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivCntDone_MSK               (0x00000002)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivCntDone_MIN               (0)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivCntDone_MAX               (1) // 0x00000001
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivCntDone_DEF               (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivCntDone_HSH               (0x01011F58)

  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivCntDone_OFF              ( 2)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivCntDone_WID              ( 1)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivCntDone_MSK              (0x00000004)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivCntDone_MIN              (0)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivCntDone_MAX              (1) // 0x00000001
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivCntDone_DEF              (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivCntDone_HSH              (0x01021F58)

  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivCnt_OFF                   ( 3)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivCnt_WID                   (11)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivCnt_MSK                   (0x00003FF8)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivCnt_MIN                   (0)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivCnt_MAX                   (2047) // 0x000007FF
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivCnt_DEF                   (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivCnt_HSH                   (0x0B031F58)

  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivCnt_OFF                  (14)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivCnt_WID                  (11)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivCnt_MSK                  (0x01FFC000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivCnt_MIN                  (0)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivCnt_MAX                  (2047) // 0x000007FF
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivCnt_DEF                  (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivCnt_HSH                  (0x0B0E1F58)

  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivErr_OFF                   (25)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivErr_WID                   ( 1)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivErr_MSK                   (0x02000000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivErr_MIN                   (0)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivErr_MAX                   (1) // 0x00000001
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivErr_DEF                   (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PreDivErr_HSH                   (0x01191F58)

  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivErr_OFF                  (26)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivErr_WID                  ( 1)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivErr_MSK                  (0x04000000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivErr_MIN                  (0)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivErr_MAX                  (1) // 0x00000001
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivErr_DEF                  (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_PostDivErr_HSH                  (0x011A1F58)

  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_CurrState_OFF                   (27)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_CurrState_WID                   ( 5)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_CurrState_MSK                   (0xF8000000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_CurrState_MIN                   (0)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_CurrState_MAX                   (31) // 0x0000001F
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_CurrState_DEF                   (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS0_CurrState_HSH                   (0x051B1F58)

#define DDRPHY_COMP_CR_DCCDCOSTATUS1_REG                               (0x00001F5C)

  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_RefCnt_OFF                      ( 0)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_RefCnt_WID                      (12)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_RefCnt_MSK                      (0x00000FFF)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_RefCnt_MIN                      (0)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_RefCnt_MAX                      (4095) // 0x00000FFF
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_RefCnt_DEF                      (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_RefCnt_HSH                      (0x0C001F5C)

  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompOffset_OFF                (12)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompOffset_WID                ( 7)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompOffset_MSK                (0x0007F000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompOffset_MIN                (0)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompOffset_MAX                (127) // 0x0000007F
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompOffset_DEF                (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompOffset_HSH                (0x070C1F5C)

  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompOffsetDone_OFF            (19)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompOffsetDone_WID            ( 1)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompOffsetDone_MSK            (0x00080000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompOffsetDone_MIN            (0)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompOffsetDone_MAX            (1) // 0x00000001
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompOffsetDone_DEF            (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompOffsetDone_HSH            (0x01131F5C)

  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompXLoopsDone_OFF            (20)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompXLoopsDone_WID            ( 1)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompXLoopsDone_MSK            (0x00100000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompXLoopsDone_MIN            (0)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompXLoopsDone_MAX            (1) // 0x00000001
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompXLoopsDone_DEF            (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_VTCompXLoopsDone_HSH            (0x01141F5C)

  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_Spare_OFF                       (21)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_Spare_WID                       (11)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_Spare_MSK                       (0xFFE00000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_Spare_MIN                       (0)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_Spare_MAX                       (2047) // 0x000007FF
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_Spare_DEF                       (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOSTATUS1_Spare_HSH                       (0x0B151F5C)

#define DDRPHY_COMP_CR_DCCDCOCONTROL2_REG                              (0x00001F60)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DcoEnOvrd_OFF                  ( 0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DcoEnOvrd_WID                  ( 1)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DcoEnOvrd_MSK                  (0x00000001)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DcoEnOvrd_MIN                  (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DcoEnOvrd_MAX                  (1) // 0x00000001
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DcoEnOvrd_DEF                  (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DcoEnOvrd_HSH                  (0x01001F60)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_PreDivCntEnOvrd_OFF            ( 1)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_PreDivCntEnOvrd_WID            ( 1)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_PreDivCntEnOvrd_MSK            (0x00000002)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_PreDivCntEnOvrd_MIN            (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_PreDivCntEnOvrd_MAX            (1) // 0x00000001
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_PreDivCntEnOvrd_DEF            (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_PreDivCntEnOvrd_HSH            (0x01011F60)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_PostDivCntEnOvrd_OFF           ( 2)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_PostDivCntEnOvrd_WID           ( 1)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_PostDivCntEnOvrd_MSK           (0x00000004)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_PostDivCntEnOvrd_MIN           (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_PostDivCntEnOvrd_MAX           (1) // 0x00000001
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_PostDivCntEnOvrd_DEF           (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_PostDivCntEnOvrd_HSH           (0x01021F60)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_LfsrEnOvrd_OFF                 ( 3)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_LfsrEnOvrd_WID                 ( 1)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_LfsrEnOvrd_MSK                 (0x00000008)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_LfsrEnOvrd_MIN                 (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_LfsrEnOvrd_MAX                 (1) // 0x00000001
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_LfsrEnOvrd_DEF                 (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_LfsrEnOvrd_HSH                 (0x01031F60)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_Spare_OFF                      ( 4)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_Spare_WID                      (10)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_Spare_MSK                      (0x00003FF0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_Spare_MIN                      (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_Spare_MAX                      (1023) // 0x000003FF
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_Spare_DEF                      (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_Spare_HSH                      (0x0A041F60)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicSyncVal_OFF       (14)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicSyncVal_WID       ( 6)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicSyncVal_MSK       (0x000FC000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicSyncVal_MIN       (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicSyncVal_MAX       (63) // 0x0000003F
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicSyncVal_DEF       (0x00000020)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicSyncVal_HSH       (0x060E1F60)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicCntVal_OFF        (20)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicCntVal_WID        (11)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicCntVal_MSK        (0x7FF00000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicCntVal_MIN        (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicCntVal_MAX        (2047) // 0x000007FF
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicCntVal_DEF        (0x000000C8)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicCntVal_HSH        (0x0B141F60)

  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicMode_OFF          (31)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicMode_WID          ( 1)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicMode_MSK          (0x80000000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicMode_MIN          (0)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicMode_MAX          (1) // 0x00000001
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicMode_DEF          (0x00000000)
  #define DDRPHY_COMP_CR_DCCDCOCONTROL2_DeterministicMode_HSH          (0x011F1F60)
#pragma pack(pop)
#endif
