#ifndef __MrcMcRegisterIcl0xxx_h__
#define __MrcMcRegisterIcl0xxx_h__
/** @file
  This file was automatically generated. Modify at your own risk.
  Note that no error checking is done in these functions so ensure that the correct values are passed.

@copyright
  Copyright (c) 2010 - 2019 Intel Corporation. All rights reserved
  This software and associated documentation (if any) is furnished
  under a license and may only be used or copied in accordance
  with the terms of the license. Except as permitted by the
  license, no part of this software or documentation may be
  reproduced, stored in a retrieval system, or transmitted in any
  form or by any means without the express written consent of
  Intel Corporation.
  This file contains an 'Intel Peripheral Driver' and is uniquely
  identified as "Intel Reference Module" and is licensed for Intel
  CPUs and chipsets under the terms of your license agreement with
  Intel or your vendor. This file may be modified by the user, subject
  to additional terms of the license agreement.

@par Specification Reference:
**/

#pragma pack(push, 1)


#define DDRDATA0CH0_CR_RXCONTROL0RANK0_REG                             (0x00000000)

  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B000000)

  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B0000)

  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07120000)

  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07190000)

#define DDRDATA0CH0_CR_RXCONTROL0RANK1_REG                             (0x00000004)

  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B000004)

  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B0004)

  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07120004)

  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07190004)

#define DDRDATA0CH0_CR_RXCONTROL0RANK2_REG                             (0x00000008)

  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B000008)

  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B0008)

  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07120008)

  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07190008)

#define DDRDATA0CH0_CR_RXCONTROL0RANK3_REG                             (0x0000000C)

  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B00000C)

  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B000C)

  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x0712000C)

  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x0719000C)

#define DDRDATA0CH0_CR_RXCONTROL1RANK0_REG                             (0x00000010)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06000010)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06060010)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C0010)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06120010)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02180010)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A0010)

#define DDRDATA0CH0_CR_RXCONTROL1RANK1_REG                             (0x00000014)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06000014)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06060014)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C0014)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06120014)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02180014)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A0014)

#define DDRDATA0CH0_CR_RXCONTROL1RANK2_REG                             (0x00000018)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06000018)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06060018)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C0018)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06120018)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02180018)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A0018)

#define DDRDATA0CH0_CR_RXCONTROL1RANK3_REG                             (0x0000001C)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x0600001C)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x0606001C)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C001C)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x0612001C)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x0218001C)

  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A001C)

#define DDRDATA0CH0_CR_TXTRAINRANK0_REG                                (0x00000020)

  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A000020)

  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A0020)

  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxEqualization_HSH               (0x06140020)

  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A0020)

  #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E0020)

#define DDRDATA0CH0_CR_TXTRAINRANK1_REG                                (0x00000024)

  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A000024)

  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A0024)

  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxEqualization_HSH               (0x06140024)

  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A0024)

  #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C0024)

#define DDRDATA0CH0_CR_TXTRAINRANK2_REG                                (0x00000028)

  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A000028)

  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A0028)

  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_TxEqualization_HSH               (0x06140028)

  #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A0028)

#define DDRDATA0CH0_CR_TXTRAINRANK3_REG                                (0x0000002C)

  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A00002C)

  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A002C)

  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_TxEqualization_HSH               (0x0614002C)

  #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA0CH0_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A002C)

#define DDRDATA0CH0_CR_TXPERBITLOWRANK0_REG                            (0x00000030)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x06000030)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x06060030)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C0030)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x06120030)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x08180030)

#define DDRDATA0CH0_CR_TXPERBITLOWRANK1_REG                            (0x00000034)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x06000034)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x06060034)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C0034)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x06120034)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x08180034)

#define DDRDATA0CH0_CR_TXPERBITLOWRANK2_REG                            (0x00000038)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x06000038)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x06060038)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C0038)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x06120038)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x08180038)

#define DDRDATA0CH0_CR_TXPERBITLOWRANK3_REG                            (0x0000003C)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x0600003C)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x0606003C)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C003C)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x0612003C)

  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x0818003C)

#define DDRDATA0CH0_CR_RCOMPDATA0_REG                                  (0x00000040)

  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x06000040)

  #define DDRDATA0CH0_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA0CH0_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA0CH0_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA0CH0_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA0CH0_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA0CH0_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA0CH0_CR_RCOMPDATA0_Rsvd_HSH                           (0x08060040)

  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA0CH0_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E0040)

  #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA0CH0_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x05140040)

  #define DDRDATA0CH0_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA0CH0_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA0CH0_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA0CH0_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA0CH0_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA0CH0_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA0CH0_CR_RCOMPDATA0_Spare_HSH                          (0x07190040)

#define DDRDATA0CH0_CR_RCOMPDATA1_REG                                  (0x00000044)

  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x06000044)

  #define DDRDATA0CH0_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA0CH0_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA0CH0_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA0CH0_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA0CH0_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA0CH0_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA0CH0_CR_RCOMPDATA1_spare_HSH                          (0x14060044)

  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA0CH0_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A0044)

#define DDRDATA0CH0_CR_DDRCRDATACONTROL8_REG                           (0x00000048)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x02000048)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x02020048)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x02040048)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x02060048)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x01080048)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL8_spare_HSH                   (0x17090048)

#define DDRDATA0CH0_CR_RCOMPDATA2_REG                                  (0x0000004C)

  #define DDRDATA0CH0_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA0CH0_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA0CH0_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA0CH0_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA0CH0_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA0CH0_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x0800004C)

  #define DDRDATA0CH0_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA0CH0_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA0CH0_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA0CH0_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA0CH0_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA0CH0_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x0808004C)

  #define DDRDATA0CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA0CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA0CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA0CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA0CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA0CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x0610004C)

  #define DDRDATA0CH0_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA0CH0_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA0CH0_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA0CH0_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA0CH0_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA0CH0_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA0CH0_CR_RCOMPDATA2_Spare_HSH                          (0x0A16004C)

#define DDRDATA0CH0_CR_RXCONTROL2RANK0_REG                             (0x00000050)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x06000050)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x06060050)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C0050)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x05110050)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x05160050)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B0050)

#define DDRDATA0CH0_CR_RXCONTROL2RANK1_REG                             (0x00000054)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x06000054)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x06060054)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C0054)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x05110054)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x05160054)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B0054)

#define DDRDATA0CH0_CR_RXCONTROL2RANK2_REG                             (0x00000058)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x06000058)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x06060058)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C0058)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x05110058)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x05160058)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B0058)

#define DDRDATA0CH0_CR_RXCONTROL2RANK3_REG                             (0x0000005C)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x0600005C)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x0606005C)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C005C)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x0511005C)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x0516005C)

  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B005C)

#define DDRDATA0CH0_CR_DATATRAINFEEDBACK_REG                           (0x00000060)

  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x09000060)

  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA0CH0_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x17090060)

#define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_REG                         (0x00000068)

  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x86000068)

  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x86060068)

  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C0068)

  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x85110068)

  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x05160068)

  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B0068)

#define DDRDATA0CH0_CR_DDRCRDATACONTROL1_REG                           (0x0000006C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x8400006C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x0204006C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x0106006C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x0307006C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A006C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E006C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x0313006C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x8516006C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B006C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E006C)

#define DDRDATA0CH0_CR_DDRCRDATACONTROL2_REG                           (0x00000070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x05000070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x01050070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x01060070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x01070070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x01080070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x04090070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D0070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x01120070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x01130070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x01140070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x01150070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x01160070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x01170070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x01180070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x01190070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A0070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D0070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E0070)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F0070)

#define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x0000007C)

  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x8600007C)

  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x8706007C)

  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D007C)

  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x8613007C)

  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x8719007C)

#define DDRDATA0CH0_CR_DDRCRDATACONTROL0_REG                           (0x00000080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01000080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01010080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01020080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01030080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01040080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01050080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01060080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01070080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01080080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01090080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A0080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B0080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C0080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D0080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F0080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02130080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01150080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01160080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01170080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01180080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01190080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A0080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B0080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C0080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D0080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E0080)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F0080)

#define DDRDATA0CH0_CR_DDRCRDATACONTROL3_REG                           (0x00000088)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04000088)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02040088)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01060088)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01070088)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86080088)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E0088)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F0088)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03100088)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01130088)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03140088)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01170088)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01180088)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01190088)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A0088)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E0088)

#define DDRDATA0CH0_CR_DDRCRDATACONTROL4_REG                           (0x0000008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x0100008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x0101008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x0302008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x0105008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x0106008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x0107008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x0108008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x0209008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x0110008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x0111008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x0112008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x0513008C)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x0518008C)

  // Keep for ICL A0 compatibility
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_LeakerComp_OFF              (29)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_LeakerComp_WID              ( 3)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_LeakerComp_MSK              (0xE0000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_LeakerComp_MIN              (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_LeakerComp_DEF              (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL4_LeakerComp_HSH              (0x031D008C)

#define DDRDATA0CH0_CR_DDRCRDATACONTROL5_REG                           (0x00000090)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08000090)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01080090)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02090090)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B0090)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F0090)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08100090)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08180090)

#define DDRDATA0CH0_CR_DDRCRDATACONTROL6_REG                           (0x00000094)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01000094)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02010094)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01030094)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05040094)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01090094)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A0094)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B0094)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C0094)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E0094)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F0094)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08100094)

  // Manual edit - bit [1] of RxBiasCtl1 is the MSB of DataControl4.biasrcomp
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_BiasRcompMsb_OFF            (17)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_BiasRcompMsb_WID            ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_BiasRcompMsb_MSK            (0x00020000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_BiasRcompMsb_MIN            (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_BiasRcompMsb_MAX            (1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_BiasRcompMsb_DEF            (1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_BiasRcompMsb_HSH            (0x01110094)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01180094)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01190094)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A0094)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D0094)

#define DDRDATA0CH0_CR_DDRCRDATACONTROL7_REG                           (0x00000098)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06000098)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06060098)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C0098)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06120098)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04180098)

  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA0CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C0098)

#define DDRDATA0CH0_CR_DELTADQSRANK0_REG                               (0x0000009C)

  #define DDRDATA0CH0_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA0CH0_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA0CH0_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA0CH0_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA0CH0_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA0CH0_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A00009C)

  #define DDRDATA0CH0_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA0CH0_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA0CH0_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA0CH0_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA0CH0_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA0CH0_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA0CH0_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A009C)

#define DDRDATA0CH0_CR_DELTADQSRANK1_REG                               (0x000000A0)

  #define DDRDATA0CH0_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA0CH0_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA0CH0_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA0CH0_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA0CH0_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA0CH0_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A0000A0)

  #define DDRDATA0CH0_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA0CH0_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA0CH0_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA0CH0_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA0CH0_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA0CH0_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA0CH0_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A00A0)

#define DDRDATA0CH0_CR_DELTADQSRANK2_REG                               (0x000000A4)

  #define DDRDATA0CH0_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA0CH0_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA0CH0_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA0CH0_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA0CH0_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA0CH0_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A0000A4)

  #define DDRDATA0CH0_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA0CH0_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA0CH0_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA0CH0_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA0CH0_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA0CH0_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA0CH0_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A00A4)

#define DDRDATA0CH0_CR_DELTADQSRANK3_REG                               (0x000000A8)

  #define DDRDATA0CH0_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA0CH0_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA0CH0_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA0CH0_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA0CH0_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA0CH0_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A0000A8)

  #define DDRDATA0CH0_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA0CH0_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA0CH0_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA0CH0_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA0CH0_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA0CH0_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA0CH0_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A00A8)

#define DDRDATA0CH0_CR_RXCONTROL3RANK0_REG                             (0x000000AC)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x060000AC)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x060600AC)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C00AC)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x051100AC)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x051600AC)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B00AC)

#define DDRDATA0CH0_CR_RXCONTROL3RANK1_REG                             (0x000000B0)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x060000B0)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x060600B0)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C00B0)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x051100B0)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x051600B0)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B00B0)

#define DDRDATA0CH0_CR_RXCONTROL3RANK2_REG                             (0x000000B4)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x060000B4)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x060600B4)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C00B4)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x051100B4)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x051600B4)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B00B4)

#define DDRDATA0CH0_CR_RXCONTROL3RANK3_REG                             (0x000000B8)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x060000B8)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x060600B8)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C00B8)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x051100B8)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x051600B8)

  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B00B8)

#define DDRDATA0CH0_CR_TXPERBITHIRANK0_REG                             (0x000000BC)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x060000BC)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x060600BC)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C00BC)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x061200BC)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK0_Spare_HSH                     (0x081800BC)

#define DDRDATA0CH0_CR_TXPERBITHIRANK1_REG                             (0x000000C0)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x060000C0)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x060600C0)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C00C0)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x061200C0)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK1_Spare_HSH                     (0x081800C0)

#define DDRDATA0CH0_CR_TXPERBITHIRANK2_REG                             (0x000000C4)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x060000C4)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x060600C4)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C00C4)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x061200C4)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK2_Spare_HSH                     (0x081800C4)

#define DDRDATA0CH0_CR_TXPERBITHIRANK3_REG                             (0x000000C8)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x060000C8)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x060600C8)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C00C8)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x061200C8)

  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_TXPERBITHIRANK3_Spare_HSH                     (0x081800C8)

#define DDRDATA0CH0_CR_DCCDATACONTROL0_REG                             (0x000000CC)

  #define DDRDATA0CH0_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x010000CC)

  #define DDRDATA0CH0_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x020100CC)

  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x010300CC)

  #define DDRDATA0CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x020400CC)

  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x070600CC)

  #define DDRDATA0CH0_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D00CC)

  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA0CH0_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C00CC)

#define DDRDATA0CH0_CR_DCCDATACONTROL1_REG                             (0x000000D0)

  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x060000D0)

  #define DDRDATA0CH0_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x020600D0)

  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x040800D0)

  #define DDRDATA0CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C00D0)

  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E00D0)

  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F00D0)

  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F1000D0)

  #define DDRDATA0CH0_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F00D0)

#define DDRDATA0CH0_CR_DCCDATACONTROL2_REG                             (0x000000D4)

  #define DDRDATA0CH0_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x060000D4)

  #define DDRDATA0CH0_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x030600D4)

  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D0900D4)

  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x051600D4)

  #define DDRDATA0CH0_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B00D4)

  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C00D4)

#define DDRDATA0CH0_CR_DCCDATACONTROL3_REG                             (0x000000D8)

  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B0000D8)

  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B00D8)

  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x091400D8)

  #define DDRDATA0CH0_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D00D8)

#define DDRDATA0CH0_CR_DCCDATACONTROL4_REG                             (0x000000DC)

  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x090000DC)

  #define DDRDATA0CH0_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_Spare_HSH                     (0x010900DC)

  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A00DC)

  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x061000DC)

  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x061600DC)

  #define DDRDATA0CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C00DC)

#define DDRDATA0CH0_CR_DCCDATACONTROL5_REG                             (0x000000E0)

  #define DDRDATA0CH0_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_Spare_HSH                     (0x020000E0)

  #define DDRDATA0CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x010200E0)

  #define DDRDATA0CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x060300E0)

  #define DDRDATA0CH0_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x050900E0)

  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E00E0)

  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B1400E0)

  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F00E0)

#define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_REG                         (0x000000E4)

  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B0000E4)

  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B00E4)

  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x091400E4)

  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D00E4)

#define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_REG                         (0x000000E8)

  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x090000E8)

  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x010900E8)

  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A00E8)

  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B00E8)

  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A00E8)

  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B00E8)

#define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_REG                         (0x000000EC)

  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x100000EC)

  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x071000EC)

  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x071700EC)

  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E00EC)

#define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x000000F0)

  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B0000F0)

  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B00F0)

  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C00F0)

#define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x000000F4)

  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x090000F4)

  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x110900F4)

  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A00F4)

#define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x000000F8)

  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x090000F8)

  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x110900F8)

  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A00F8)

#define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x000000FC)

  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x090000FC)

  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x110900FC)

  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A00FC)

#define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_REG                        (0x00000100)

  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06000100)

  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06060100)

  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C0100)

  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06120100)

  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07180100)

  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F0100)

#define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00000104)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06000104)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06060104)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C0104)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06120104)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06180104)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E0104)

#define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00000108)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06000108)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06060108)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C0108)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06120108)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06180108)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E0108)

#define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_REG                       (0x0000010C)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x0600010C)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x0606010C)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C010C)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x0612010C)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x0618010C)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E010C)

#define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00000110)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06000110)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06060110)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C0110)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06120110)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06180110)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E0110)

#define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00000114)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06000114)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06060114)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C0114)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06120114)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06180114)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E0114)

#define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00000118)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06000118)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06060118)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C0118)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06120118)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02180118)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A0118)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D0118)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E0118)

#define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_REG                       (0x0000011C)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x0600011C)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x0606011C)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C011C)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x0612011C)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x0618011C)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E011C)

#define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_REG                       (0x00000120)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x06000120)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x06060120)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C0120)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x06120120)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x06180120)

  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA0CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E0120)

#define DDRDATA0CH0_CR_DCCDATADCCPILUT0_REG                            (0x00000124)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x06000124)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x06060124)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C0124)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x06120124)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x06180124)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E0124)

#define DDRDATA0CH0_CR_DCCDATADCCPILUT1_REG                            (0x00000128)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x06000128)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x06060128)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C0128)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x06120128)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x06180128)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E0128)

#define DDRDATA0CH0_CR_DCCDATADCCPILUT2_REG                            (0x0000012C)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x0600012C)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x0606012C)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C012C)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x0612012C)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x0618012C)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E012C)

#define DDRDATA0CH0_CR_DCCDATADCCPILUT3_REG                            (0x00000130)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x06000130)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x06060130)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C0130)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x06120130)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x06180130)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E0130)

#define DDRDATA0CH0_CR_DCCDATADCCPILUT4_REG                            (0x00000134)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x06000134)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x06060134)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C0134)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x06120134)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x06180134)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E0134)

#define DDRDATA0CH0_CR_DCCDATADCCPILUT5_REG                            (0x00000138)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x06000138)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x06060138)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C0138)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x06120138)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x06180138)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E0138)

#define DDRDATA0CH0_CR_DCCDATADCCPILUT6_REG                            (0x0000013C)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x0600013C)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x0606013C)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C013C)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x0612013C)

  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH0_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x0818013C)

#define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_REG                        (0x00000140)

  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x06000140)

  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x06060140)

  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C0140)

  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x06120140)

  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x06180140)

  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E0140)

#define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_REG                        (0x00000144)

  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x06000144)

  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x06060144)

  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C0144)

  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x06120144)

  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x06180144)

  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E0144)

#define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x00000148)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x06000148)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x06060148)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C0148)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x06120148)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x02180148)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A0148)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C0148)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E0148)

#define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x0000014C)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x0600014C)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x0606014C)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C014C)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x0612014C)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x0818014C)

#define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x00000150)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x06000150)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x06060150)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C0150)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x06120150)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x06180150)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E0150)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F0150)

#define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x00000154)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x06000154)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x06060154)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C0154)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x06120154)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x06180154)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E0154)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F0154)

#define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x00000158)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x06000158)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x06060158)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C0158)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x06120158)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x06180158)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E0158)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F0158)

#define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x0000015C)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x0600015C)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x0606015C)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C015C)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x0612015C)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x0618015C)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E015C)

  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA0CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F015C)

#define DDRDATA0CH1_CR_RXCONTROL0RANK0_REG                             (0x00000180)

  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B000180)

  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B0180)

  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07120180)

  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07190180)

#define DDRDATA0CH1_CR_RXCONTROL0RANK1_REG                             (0x00000184)

  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B000184)

  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B0184)

  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07120184)

  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07190184)

#define DDRDATA0CH1_CR_RXCONTROL0RANK2_REG                             (0x00000188)

  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B000188)

  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B0188)

  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07120188)

  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07190188)

#define DDRDATA0CH1_CR_RXCONTROL0RANK3_REG                             (0x0000018C)

  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B00018C)

  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B018C)

  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x0712018C)

  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x0719018C)

#define DDRDATA0CH1_CR_RXCONTROL1RANK0_REG                             (0x00000190)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06000190)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06060190)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C0190)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06120190)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02180190)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A0190)

#define DDRDATA0CH1_CR_RXCONTROL1RANK1_REG                             (0x00000194)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06000194)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06060194)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C0194)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06120194)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02180194)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A0194)

#define DDRDATA0CH1_CR_RXCONTROL1RANK2_REG                             (0x00000198)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06000198)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06060198)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C0198)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06120198)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02180198)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A0198)

#define DDRDATA0CH1_CR_RXCONTROL1RANK3_REG                             (0x0000019C)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x0600019C)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x0606019C)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C019C)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x0612019C)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x0218019C)

  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A019C)

#define DDRDATA0CH1_CR_TXTRAINRANK0_REG                                (0x000001A0)

  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A0001A0)

  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A01A0)

  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxEqualization_HSH               (0x061401A0)

  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A01A0)

  #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E01A0)

#define DDRDATA0CH1_CR_TXTRAINRANK1_REG                                (0x000001A4)

  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A0001A4)

  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A01A4)

  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxEqualization_HSH               (0x061401A4)

  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A01A4)

  #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C01A4)

#define DDRDATA0CH1_CR_TXTRAINRANK2_REG                                (0x000001A8)

  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A0001A8)

  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A01A8)

  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_TxEqualization_HSH               (0x061401A8)

  #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A01A8)

#define DDRDATA0CH1_CR_TXTRAINRANK3_REG                                (0x000001AC)

  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A0001AC)

  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A01AC)

  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_TxEqualization_HSH               (0x061401AC)

  #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA0CH1_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A01AC)

#define DDRDATA0CH1_CR_TXPERBITLOWRANK0_REG                            (0x000001B0)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x060001B0)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x060601B0)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C01B0)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x061201B0)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x081801B0)

#define DDRDATA0CH1_CR_TXPERBITLOWRANK1_REG                            (0x000001B4)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x060001B4)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x060601B4)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C01B4)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x061201B4)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x081801B4)

#define DDRDATA0CH1_CR_TXPERBITLOWRANK2_REG                            (0x000001B8)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x060001B8)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x060601B8)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C01B8)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x061201B8)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x081801B8)

#define DDRDATA0CH1_CR_TXPERBITLOWRANK3_REG                            (0x000001BC)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x060001BC)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x060601BC)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C01BC)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x061201BC)

  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x081801BC)

#define DDRDATA0CH1_CR_RCOMPDATA0_REG                                  (0x000001C0)

  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x060001C0)

  #define DDRDATA0CH1_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA0CH1_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA0CH1_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA0CH1_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA0CH1_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA0CH1_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA0CH1_CR_RCOMPDATA0_Rsvd_HSH                           (0x080601C0)

  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA0CH1_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E01C0)

  #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA0CH1_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x051401C0)

  #define DDRDATA0CH1_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA0CH1_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA0CH1_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA0CH1_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA0CH1_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA0CH1_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA0CH1_CR_RCOMPDATA0_Spare_HSH                          (0x071901C0)

#define DDRDATA0CH1_CR_RCOMPDATA1_REG                                  (0x000001C4)

  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x060001C4)

  #define DDRDATA0CH1_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA0CH1_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA0CH1_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA0CH1_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA0CH1_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA0CH1_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA0CH1_CR_RCOMPDATA1_spare_HSH                          (0x140601C4)

  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA0CH1_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A01C4)

#define DDRDATA0CH1_CR_DDRCRDATACONTROL8_REG                           (0x000001C8)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x020001C8)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x020201C8)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x020401C8)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x020601C8)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x010801C8)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL8_spare_HSH                   (0x170901C8)

#define DDRDATA0CH1_CR_RCOMPDATA2_REG                                  (0x000001CC)

  #define DDRDATA0CH1_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA0CH1_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA0CH1_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA0CH1_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA0CH1_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA0CH1_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x080001CC)

  #define DDRDATA0CH1_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA0CH1_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA0CH1_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA0CH1_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA0CH1_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA0CH1_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x080801CC)

  #define DDRDATA0CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA0CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA0CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA0CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA0CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA0CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x061001CC)

  #define DDRDATA0CH1_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA0CH1_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA0CH1_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA0CH1_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA0CH1_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA0CH1_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA0CH1_CR_RCOMPDATA2_Spare_HSH                          (0x0A1601CC)

#define DDRDATA0CH1_CR_RXCONTROL2RANK0_REG                             (0x000001D0)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x060001D0)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x060601D0)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C01D0)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x051101D0)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x051601D0)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B01D0)

#define DDRDATA0CH1_CR_RXCONTROL2RANK1_REG                             (0x000001D4)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x060001D4)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x060601D4)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C01D4)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x051101D4)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x051601D4)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B01D4)

#define DDRDATA0CH1_CR_RXCONTROL2RANK2_REG                             (0x000001D8)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x060001D8)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x060601D8)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C01D8)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x051101D8)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x051601D8)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B01D8)

#define DDRDATA0CH1_CR_RXCONTROL2RANK3_REG                             (0x000001DC)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x060001DC)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x060601DC)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C01DC)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x051101DC)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x051601DC)

  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B01DC)

#define DDRDATA0CH1_CR_DATATRAINFEEDBACK_REG                           (0x000001E0)

  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x090001E0)

  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA0CH1_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x170901E0)

#define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_REG                         (0x000001E8)

  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x860001E8)

  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x860601E8)

  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C01E8)

  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x851101E8)

  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x051601E8)

  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B01E8)

#define DDRDATA0CH1_CR_DDRCRDATACONTROL1_REG                           (0x000001EC)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x840001EC)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x020401EC)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x010601EC)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x030701EC)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A01EC)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E01EC)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x031301EC)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x851601EC)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B01EC)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E01EC)

#define DDRDATA0CH1_CR_DDRCRDATACONTROL2_REG                           (0x000001F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x050001F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x010501F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x010601F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x010701F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x010801F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x040901F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D01F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x011201F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x011301F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x011401F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x011501F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x011601F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x011701F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x011801F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x011901F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A01F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D01F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E01F0)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F01F0)

#define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x000001FC)

  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x860001FC)

  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x870601FC)

  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D01FC)

  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x861301FC)

  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x871901FC)

#define DDRDATA0CH1_CR_DDRCRDATACONTROL0_REG                           (0x00000200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01000200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01010200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01020200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01030200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01040200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01050200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01060200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01070200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01080200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01090200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A0200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B0200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C0200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D0200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F0200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02130200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01150200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01160200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01170200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01180200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01190200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A0200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B0200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C0200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D0200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E0200)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F0200)

#define DDRDATA0CH1_CR_DDRCRDATACONTROL3_REG                           (0x00000208)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04000208)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02040208)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01060208)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01070208)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86080208)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E0208)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F0208)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03100208)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01130208)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03140208)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01170208)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01180208)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01190208)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A0208)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E0208)

#define DDRDATA0CH1_CR_DDRCRDATACONTROL4_REG                           (0x0000020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x0100020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x0101020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x0302020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x0105020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x0106020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x0107020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x0108020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x0209020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x0110020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x0111020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x0112020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x0513020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x0518020C)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_spare2_OFF                  (29)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_spare2_WID                  ( 3)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_spare2_MSK                  (0xE0000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_spare2_MIN                  (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_spare2_MAX                  (7) // 0x00000007
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_spare2_DEF                  (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL4_spare2_HSH                  (0x031D020C)

#define DDRDATA0CH1_CR_DDRCRDATACONTROL5_REG                           (0x00000210)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08000210)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01080210)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02090210)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B0210)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F0210)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08100210)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08180210)

#define DDRDATA0CH1_CR_DDRCRDATACONTROL6_REG                           (0x00000214)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01000214)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02010214)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01030214)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05040214)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01090214)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A0214)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B0214)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C0214)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E0214)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F0214)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08100214)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01180214)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01190214)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A0214)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D0214)

#define DDRDATA0CH1_CR_DDRCRDATACONTROL7_REG                           (0x00000218)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06000218)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06060218)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C0218)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06120218)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04180218)

  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA0CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C0218)

#define DDRDATA0CH1_CR_DELTADQSRANK0_REG                               (0x0000021C)

  #define DDRDATA0CH1_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA0CH1_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA0CH1_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA0CH1_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA0CH1_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA0CH1_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A00021C)

  #define DDRDATA0CH1_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA0CH1_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA0CH1_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA0CH1_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA0CH1_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA0CH1_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA0CH1_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A021C)

#define DDRDATA0CH1_CR_DELTADQSRANK1_REG                               (0x00000220)

  #define DDRDATA0CH1_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA0CH1_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA0CH1_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA0CH1_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA0CH1_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA0CH1_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A000220)

  #define DDRDATA0CH1_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA0CH1_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA0CH1_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA0CH1_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA0CH1_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA0CH1_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA0CH1_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A0220)

#define DDRDATA0CH1_CR_DELTADQSRANK2_REG                               (0x00000224)

  #define DDRDATA0CH1_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA0CH1_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA0CH1_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA0CH1_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA0CH1_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA0CH1_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A000224)

  #define DDRDATA0CH1_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA0CH1_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA0CH1_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA0CH1_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA0CH1_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA0CH1_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA0CH1_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A0224)

#define DDRDATA0CH1_CR_DELTADQSRANK3_REG                               (0x00000228)

  #define DDRDATA0CH1_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA0CH1_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA0CH1_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA0CH1_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA0CH1_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA0CH1_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A000228)

  #define DDRDATA0CH1_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA0CH1_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA0CH1_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA0CH1_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA0CH1_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA0CH1_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA0CH1_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A0228)

#define DDRDATA0CH1_CR_RXCONTROL3RANK0_REG                             (0x0000022C)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x0600022C)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x0606022C)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C022C)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x0511022C)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x0516022C)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B022C)

#define DDRDATA0CH1_CR_RXCONTROL3RANK1_REG                             (0x00000230)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x06000230)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x06060230)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C0230)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x05110230)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x05160230)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B0230)

#define DDRDATA0CH1_CR_RXCONTROL3RANK2_REG                             (0x00000234)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x06000234)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x06060234)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C0234)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x05110234)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x05160234)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B0234)

#define DDRDATA0CH1_CR_RXCONTROL3RANK3_REG                             (0x00000238)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x06000238)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x06060238)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C0238)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x05110238)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x05160238)

  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA0CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B0238)

#define DDRDATA0CH1_CR_TXPERBITHIRANK0_REG                             (0x0000023C)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x0600023C)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x0606023C)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C023C)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x0612023C)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK0_Spare_HSH                     (0x0818023C)

#define DDRDATA0CH1_CR_TXPERBITHIRANK1_REG                             (0x00000240)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x06000240)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x06060240)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C0240)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x06120240)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK1_Spare_HSH                     (0x08180240)

#define DDRDATA0CH1_CR_TXPERBITHIRANK2_REG                             (0x00000244)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x06000244)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x06060244)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C0244)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x06120244)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK2_Spare_HSH                     (0x08180244)

#define DDRDATA0CH1_CR_TXPERBITHIRANK3_REG                             (0x00000248)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x06000248)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x06060248)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C0248)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x06120248)

  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_TXPERBITHIRANK3_Spare_HSH                     (0x08180248)

#define DDRDATA0CH1_CR_DCCDATACONTROL0_REG                             (0x0000024C)

  #define DDRDATA0CH1_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x0100024C)

  #define DDRDATA0CH1_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x0201024C)

  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x0103024C)

  #define DDRDATA0CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x0204024C)

  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x0706024C)

  #define DDRDATA0CH1_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D024C)

  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA0CH1_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C024C)

#define DDRDATA0CH1_CR_DCCDATACONTROL1_REG                             (0x00000250)

  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x06000250)

  #define DDRDATA0CH1_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x02060250)

  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x04080250)

  #define DDRDATA0CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C0250)

  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E0250)

  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F0250)

  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F100250)

  #define DDRDATA0CH1_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F0250)

#define DDRDATA0CH1_CR_DCCDATACONTROL2_REG                             (0x00000254)

  #define DDRDATA0CH1_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x06000254)

  #define DDRDATA0CH1_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x03060254)

  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D090254)

  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x05160254)

  #define DDRDATA0CH1_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B0254)

  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C0254)

#define DDRDATA0CH1_CR_DCCDATACONTROL3_REG                             (0x00000258)

  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B000258)

  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B0258)

  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x09140258)

  #define DDRDATA0CH1_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D0258)

#define DDRDATA0CH1_CR_DCCDATACONTROL4_REG                             (0x0000025C)

  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x0900025C)

  #define DDRDATA0CH1_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_Spare_HSH                     (0x0109025C)

  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A025C)

  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x0610025C)

  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x0616025C)

  #define DDRDATA0CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C025C)

#define DDRDATA0CH1_CR_DCCDATACONTROL5_REG                             (0x00000260)

  #define DDRDATA0CH1_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_Spare_HSH                     (0x02000260)

  #define DDRDATA0CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x01020260)

  #define DDRDATA0CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x06030260)

  #define DDRDATA0CH1_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x05090260)

  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E0260)

  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B140260)

  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F0260)

#define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_REG                         (0x00000264)

  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B000264)

  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B0264)

  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x09140264)

  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D0264)

#define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_REG                         (0x00000268)

  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x09000268)

  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x01090268)

  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A0268)

  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B0268)

  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A0268)

  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B0268)

#define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_REG                         (0x0000026C)

  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x1000026C)

  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x0710026C)

  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x0717026C)

  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E026C)

#define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x00000270)

  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B000270)

  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B0270)

  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C0270)

#define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x00000274)

  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x09000274)

  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x11090274)

  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A0274)

#define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x00000278)

  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x09000278)

  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x11090278)

  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A0278)

#define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x0000027C)

  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x0900027C)

  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x1109027C)

  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A027C)

#define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_REG                        (0x00000280)

  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06000280)

  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06060280)

  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C0280)

  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06120280)

  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07180280)

  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F0280)

#define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00000284)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06000284)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06060284)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C0284)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06120284)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06180284)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E0284)

#define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00000288)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06000288)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06060288)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C0288)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06120288)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06180288)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E0288)

#define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_REG                       (0x0000028C)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x0600028C)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x0606028C)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C028C)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x0612028C)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x0618028C)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E028C)

#define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00000290)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06000290)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06060290)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C0290)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06120290)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06180290)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E0290)

#define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00000294)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06000294)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06060294)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C0294)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06120294)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06180294)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E0294)

#define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00000298)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06000298)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06060298)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C0298)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06120298)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02180298)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A0298)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D0298)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E0298)

#define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_REG                       (0x0000029C)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x0600029C)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x0606029C)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C029C)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x0612029C)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x0618029C)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E029C)

#define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_REG                       (0x000002A0)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x060002A0)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x060602A0)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C02A0)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x061202A0)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x061802A0)

  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA0CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E02A0)

#define DDRDATA0CH1_CR_DCCDATADCCPILUT0_REG                            (0x000002A4)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x060002A4)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x060602A4)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C02A4)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x061202A4)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x061802A4)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E02A4)

#define DDRDATA0CH1_CR_DCCDATADCCPILUT1_REG                            (0x000002A8)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x060002A8)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x060602A8)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C02A8)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x061202A8)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x061802A8)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E02A8)

#define DDRDATA0CH1_CR_DCCDATADCCPILUT2_REG                            (0x000002AC)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x060002AC)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x060602AC)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C02AC)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x061202AC)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x061802AC)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E02AC)

#define DDRDATA0CH1_CR_DCCDATADCCPILUT3_REG                            (0x000002B0)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x060002B0)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x060602B0)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C02B0)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x061202B0)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x061802B0)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E02B0)

#define DDRDATA0CH1_CR_DCCDATADCCPILUT4_REG                            (0x000002B4)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x060002B4)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x060602B4)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C02B4)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x061202B4)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x061802B4)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E02B4)

#define DDRDATA0CH1_CR_DCCDATADCCPILUT5_REG                            (0x000002B8)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x060002B8)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x060602B8)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C02B8)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x061202B8)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x061802B8)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E02B8)

#define DDRDATA0CH1_CR_DCCDATADCCPILUT6_REG                            (0x000002BC)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x060002BC)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x060602BC)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C02BC)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x061202BC)

  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA0CH1_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x081802BC)

#define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_REG                        (0x000002C0)

  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x060002C0)

  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x060602C0)

  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C02C0)

  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x061202C0)

  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x061802C0)

  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E02C0)

#define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_REG                        (0x000002C4)

  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x060002C4)

  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x060602C4)

  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C02C4)

  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x061202C4)

  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x061802C4)

  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E02C4)

#define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x000002C8)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x060002C8)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x060602C8)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C02C8)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x061202C8)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x021802C8)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A02C8)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C02C8)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E02C8)

#define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x000002CC)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x060002CC)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x060602CC)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C02CC)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x061202CC)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x081802CC)

#define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x000002D0)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x060002D0)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x060602D0)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C02D0)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x061202D0)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x061802D0)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E02D0)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F02D0)

#define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x000002D4)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x060002D4)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x060602D4)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C02D4)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x061202D4)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x061802D4)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E02D4)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F02D4)

#define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x000002D8)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x060002D8)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x060602D8)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C02D8)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x061202D8)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x061802D8)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E02D8)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F02D8)

#define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x000002DC)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x060002DC)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x060602DC)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C02DC)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x061202DC)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x061802DC)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E02DC)

  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA0CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F02DC)

#define DDRDATA1CH0_CR_RXCONTROL0RANK0_REG                             (0x00000300)

  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B000300)

  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B0300)

  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07120300)

  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07190300)

#define DDRDATA1CH0_CR_RXCONTROL0RANK1_REG                             (0x00000304)

  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B000304)

  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B0304)

  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07120304)

  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07190304)

#define DDRDATA1CH0_CR_RXCONTROL0RANK2_REG                             (0x00000308)

  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B000308)

  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B0308)

  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07120308)

  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07190308)

#define DDRDATA1CH0_CR_RXCONTROL0RANK3_REG                             (0x0000030C)

  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B00030C)

  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B030C)

  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x0712030C)

  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x0719030C)

#define DDRDATA1CH0_CR_RXCONTROL1RANK0_REG                             (0x00000310)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06000310)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06060310)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C0310)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06120310)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02180310)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A0310)

#define DDRDATA1CH0_CR_RXCONTROL1RANK1_REG                             (0x00000314)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06000314)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06060314)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C0314)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06120314)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02180314)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A0314)

#define DDRDATA1CH0_CR_RXCONTROL1RANK2_REG                             (0x00000318)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06000318)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06060318)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C0318)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06120318)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02180318)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A0318)

#define DDRDATA1CH0_CR_RXCONTROL1RANK3_REG                             (0x0000031C)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x0600031C)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x0606031C)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C031C)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x0612031C)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x0218031C)

  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A031C)

#define DDRDATA1CH0_CR_TXTRAINRANK0_REG                                (0x00000320)

  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A000320)

  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A0320)

  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxEqualization_HSH               (0x06140320)

  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A0320)

  #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E0320)

#define DDRDATA1CH0_CR_TXTRAINRANK1_REG                                (0x00000324)

  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A000324)

  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A0324)

  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxEqualization_HSH               (0x06140324)

  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A0324)

  #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C0324)

#define DDRDATA1CH0_CR_TXTRAINRANK2_REG                                (0x00000328)

  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A000328)

  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A0328)

  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_TxEqualization_HSH               (0x06140328)

  #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A0328)

#define DDRDATA1CH0_CR_TXTRAINRANK3_REG                                (0x0000032C)

  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A00032C)

  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A032C)

  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_TxEqualization_HSH               (0x0614032C)

  #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA1CH0_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A032C)

#define DDRDATA1CH0_CR_TXPERBITLOWRANK0_REG                            (0x00000330)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x06000330)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x06060330)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C0330)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x06120330)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x08180330)

#define DDRDATA1CH0_CR_TXPERBITLOWRANK1_REG                            (0x00000334)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x06000334)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x06060334)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C0334)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x06120334)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x08180334)

#define DDRDATA1CH0_CR_TXPERBITLOWRANK2_REG                            (0x00000338)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x06000338)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x06060338)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C0338)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x06120338)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x08180338)

#define DDRDATA1CH0_CR_TXPERBITLOWRANK3_REG                            (0x0000033C)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x0600033C)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x0606033C)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C033C)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x0612033C)

  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x0818033C)

#define DDRDATA1CH0_CR_RCOMPDATA0_REG                                  (0x00000340)

  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x06000340)

  #define DDRDATA1CH0_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA1CH0_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA1CH0_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA1CH0_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA1CH0_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA1CH0_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA1CH0_CR_RCOMPDATA0_Rsvd_HSH                           (0x08060340)

  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA1CH0_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E0340)

  #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA1CH0_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x05140340)

  #define DDRDATA1CH0_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA1CH0_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA1CH0_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA1CH0_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA1CH0_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA1CH0_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA1CH0_CR_RCOMPDATA0_Spare_HSH                          (0x07190340)

#define DDRDATA1CH0_CR_RCOMPDATA1_REG                                  (0x00000344)

  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x06000344)

  #define DDRDATA1CH0_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA1CH0_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA1CH0_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA1CH0_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA1CH0_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA1CH0_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA1CH0_CR_RCOMPDATA1_spare_HSH                          (0x14060344)

  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA1CH0_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A0344)

#define DDRDATA1CH0_CR_DDRCRDATACONTROL8_REG                           (0x00000348)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x02000348)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x02020348)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x02040348)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x02060348)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x01080348)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL8_spare_HSH                   (0x17090348)

#define DDRDATA1CH0_CR_RCOMPDATA2_REG                                  (0x0000034C)

  #define DDRDATA1CH0_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA1CH0_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA1CH0_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA1CH0_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA1CH0_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA1CH0_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x0800034C)

  #define DDRDATA1CH0_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA1CH0_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA1CH0_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA1CH0_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA1CH0_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA1CH0_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x0808034C)

  #define DDRDATA1CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA1CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA1CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA1CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA1CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA1CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x0610034C)

  #define DDRDATA1CH0_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA1CH0_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA1CH0_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA1CH0_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA1CH0_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA1CH0_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA1CH0_CR_RCOMPDATA2_Spare_HSH                          (0x0A16034C)

#define DDRDATA1CH0_CR_RXCONTROL2RANK0_REG                             (0x00000350)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x06000350)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x06060350)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C0350)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x05110350)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x05160350)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B0350)

#define DDRDATA1CH0_CR_RXCONTROL2RANK1_REG                             (0x00000354)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x06000354)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x06060354)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C0354)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x05110354)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x05160354)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B0354)

#define DDRDATA1CH0_CR_RXCONTROL2RANK2_REG                             (0x00000358)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x06000358)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x06060358)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C0358)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x05110358)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x05160358)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B0358)

#define DDRDATA1CH0_CR_RXCONTROL2RANK3_REG                             (0x0000035C)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x0600035C)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x0606035C)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C035C)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x0511035C)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x0516035C)

  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B035C)

#define DDRDATA1CH0_CR_DATATRAINFEEDBACK_REG                           (0x00000360)

  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x09000360)

  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA1CH0_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x17090360)

#define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_REG                         (0x00000368)

  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x86000368)

  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x86060368)

  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C0368)

  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x85110368)

  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x05160368)

  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B0368)

#define DDRDATA1CH0_CR_DDRCRDATACONTROL1_REG                           (0x0000036C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x8400036C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x0204036C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x0106036C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x0307036C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A036C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E036C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x0313036C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x8516036C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B036C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E036C)

#define DDRDATA1CH0_CR_DDRCRDATACONTROL2_REG                           (0x00000370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x05000370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x01050370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x01060370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x01070370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x01080370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x04090370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D0370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x01120370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x01130370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x01140370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x01150370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x01160370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x01170370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x01180370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x01190370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A0370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D0370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E0370)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F0370)

#define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x0000037C)

  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x8600037C)

  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x8706037C)

  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D037C)

  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x8613037C)

  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x8719037C)

#define DDRDATA1CH0_CR_DDRCRDATACONTROL0_REG                           (0x00000380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01000380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01010380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01020380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01030380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01040380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01050380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01060380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01070380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01080380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01090380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A0380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B0380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C0380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D0380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F0380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02130380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01150380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01160380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01170380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01180380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01190380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A0380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B0380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C0380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D0380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E0380)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F0380)

#define DDRDATA1CH0_CR_DDRCRDATACONTROL3_REG                           (0x00000388)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04000388)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02040388)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01060388)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01070388)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86080388)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E0388)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F0388)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03100388)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01130388)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03140388)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01170388)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01180388)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01190388)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A0388)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E0388)

#define DDRDATA1CH0_CR_DDRCRDATACONTROL4_REG                           (0x0000038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x0100038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x0101038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x0302038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x0105038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x0106038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x0107038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x0108038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x0209038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x0110038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x0111038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x0112038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x0513038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x0518038C)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_spare2_OFF                  (29)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_spare2_WID                  ( 3)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_spare2_MSK                  (0xE0000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_spare2_MIN                  (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_spare2_MAX                  (7) // 0x00000007
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_spare2_DEF                  (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL4_spare2_HSH                  (0x031D038C)

#define DDRDATA1CH0_CR_DDRCRDATACONTROL5_REG                           (0x00000390)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08000390)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01080390)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02090390)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B0390)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F0390)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08100390)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08180390)

#define DDRDATA1CH0_CR_DDRCRDATACONTROL6_REG                           (0x00000394)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01000394)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02010394)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01030394)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05040394)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01090394)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A0394)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B0394)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C0394)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E0394)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F0394)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08100394)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01180394)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01190394)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A0394)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D0394)

#define DDRDATA1CH0_CR_DDRCRDATACONTROL7_REG                           (0x00000398)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06000398)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06060398)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C0398)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06120398)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04180398)

  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA1CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C0398)

#define DDRDATA1CH0_CR_DELTADQSRANK0_REG                               (0x0000039C)

  #define DDRDATA1CH0_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA1CH0_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA1CH0_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA1CH0_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA1CH0_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA1CH0_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A00039C)

  #define DDRDATA1CH0_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA1CH0_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA1CH0_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA1CH0_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA1CH0_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA1CH0_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA1CH0_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A039C)

#define DDRDATA1CH0_CR_DELTADQSRANK1_REG                               (0x000003A0)

  #define DDRDATA1CH0_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA1CH0_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA1CH0_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA1CH0_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA1CH0_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA1CH0_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A0003A0)

  #define DDRDATA1CH0_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA1CH0_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA1CH0_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA1CH0_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA1CH0_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA1CH0_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA1CH0_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A03A0)

#define DDRDATA1CH0_CR_DELTADQSRANK2_REG                               (0x000003A4)

  #define DDRDATA1CH0_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA1CH0_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA1CH0_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA1CH0_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA1CH0_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA1CH0_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A0003A4)

  #define DDRDATA1CH0_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA1CH0_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA1CH0_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA1CH0_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA1CH0_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA1CH0_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA1CH0_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A03A4)

#define DDRDATA1CH0_CR_DELTADQSRANK3_REG                               (0x000003A8)

  #define DDRDATA1CH0_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA1CH0_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA1CH0_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA1CH0_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA1CH0_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA1CH0_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A0003A8)

  #define DDRDATA1CH0_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA1CH0_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA1CH0_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA1CH0_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA1CH0_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA1CH0_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA1CH0_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A03A8)

#define DDRDATA1CH0_CR_RXCONTROL3RANK0_REG                             (0x000003AC)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x060003AC)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x060603AC)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C03AC)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x051103AC)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x051603AC)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B03AC)

#define DDRDATA1CH0_CR_RXCONTROL3RANK1_REG                             (0x000003B0)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x060003B0)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x060603B0)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C03B0)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x051103B0)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x051603B0)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B03B0)

#define DDRDATA1CH0_CR_RXCONTROL3RANK2_REG                             (0x000003B4)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x060003B4)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x060603B4)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C03B4)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x051103B4)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x051603B4)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B03B4)

#define DDRDATA1CH0_CR_RXCONTROL3RANK3_REG                             (0x000003B8)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x060003B8)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x060603B8)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C03B8)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x051103B8)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x051603B8)

  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B03B8)

#define DDRDATA1CH0_CR_TXPERBITHIRANK0_REG                             (0x000003BC)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x060003BC)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x060603BC)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C03BC)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x061203BC)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK0_Spare_HSH                     (0x081803BC)

#define DDRDATA1CH0_CR_TXPERBITHIRANK1_REG                             (0x000003C0)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x060003C0)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x060603C0)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C03C0)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x061203C0)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK1_Spare_HSH                     (0x081803C0)

#define DDRDATA1CH0_CR_TXPERBITHIRANK2_REG                             (0x000003C4)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x060003C4)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x060603C4)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C03C4)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x061203C4)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK2_Spare_HSH                     (0x081803C4)

#define DDRDATA1CH0_CR_TXPERBITHIRANK3_REG                             (0x000003C8)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x060003C8)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x060603C8)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C03C8)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x061203C8)

  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_TXPERBITHIRANK3_Spare_HSH                     (0x081803C8)

#define DDRDATA1CH0_CR_DCCDATACONTROL0_REG                             (0x000003CC)

  #define DDRDATA1CH0_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x010003CC)

  #define DDRDATA1CH0_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x020103CC)

  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x010303CC)

  #define DDRDATA1CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x020403CC)

  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x070603CC)

  #define DDRDATA1CH0_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D03CC)

  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA1CH0_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C03CC)

#define DDRDATA1CH0_CR_DCCDATACONTROL1_REG                             (0x000003D0)

  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x060003D0)

  #define DDRDATA1CH0_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x020603D0)

  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x040803D0)

  #define DDRDATA1CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C03D0)

  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E03D0)

  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F03D0)

  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F1003D0)

  #define DDRDATA1CH0_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F03D0)

#define DDRDATA1CH0_CR_DCCDATACONTROL2_REG                             (0x000003D4)

  #define DDRDATA1CH0_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x060003D4)

  #define DDRDATA1CH0_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x030603D4)

  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D0903D4)

  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x051603D4)

  #define DDRDATA1CH0_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B03D4)

  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C03D4)

#define DDRDATA1CH0_CR_DCCDATACONTROL3_REG                             (0x000003D8)

  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B0003D8)

  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B03D8)

  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x091403D8)

  #define DDRDATA1CH0_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D03D8)

#define DDRDATA1CH0_CR_DCCDATACONTROL4_REG                             (0x000003DC)

  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x090003DC)

  #define DDRDATA1CH0_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_Spare_HSH                     (0x010903DC)

  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A03DC)

  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x061003DC)

  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x061603DC)

  #define DDRDATA1CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C03DC)

#define DDRDATA1CH0_CR_DCCDATACONTROL5_REG                             (0x000003E0)

  #define DDRDATA1CH0_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_Spare_HSH                     (0x020003E0)

  #define DDRDATA1CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x010203E0)

  #define DDRDATA1CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x060303E0)

  #define DDRDATA1CH0_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x050903E0)

  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E03E0)

  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B1403E0)

  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F03E0)

#define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_REG                         (0x000003E4)

  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B0003E4)

  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B03E4)

  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x091403E4)

  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D03E4)

#define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_REG                         (0x000003E8)

  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x090003E8)

  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x010903E8)

  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A03E8)

  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B03E8)

  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A03E8)

  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B03E8)

#define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_REG                         (0x000003EC)

  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x100003EC)

  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x071003EC)

  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x071703EC)

  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E03EC)

#define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x000003F0)

  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B0003F0)

  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B03F0)

  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C03F0)

#define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x000003F4)

  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x090003F4)

  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x110903F4)

  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A03F4)

#define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x000003F8)

  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x090003F8)

  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x110903F8)

  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A03F8)

#define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x000003FC)

  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x090003FC)

  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x110903FC)

  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A03FC)

#define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_REG                        (0x00000400)

  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06000400)

  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06060400)

  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C0400)

  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06120400)

  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07180400)

  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F0400)

#define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00000404)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06000404)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06060404)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C0404)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06120404)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06180404)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E0404)

#define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00000408)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06000408)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06060408)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C0408)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06120408)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06180408)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E0408)

#define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_REG                       (0x0000040C)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x0600040C)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x0606040C)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C040C)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x0612040C)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x0618040C)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E040C)

#define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00000410)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06000410)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06060410)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C0410)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06120410)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06180410)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E0410)

#define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00000414)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06000414)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06060414)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C0414)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06120414)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06180414)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E0414)

#define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00000418)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06000418)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06060418)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C0418)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06120418)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02180418)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A0418)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D0418)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E0418)

#define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_REG                       (0x0000041C)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x0600041C)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x0606041C)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C041C)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x0612041C)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x0618041C)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E041C)

#define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_REG                       (0x00000420)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x06000420)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x06060420)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C0420)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x06120420)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x06180420)

  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA1CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E0420)

#define DDRDATA1CH0_CR_DCCDATADCCPILUT0_REG                            (0x00000424)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x06000424)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x06060424)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C0424)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x06120424)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x06180424)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E0424)

#define DDRDATA1CH0_CR_DCCDATADCCPILUT1_REG                            (0x00000428)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x06000428)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x06060428)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C0428)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x06120428)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x06180428)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E0428)

#define DDRDATA1CH0_CR_DCCDATADCCPILUT2_REG                            (0x0000042C)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x0600042C)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x0606042C)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C042C)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x0612042C)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x0618042C)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E042C)

#define DDRDATA1CH0_CR_DCCDATADCCPILUT3_REG                            (0x00000430)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x06000430)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x06060430)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C0430)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x06120430)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x06180430)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E0430)

#define DDRDATA1CH0_CR_DCCDATADCCPILUT4_REG                            (0x00000434)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x06000434)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x06060434)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C0434)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x06120434)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x06180434)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E0434)

#define DDRDATA1CH0_CR_DCCDATADCCPILUT5_REG                            (0x00000438)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x06000438)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x06060438)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C0438)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x06120438)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x06180438)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E0438)

#define DDRDATA1CH0_CR_DCCDATADCCPILUT6_REG                            (0x0000043C)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x0600043C)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x0606043C)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C043C)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x0612043C)

  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH0_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x0818043C)

#define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_REG                        (0x00000440)

  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x06000440)

  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x06060440)

  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C0440)

  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x06120440)

  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x06180440)

  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E0440)

#define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_REG                        (0x00000444)

  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x06000444)

  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x06060444)

  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C0444)

  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x06120444)

  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x06180444)

  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E0444)

#define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x00000448)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x06000448)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x06060448)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C0448)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x06120448)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x02180448)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A0448)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C0448)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E0448)

#define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x0000044C)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x0600044C)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x0606044C)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C044C)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x0612044C)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x0818044C)

#define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x00000450)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x06000450)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x06060450)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C0450)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x06120450)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x06180450)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E0450)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F0450)

#define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x00000454)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x06000454)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x06060454)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C0454)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x06120454)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x06180454)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E0454)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F0454)

#define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x00000458)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x06000458)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x06060458)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C0458)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x06120458)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x06180458)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E0458)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F0458)

#define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x0000045C)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x0600045C)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x0606045C)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C045C)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x0612045C)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x0618045C)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E045C)

  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA1CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F045C)

#define DDRDATA1CH1_CR_RXCONTROL0RANK0_REG                             (0x00000480)

  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B000480)

  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B0480)

  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07120480)

  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07190480)

#define DDRDATA1CH1_CR_RXCONTROL0RANK1_REG                             (0x00000484)

  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B000484)

  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B0484)

  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07120484)

  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07190484)

#define DDRDATA1CH1_CR_RXCONTROL0RANK2_REG                             (0x00000488)

  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B000488)

  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B0488)

  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07120488)

  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07190488)

#define DDRDATA1CH1_CR_RXCONTROL0RANK3_REG                             (0x0000048C)

  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B00048C)

  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B048C)

  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x0712048C)

  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x0719048C)

#define DDRDATA1CH1_CR_RXCONTROL1RANK0_REG                             (0x00000490)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06000490)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06060490)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C0490)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06120490)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02180490)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A0490)

#define DDRDATA1CH1_CR_RXCONTROL1RANK1_REG                             (0x00000494)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06000494)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06060494)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C0494)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06120494)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02180494)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A0494)

#define DDRDATA1CH1_CR_RXCONTROL1RANK2_REG                             (0x00000498)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06000498)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06060498)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C0498)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06120498)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02180498)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A0498)

#define DDRDATA1CH1_CR_RXCONTROL1RANK3_REG                             (0x0000049C)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x0600049C)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x0606049C)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C049C)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x0612049C)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x0218049C)

  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A049C)

#define DDRDATA1CH1_CR_TXTRAINRANK0_REG                                (0x000004A0)

  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A0004A0)

  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A04A0)

  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxEqualization_HSH               (0x061404A0)

  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A04A0)

  #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E04A0)

#define DDRDATA1CH1_CR_TXTRAINRANK1_REG                                (0x000004A4)

  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A0004A4)

  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A04A4)

  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxEqualization_HSH               (0x061404A4)

  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A04A4)

  #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C04A4)

#define DDRDATA1CH1_CR_TXTRAINRANK2_REG                                (0x000004A8)

  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A0004A8)

  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A04A8)

  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_TxEqualization_HSH               (0x061404A8)

  #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A04A8)

#define DDRDATA1CH1_CR_TXTRAINRANK3_REG                                (0x000004AC)

  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A0004AC)

  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A04AC)

  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_TxEqualization_HSH               (0x061404AC)

  #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA1CH1_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A04AC)

#define DDRDATA1CH1_CR_TXPERBITLOWRANK0_REG                            (0x000004B0)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x060004B0)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x060604B0)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C04B0)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x061204B0)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x081804B0)

#define DDRDATA1CH1_CR_TXPERBITLOWRANK1_REG                            (0x000004B4)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x060004B4)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x060604B4)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C04B4)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x061204B4)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x081804B4)

#define DDRDATA1CH1_CR_TXPERBITLOWRANK2_REG                            (0x000004B8)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x060004B8)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x060604B8)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C04B8)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x061204B8)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x081804B8)

#define DDRDATA1CH1_CR_TXPERBITLOWRANK3_REG                            (0x000004BC)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x060004BC)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x060604BC)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C04BC)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x061204BC)

  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x081804BC)

#define DDRDATA1CH1_CR_RCOMPDATA0_REG                                  (0x000004C0)

  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x060004C0)

  #define DDRDATA1CH1_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA1CH1_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA1CH1_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA1CH1_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA1CH1_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA1CH1_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA1CH1_CR_RCOMPDATA0_Rsvd_HSH                           (0x080604C0)

  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA1CH1_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E04C0)

  #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA1CH1_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x051404C0)

  #define DDRDATA1CH1_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA1CH1_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA1CH1_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA1CH1_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA1CH1_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA1CH1_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA1CH1_CR_RCOMPDATA0_Spare_HSH                          (0x071904C0)

#define DDRDATA1CH1_CR_RCOMPDATA1_REG                                  (0x000004C4)

  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x060004C4)

  #define DDRDATA1CH1_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA1CH1_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA1CH1_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA1CH1_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA1CH1_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA1CH1_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA1CH1_CR_RCOMPDATA1_spare_HSH                          (0x140604C4)

  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA1CH1_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A04C4)

#define DDRDATA1CH1_CR_DDRCRDATACONTROL8_REG                           (0x000004C8)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x020004C8)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x020204C8)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x020404C8)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x020604C8)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x010804C8)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL8_spare_HSH                   (0x170904C8)

#define DDRDATA1CH1_CR_RCOMPDATA2_REG                                  (0x000004CC)

  #define DDRDATA1CH1_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA1CH1_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA1CH1_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA1CH1_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA1CH1_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA1CH1_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x080004CC)

  #define DDRDATA1CH1_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA1CH1_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA1CH1_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA1CH1_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA1CH1_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA1CH1_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x080804CC)

  #define DDRDATA1CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA1CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA1CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA1CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA1CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA1CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x061004CC)

  #define DDRDATA1CH1_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA1CH1_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA1CH1_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA1CH1_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA1CH1_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA1CH1_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA1CH1_CR_RCOMPDATA2_Spare_HSH                          (0x0A1604CC)

#define DDRDATA1CH1_CR_RXCONTROL2RANK0_REG                             (0x000004D0)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x060004D0)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x060604D0)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C04D0)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x051104D0)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x051604D0)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B04D0)

#define DDRDATA1CH1_CR_RXCONTROL2RANK1_REG                             (0x000004D4)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x060004D4)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x060604D4)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C04D4)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x051104D4)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x051604D4)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B04D4)

#define DDRDATA1CH1_CR_RXCONTROL2RANK2_REG                             (0x000004D8)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x060004D8)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x060604D8)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C04D8)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x051104D8)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x051604D8)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B04D8)

#define DDRDATA1CH1_CR_RXCONTROL2RANK3_REG                             (0x000004DC)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x060004DC)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x060604DC)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C04DC)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x051104DC)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x051604DC)

  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B04DC)

#define DDRDATA1CH1_CR_DATATRAINFEEDBACK_REG                           (0x000004E0)

  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x090004E0)

  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA1CH1_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x170904E0)

#define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_REG                         (0x000004E8)

  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x860004E8)

  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x860604E8)

  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C04E8)

  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x851104E8)

  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x051604E8)

  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B04E8)

#define DDRDATA1CH1_CR_DDRCRDATACONTROL1_REG                           (0x000004EC)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x840004EC)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x020404EC)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x010604EC)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x030704EC)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A04EC)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E04EC)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x031304EC)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x851604EC)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B04EC)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E04EC)

#define DDRDATA1CH1_CR_DDRCRDATACONTROL2_REG                           (0x000004F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x050004F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x010504F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x010604F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x010704F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x010804F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x040904F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D04F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x011204F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x011304F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x011404F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x011504F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x011604F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x011704F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x011804F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x011904F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A04F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D04F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E04F0)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F04F0)

#define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x000004FC)

  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x860004FC)

  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x870604FC)

  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D04FC)

  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x861304FC)

  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x871904FC)

#define DDRDATA1CH1_CR_DDRCRDATACONTROL0_REG                           (0x00000500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01000500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01010500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01020500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01030500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01040500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01050500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01060500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01070500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01080500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01090500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A0500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B0500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C0500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D0500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F0500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02130500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01150500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01160500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01170500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01180500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01190500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A0500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B0500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C0500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D0500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E0500)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F0500)

#define DDRDATA1CH1_CR_DDRCRDATACONTROL3_REG                           (0x00000508)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04000508)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02040508)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01060508)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01070508)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86080508)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E0508)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F0508)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03100508)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01130508)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03140508)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01170508)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01180508)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01190508)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A0508)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E0508)

#define DDRDATA1CH1_CR_DDRCRDATACONTROL4_REG                           (0x0000050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x0100050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x0101050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x0302050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x0105050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x0106050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x0107050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x0108050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x0209050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x0110050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x0111050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x0112050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x0513050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x0518050C)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_spare2_OFF                  (29)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_spare2_WID                  ( 3)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_spare2_MSK                  (0xE0000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_spare2_MIN                  (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_spare2_MAX                  (7) // 0x00000007
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_spare2_DEF                  (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL4_spare2_HSH                  (0x031D050C)

#define DDRDATA1CH1_CR_DDRCRDATACONTROL5_REG                           (0x00000510)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08000510)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01080510)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02090510)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B0510)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F0510)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08100510)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08180510)

#define DDRDATA1CH1_CR_DDRCRDATACONTROL6_REG                           (0x00000514)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01000514)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02010514)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01030514)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05040514)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01090514)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A0514)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B0514)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C0514)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E0514)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F0514)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08100514)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01180514)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01190514)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A0514)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D0514)

#define DDRDATA1CH1_CR_DDRCRDATACONTROL7_REG                           (0x00000518)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06000518)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06060518)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C0518)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06120518)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04180518)

  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA1CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C0518)

#define DDRDATA1CH1_CR_DELTADQSRANK0_REG                               (0x0000051C)

  #define DDRDATA1CH1_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA1CH1_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA1CH1_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA1CH1_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA1CH1_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA1CH1_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A00051C)

  #define DDRDATA1CH1_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA1CH1_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA1CH1_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA1CH1_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA1CH1_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA1CH1_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA1CH1_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A051C)

#define DDRDATA1CH1_CR_DELTADQSRANK1_REG                               (0x00000520)

  #define DDRDATA1CH1_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA1CH1_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA1CH1_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA1CH1_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA1CH1_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA1CH1_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A000520)

  #define DDRDATA1CH1_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA1CH1_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA1CH1_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA1CH1_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA1CH1_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA1CH1_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA1CH1_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A0520)

#define DDRDATA1CH1_CR_DELTADQSRANK2_REG                               (0x00000524)

  #define DDRDATA1CH1_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA1CH1_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA1CH1_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA1CH1_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA1CH1_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA1CH1_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A000524)

  #define DDRDATA1CH1_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA1CH1_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA1CH1_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA1CH1_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA1CH1_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA1CH1_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA1CH1_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A0524)

#define DDRDATA1CH1_CR_DELTADQSRANK3_REG                               (0x00000528)

  #define DDRDATA1CH1_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA1CH1_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA1CH1_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA1CH1_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA1CH1_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA1CH1_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A000528)

  #define DDRDATA1CH1_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA1CH1_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA1CH1_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA1CH1_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA1CH1_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA1CH1_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA1CH1_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A0528)

#define DDRDATA1CH1_CR_RXCONTROL3RANK0_REG                             (0x0000052C)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x0600052C)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x0606052C)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C052C)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x0511052C)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x0516052C)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B052C)

#define DDRDATA1CH1_CR_RXCONTROL3RANK1_REG                             (0x00000530)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x06000530)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x06060530)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C0530)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x05110530)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x05160530)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B0530)

#define DDRDATA1CH1_CR_RXCONTROL3RANK2_REG                             (0x00000534)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x06000534)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x06060534)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C0534)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x05110534)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x05160534)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B0534)

#define DDRDATA1CH1_CR_RXCONTROL3RANK3_REG                             (0x00000538)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x06000538)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x06060538)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C0538)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x05110538)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x05160538)

  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA1CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B0538)

#define DDRDATA1CH1_CR_TXPERBITHIRANK0_REG                             (0x0000053C)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x0600053C)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x0606053C)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C053C)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x0612053C)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK0_Spare_HSH                     (0x0818053C)

#define DDRDATA1CH1_CR_TXPERBITHIRANK1_REG                             (0x00000540)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x06000540)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x06060540)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C0540)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x06120540)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK1_Spare_HSH                     (0x08180540)

#define DDRDATA1CH1_CR_TXPERBITHIRANK2_REG                             (0x00000544)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x06000544)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x06060544)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C0544)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x06120544)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK2_Spare_HSH                     (0x08180544)

#define DDRDATA1CH1_CR_TXPERBITHIRANK3_REG                             (0x00000548)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x06000548)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x06060548)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C0548)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x06120548)

  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_TXPERBITHIRANK3_Spare_HSH                     (0x08180548)

#define DDRDATA1CH1_CR_DCCDATACONTROL0_REG                             (0x0000054C)

  #define DDRDATA1CH1_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x0100054C)

  #define DDRDATA1CH1_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x0201054C)

  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x0103054C)

  #define DDRDATA1CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x0204054C)

  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x0706054C)

  #define DDRDATA1CH1_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D054C)

  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA1CH1_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C054C)

#define DDRDATA1CH1_CR_DCCDATACONTROL1_REG                             (0x00000550)

  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x06000550)

  #define DDRDATA1CH1_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x02060550)

  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x04080550)

  #define DDRDATA1CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C0550)

  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E0550)

  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F0550)

  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F100550)

  #define DDRDATA1CH1_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F0550)

#define DDRDATA1CH1_CR_DCCDATACONTROL2_REG                             (0x00000554)

  #define DDRDATA1CH1_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x06000554)

  #define DDRDATA1CH1_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x03060554)

  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D090554)

  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x05160554)

  #define DDRDATA1CH1_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B0554)

  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C0554)

#define DDRDATA1CH1_CR_DCCDATACONTROL3_REG                             (0x00000558)

  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B000558)

  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B0558)

  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x09140558)

  #define DDRDATA1CH1_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D0558)

#define DDRDATA1CH1_CR_DCCDATACONTROL4_REG                             (0x0000055C)

  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x0900055C)

  #define DDRDATA1CH1_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_Spare_HSH                     (0x0109055C)

  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A055C)

  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x0610055C)

  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x0616055C)

  #define DDRDATA1CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C055C)

#define DDRDATA1CH1_CR_DCCDATACONTROL5_REG                             (0x00000560)

  #define DDRDATA1CH1_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_Spare_HSH                     (0x02000560)

  #define DDRDATA1CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x01020560)

  #define DDRDATA1CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x06030560)

  #define DDRDATA1CH1_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x05090560)

  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E0560)

  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B140560)

  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F0560)

#define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_REG                         (0x00000564)

  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B000564)

  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B0564)

  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x09140564)

  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D0564)

#define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_REG                         (0x00000568)

  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x09000568)

  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x01090568)

  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A0568)

  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B0568)

  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A0568)

  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B0568)

#define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_REG                         (0x0000056C)

  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x1000056C)

  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x0710056C)

  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x0717056C)

  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E056C)

#define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x00000570)

  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B000570)

  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B0570)

  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C0570)

#define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x00000574)

  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x09000574)

  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x11090574)

  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A0574)

#define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x00000578)

  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x09000578)

  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x11090578)

  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A0578)

#define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x0000057C)

  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x0900057C)

  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x1109057C)

  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A057C)

#define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_REG                        (0x00000580)

  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06000580)

  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06060580)

  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C0580)

  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06120580)

  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07180580)

  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F0580)

#define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00000584)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06000584)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06060584)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C0584)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06120584)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06180584)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E0584)

#define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00000588)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06000588)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06060588)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C0588)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06120588)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06180588)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E0588)

#define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_REG                       (0x0000058C)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x0600058C)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x0606058C)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C058C)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x0612058C)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x0618058C)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E058C)

#define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00000590)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06000590)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06060590)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C0590)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06120590)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06180590)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E0590)

#define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00000594)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06000594)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06060594)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C0594)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06120594)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06180594)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E0594)

#define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00000598)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06000598)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06060598)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C0598)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06120598)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02180598)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A0598)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D0598)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E0598)

#define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_REG                       (0x0000059C)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x0600059C)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x0606059C)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C059C)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x0612059C)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x0618059C)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E059C)

#define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_REG                       (0x000005A0)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x060005A0)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x060605A0)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C05A0)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x061205A0)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x061805A0)

  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA1CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E05A0)

#define DDRDATA1CH1_CR_DCCDATADCCPILUT0_REG                            (0x000005A4)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x060005A4)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x060605A4)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C05A4)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x061205A4)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x061805A4)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E05A4)

#define DDRDATA1CH1_CR_DCCDATADCCPILUT1_REG                            (0x000005A8)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x060005A8)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x060605A8)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C05A8)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x061205A8)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x061805A8)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E05A8)

#define DDRDATA1CH1_CR_DCCDATADCCPILUT2_REG                            (0x000005AC)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x060005AC)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x060605AC)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C05AC)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x061205AC)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x061805AC)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E05AC)

#define DDRDATA1CH1_CR_DCCDATADCCPILUT3_REG                            (0x000005B0)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x060005B0)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x060605B0)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C05B0)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x061205B0)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x061805B0)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E05B0)

#define DDRDATA1CH1_CR_DCCDATADCCPILUT4_REG                            (0x000005B4)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x060005B4)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x060605B4)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C05B4)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x061205B4)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x061805B4)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E05B4)

#define DDRDATA1CH1_CR_DCCDATADCCPILUT5_REG                            (0x000005B8)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x060005B8)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x060605B8)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C05B8)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x061205B8)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x061805B8)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E05B8)

#define DDRDATA1CH1_CR_DCCDATADCCPILUT6_REG                            (0x000005BC)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x060005BC)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x060605BC)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C05BC)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x061205BC)

  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA1CH1_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x081805BC)

#define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_REG                        (0x000005C0)

  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x060005C0)

  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x060605C0)

  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C05C0)

  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x061205C0)

  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x061805C0)

  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E05C0)

#define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_REG                        (0x000005C4)

  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x060005C4)

  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x060605C4)

  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C05C4)

  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x061205C4)

  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x061805C4)

  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E05C4)

#define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x000005C8)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x060005C8)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x060605C8)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C05C8)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x061205C8)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x021805C8)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A05C8)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C05C8)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E05C8)

#define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x000005CC)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x060005CC)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x060605CC)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C05CC)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x061205CC)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x081805CC)

#define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x000005D0)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x060005D0)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x060605D0)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C05D0)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x061205D0)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x061805D0)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E05D0)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F05D0)

#define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x000005D4)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x060005D4)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x060605D4)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C05D4)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x061205D4)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x061805D4)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E05D4)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F05D4)

#define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x000005D8)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x060005D8)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x060605D8)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C05D8)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x061205D8)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x061805D8)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E05D8)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F05D8)

#define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x000005DC)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x060005DC)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x060605DC)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C05DC)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x061205DC)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x061805DC)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E05DC)

  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA1CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F05DC)

#define DDRDATA2CH0_CR_RXCONTROL0RANK0_REG                             (0x00000600)

  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B000600)

  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B0600)

  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07120600)

  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07190600)

#define DDRDATA2CH0_CR_RXCONTROL0RANK1_REG                             (0x00000604)

  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B000604)

  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B0604)

  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07120604)

  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07190604)

#define DDRDATA2CH0_CR_RXCONTROL0RANK2_REG                             (0x00000608)

  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B000608)

  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B0608)

  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07120608)

  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07190608)

#define DDRDATA2CH0_CR_RXCONTROL0RANK3_REG                             (0x0000060C)

  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B00060C)

  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B060C)

  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x0712060C)

  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x0719060C)

#define DDRDATA2CH0_CR_RXCONTROL1RANK0_REG                             (0x00000610)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06000610)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06060610)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C0610)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06120610)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02180610)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A0610)

#define DDRDATA2CH0_CR_RXCONTROL1RANK1_REG                             (0x00000614)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06000614)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06060614)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C0614)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06120614)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02180614)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A0614)

#define DDRDATA2CH0_CR_RXCONTROL1RANK2_REG                             (0x00000618)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06000618)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06060618)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C0618)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06120618)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02180618)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A0618)

#define DDRDATA2CH0_CR_RXCONTROL1RANK3_REG                             (0x0000061C)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x0600061C)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x0606061C)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C061C)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x0612061C)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x0218061C)

  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A061C)

#define DDRDATA2CH0_CR_TXTRAINRANK0_REG                                (0x00000620)

  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A000620)

  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A0620)

  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxEqualization_HSH               (0x06140620)

  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A0620)

  #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E0620)

#define DDRDATA2CH0_CR_TXTRAINRANK1_REG                                (0x00000624)

  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A000624)

  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A0624)

  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxEqualization_HSH               (0x06140624)

  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A0624)

  #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C0624)

#define DDRDATA2CH0_CR_TXTRAINRANK2_REG                                (0x00000628)

  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A000628)

  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A0628)

  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_TxEqualization_HSH               (0x06140628)

  #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A0628)

#define DDRDATA2CH0_CR_TXTRAINRANK3_REG                                (0x0000062C)

  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A00062C)

  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A062C)

  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_TxEqualization_HSH               (0x0614062C)

  #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA2CH0_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A062C)

#define DDRDATA2CH0_CR_TXPERBITLOWRANK0_REG                            (0x00000630)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x06000630)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x06060630)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C0630)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x06120630)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x08180630)

#define DDRDATA2CH0_CR_TXPERBITLOWRANK1_REG                            (0x00000634)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x06000634)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x06060634)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C0634)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x06120634)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x08180634)

#define DDRDATA2CH0_CR_TXPERBITLOWRANK2_REG                            (0x00000638)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x06000638)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x06060638)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C0638)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x06120638)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x08180638)

#define DDRDATA2CH0_CR_TXPERBITLOWRANK3_REG                            (0x0000063C)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x0600063C)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x0606063C)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C063C)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x0612063C)

  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x0818063C)

#define DDRDATA2CH0_CR_RCOMPDATA0_REG                                  (0x00000640)

  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x06000640)

  #define DDRDATA2CH0_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA2CH0_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA2CH0_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA2CH0_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA2CH0_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA2CH0_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA2CH0_CR_RCOMPDATA0_Rsvd_HSH                           (0x08060640)

  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA2CH0_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E0640)

  #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA2CH0_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x05140640)

  #define DDRDATA2CH0_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA2CH0_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA2CH0_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA2CH0_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA2CH0_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA2CH0_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA2CH0_CR_RCOMPDATA0_Spare_HSH                          (0x07190640)

#define DDRDATA2CH0_CR_RCOMPDATA1_REG                                  (0x00000644)

  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x06000644)

  #define DDRDATA2CH0_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA2CH0_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA2CH0_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA2CH0_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA2CH0_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA2CH0_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA2CH0_CR_RCOMPDATA1_spare_HSH                          (0x14060644)

  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA2CH0_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A0644)

#define DDRDATA2CH0_CR_DDRCRDATACONTROL8_REG                           (0x00000648)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x02000648)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x02020648)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x02040648)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x02060648)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x01080648)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL8_spare_HSH                   (0x17090648)

#define DDRDATA2CH0_CR_RCOMPDATA2_REG                                  (0x0000064C)

  #define DDRDATA2CH0_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA2CH0_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA2CH0_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA2CH0_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA2CH0_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA2CH0_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x0800064C)

  #define DDRDATA2CH0_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA2CH0_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA2CH0_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA2CH0_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA2CH0_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA2CH0_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x0808064C)

  #define DDRDATA2CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA2CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA2CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA2CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA2CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA2CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x0610064C)

  #define DDRDATA2CH0_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA2CH0_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA2CH0_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA2CH0_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA2CH0_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA2CH0_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA2CH0_CR_RCOMPDATA2_Spare_HSH                          (0x0A16064C)

#define DDRDATA2CH0_CR_RXCONTROL2RANK0_REG                             (0x00000650)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x06000650)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x06060650)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C0650)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x05110650)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x05160650)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B0650)

#define DDRDATA2CH0_CR_RXCONTROL2RANK1_REG                             (0x00000654)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x06000654)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x06060654)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C0654)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x05110654)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x05160654)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B0654)

#define DDRDATA2CH0_CR_RXCONTROL2RANK2_REG                             (0x00000658)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x06000658)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x06060658)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C0658)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x05110658)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x05160658)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B0658)

#define DDRDATA2CH0_CR_RXCONTROL2RANK3_REG                             (0x0000065C)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x0600065C)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x0606065C)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C065C)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x0511065C)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x0516065C)

  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B065C)

#define DDRDATA2CH0_CR_DATATRAINFEEDBACK_REG                           (0x00000660)

  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x09000660)

  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA2CH0_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x17090660)

#define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_REG                         (0x00000668)

  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x86000668)

  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x86060668)

  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C0668)

  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x85110668)

  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x05160668)

  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B0668)

#define DDRDATA2CH0_CR_DDRCRDATACONTROL1_REG                           (0x0000066C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x8400066C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x0204066C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x0106066C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x0307066C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A066C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E066C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x0313066C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x8516066C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B066C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E066C)

#define DDRDATA2CH0_CR_DDRCRDATACONTROL2_REG                           (0x00000670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x05000670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x01050670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x01060670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x01070670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x01080670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x04090670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D0670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x01120670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x01130670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x01140670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x01150670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x01160670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x01170670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x01180670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x01190670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A0670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D0670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E0670)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F0670)

#define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x0000067C)

  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x8600067C)

  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x8706067C)

  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D067C)

  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x8613067C)

  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x8719067C)

#define DDRDATA2CH0_CR_DDRCRDATACONTROL0_REG                           (0x00000680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01000680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01010680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01020680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01030680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01040680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01050680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01060680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01070680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01080680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01090680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A0680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B0680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C0680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D0680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F0680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02130680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01150680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01160680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01170680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01180680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01190680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A0680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B0680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C0680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D0680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E0680)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F0680)

#define DDRDATA2CH0_CR_DDRCRDATACONTROL3_REG                           (0x00000688)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04000688)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02040688)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01060688)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01070688)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86080688)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E0688)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F0688)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03100688)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01130688)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03140688)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01170688)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01180688)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01190688)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A0688)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E0688)

#define DDRDATA2CH0_CR_DDRCRDATACONTROL4_REG                           (0x0000068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x0100068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x0101068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x0302068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x0105068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x0106068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x0107068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x0108068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x0209068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x0110068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x0111068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x0112068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x0513068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x0518068C)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_spare2_OFF                  (29)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_spare2_WID                  ( 3)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_spare2_MSK                  (0xE0000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_spare2_MIN                  (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_spare2_MAX                  (7) // 0x00000007
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_spare2_DEF                  (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL4_spare2_HSH                  (0x031D068C)

#define DDRDATA2CH0_CR_DDRCRDATACONTROL5_REG                           (0x00000690)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08000690)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01080690)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02090690)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B0690)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F0690)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08100690)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08180690)

#define DDRDATA2CH0_CR_DDRCRDATACONTROL6_REG                           (0x00000694)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01000694)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02010694)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01030694)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05040694)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01090694)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A0694)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B0694)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C0694)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E0694)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F0694)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08100694)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01180694)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01190694)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A0694)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D0694)

#define DDRDATA2CH0_CR_DDRCRDATACONTROL7_REG                           (0x00000698)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06000698)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06060698)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C0698)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06120698)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04180698)

  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA2CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C0698)

#define DDRDATA2CH0_CR_DELTADQSRANK0_REG                               (0x0000069C)

  #define DDRDATA2CH0_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA2CH0_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA2CH0_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA2CH0_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA2CH0_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA2CH0_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A00069C)

  #define DDRDATA2CH0_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA2CH0_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA2CH0_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA2CH0_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA2CH0_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA2CH0_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA2CH0_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A069C)

#define DDRDATA2CH0_CR_DELTADQSRANK1_REG                               (0x000006A0)

  #define DDRDATA2CH0_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA2CH0_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA2CH0_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA2CH0_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA2CH0_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA2CH0_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A0006A0)

  #define DDRDATA2CH0_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA2CH0_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA2CH0_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA2CH0_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA2CH0_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA2CH0_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA2CH0_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A06A0)

#define DDRDATA2CH0_CR_DELTADQSRANK2_REG                               (0x000006A4)

  #define DDRDATA2CH0_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA2CH0_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA2CH0_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA2CH0_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA2CH0_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA2CH0_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A0006A4)

  #define DDRDATA2CH0_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA2CH0_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA2CH0_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA2CH0_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA2CH0_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA2CH0_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA2CH0_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A06A4)

#define DDRDATA2CH0_CR_DELTADQSRANK3_REG                               (0x000006A8)

  #define DDRDATA2CH0_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA2CH0_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA2CH0_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA2CH0_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA2CH0_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA2CH0_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A0006A8)

  #define DDRDATA2CH0_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA2CH0_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA2CH0_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA2CH0_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA2CH0_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA2CH0_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA2CH0_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A06A8)

#define DDRDATA2CH0_CR_RXCONTROL3RANK0_REG                             (0x000006AC)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x060006AC)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x060606AC)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C06AC)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x051106AC)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x051606AC)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B06AC)

#define DDRDATA2CH0_CR_RXCONTROL3RANK1_REG                             (0x000006B0)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x060006B0)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x060606B0)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C06B0)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x051106B0)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x051606B0)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B06B0)

#define DDRDATA2CH0_CR_RXCONTROL3RANK2_REG                             (0x000006B4)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x060006B4)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x060606B4)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C06B4)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x051106B4)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x051606B4)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B06B4)

#define DDRDATA2CH0_CR_RXCONTROL3RANK3_REG                             (0x000006B8)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x060006B8)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x060606B8)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C06B8)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x051106B8)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x051606B8)

  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B06B8)

#define DDRDATA2CH0_CR_TXPERBITHIRANK0_REG                             (0x000006BC)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x060006BC)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x060606BC)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C06BC)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x061206BC)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK0_Spare_HSH                     (0x081806BC)

#define DDRDATA2CH0_CR_TXPERBITHIRANK1_REG                             (0x000006C0)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x060006C0)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x060606C0)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C06C0)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x061206C0)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK1_Spare_HSH                     (0x081806C0)

#define DDRDATA2CH0_CR_TXPERBITHIRANK2_REG                             (0x000006C4)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x060006C4)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x060606C4)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C06C4)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x061206C4)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK2_Spare_HSH                     (0x081806C4)

#define DDRDATA2CH0_CR_TXPERBITHIRANK3_REG                             (0x000006C8)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x060006C8)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x060606C8)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C06C8)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x061206C8)

  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_TXPERBITHIRANK3_Spare_HSH                     (0x081806C8)

#define DDRDATA2CH0_CR_DCCDATACONTROL0_REG                             (0x000006CC)

  #define DDRDATA2CH0_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x010006CC)

  #define DDRDATA2CH0_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x020106CC)

  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x010306CC)

  #define DDRDATA2CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x020406CC)

  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x070606CC)

  #define DDRDATA2CH0_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D06CC)

  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA2CH0_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C06CC)

#define DDRDATA2CH0_CR_DCCDATACONTROL1_REG                             (0x000006D0)

  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x060006D0)

  #define DDRDATA2CH0_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x020606D0)

  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x040806D0)

  #define DDRDATA2CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C06D0)

  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E06D0)

  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F06D0)

  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F1006D0)

  #define DDRDATA2CH0_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F06D0)

#define DDRDATA2CH0_CR_DCCDATACONTROL2_REG                             (0x000006D4)

  #define DDRDATA2CH0_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x060006D4)

  #define DDRDATA2CH0_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x030606D4)

  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D0906D4)

  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x051606D4)

  #define DDRDATA2CH0_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B06D4)

  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C06D4)

#define DDRDATA2CH0_CR_DCCDATACONTROL3_REG                             (0x000006D8)

  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B0006D8)

  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B06D8)

  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x091406D8)

  #define DDRDATA2CH0_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D06D8)

#define DDRDATA2CH0_CR_DCCDATACONTROL4_REG                             (0x000006DC)

  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x090006DC)

  #define DDRDATA2CH0_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_Spare_HSH                     (0x010906DC)

  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A06DC)

  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x061006DC)

  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x061606DC)

  #define DDRDATA2CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C06DC)

#define DDRDATA2CH0_CR_DCCDATACONTROL5_REG                             (0x000006E0)

  #define DDRDATA2CH0_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_Spare_HSH                     (0x020006E0)

  #define DDRDATA2CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x010206E0)

  #define DDRDATA2CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x060306E0)

  #define DDRDATA2CH0_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x050906E0)

  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E06E0)

  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B1406E0)

  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F06E0)

#define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_REG                         (0x000006E4)

  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B0006E4)

  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B06E4)

  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x091406E4)

  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D06E4)

#define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_REG                         (0x000006E8)

  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x090006E8)

  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x010906E8)

  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A06E8)

  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B06E8)

  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A06E8)

  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B06E8)

#define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_REG                         (0x000006EC)

  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x100006EC)

  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x071006EC)

  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x071706EC)

  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E06EC)

#define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x000006F0)

  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B0006F0)

  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B06F0)

  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C06F0)

#define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x000006F4)

  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x090006F4)

  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x110906F4)

  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A06F4)

#define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x000006F8)

  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x090006F8)

  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x110906F8)

  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A06F8)

#define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x000006FC)

  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x090006FC)

  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x110906FC)

  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A06FC)

#define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_REG                        (0x00000700)

  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06000700)

  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06060700)

  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C0700)

  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06120700)

  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07180700)

  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F0700)

#define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00000704)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06000704)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06060704)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C0704)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06120704)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06180704)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E0704)

#define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00000708)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06000708)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06060708)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C0708)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06120708)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06180708)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E0708)

#define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_REG                       (0x0000070C)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x0600070C)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x0606070C)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C070C)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x0612070C)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x0618070C)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E070C)

#define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00000710)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06000710)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06060710)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C0710)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06120710)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06180710)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E0710)

#define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00000714)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06000714)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06060714)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C0714)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06120714)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06180714)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E0714)

#define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00000718)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06000718)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06060718)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C0718)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06120718)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02180718)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A0718)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D0718)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E0718)

#define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_REG                       (0x0000071C)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x0600071C)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x0606071C)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C071C)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x0612071C)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x0618071C)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E071C)

#define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_REG                       (0x00000720)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x06000720)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x06060720)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C0720)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x06120720)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x06180720)

  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA2CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E0720)

#define DDRDATA2CH0_CR_DCCDATADCCPILUT0_REG                            (0x00000724)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x06000724)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x06060724)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C0724)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x06120724)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x06180724)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E0724)

#define DDRDATA2CH0_CR_DCCDATADCCPILUT1_REG                            (0x00000728)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x06000728)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x06060728)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C0728)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x06120728)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x06180728)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E0728)

#define DDRDATA2CH0_CR_DCCDATADCCPILUT2_REG                            (0x0000072C)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x0600072C)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x0606072C)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C072C)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x0612072C)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x0618072C)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E072C)

#define DDRDATA2CH0_CR_DCCDATADCCPILUT3_REG                            (0x00000730)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x06000730)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x06060730)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C0730)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x06120730)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x06180730)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E0730)

#define DDRDATA2CH0_CR_DCCDATADCCPILUT4_REG                            (0x00000734)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x06000734)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x06060734)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C0734)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x06120734)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x06180734)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E0734)

#define DDRDATA2CH0_CR_DCCDATADCCPILUT5_REG                            (0x00000738)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x06000738)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x06060738)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C0738)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x06120738)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x06180738)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E0738)

#define DDRDATA2CH0_CR_DCCDATADCCPILUT6_REG                            (0x0000073C)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x0600073C)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x0606073C)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C073C)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x0612073C)

  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH0_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x0818073C)

#define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_REG                        (0x00000740)

  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x06000740)

  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x06060740)

  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C0740)

  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x06120740)

  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x06180740)

  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E0740)

#define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_REG                        (0x00000744)

  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x06000744)

  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x06060744)

  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C0744)

  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x06120744)

  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x06180744)

  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E0744)

#define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x00000748)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x06000748)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x06060748)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C0748)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x06120748)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x02180748)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A0748)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C0748)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E0748)

#define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x0000074C)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x0600074C)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x0606074C)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C074C)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x0612074C)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x0818074C)

#define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x00000750)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x06000750)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x06060750)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C0750)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x06120750)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x06180750)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E0750)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F0750)

#define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x00000754)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x06000754)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x06060754)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C0754)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x06120754)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x06180754)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E0754)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F0754)

#define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x00000758)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x06000758)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x06060758)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C0758)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x06120758)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x06180758)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E0758)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F0758)

#define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x0000075C)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x0600075C)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x0606075C)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C075C)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x0612075C)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x0618075C)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E075C)

  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA2CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F075C)

#define DDRDATA2CH1_CR_RXCONTROL0RANK0_REG                             (0x00000780)

  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B000780)

  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B0780)

  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07120780)

  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07190780)

#define DDRDATA2CH1_CR_RXCONTROL0RANK1_REG                             (0x00000784)

  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B000784)

  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B0784)

  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07120784)

  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07190784)

#define DDRDATA2CH1_CR_RXCONTROL0RANK2_REG                             (0x00000788)

  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B000788)

  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B0788)

  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07120788)

  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07190788)

#define DDRDATA2CH1_CR_RXCONTROL0RANK3_REG                             (0x0000078C)

  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B00078C)

  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B078C)

  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x0712078C)

  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x0719078C)

#define DDRDATA2CH1_CR_RXCONTROL1RANK0_REG                             (0x00000790)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06000790)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06060790)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C0790)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06120790)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02180790)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A0790)

#define DDRDATA2CH1_CR_RXCONTROL1RANK1_REG                             (0x00000794)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06000794)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06060794)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C0794)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06120794)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02180794)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A0794)

#define DDRDATA2CH1_CR_RXCONTROL1RANK2_REG                             (0x00000798)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06000798)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06060798)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C0798)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06120798)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02180798)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A0798)

#define DDRDATA2CH1_CR_RXCONTROL1RANK3_REG                             (0x0000079C)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x0600079C)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x0606079C)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C079C)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x0612079C)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x0218079C)

  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A079C)

#define DDRDATA2CH1_CR_TXTRAINRANK0_REG                                (0x000007A0)

  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A0007A0)

  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A07A0)

  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxEqualization_HSH               (0x061407A0)

  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A07A0)

  #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E07A0)

#define DDRDATA2CH1_CR_TXTRAINRANK1_REG                                (0x000007A4)

  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A0007A4)

  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A07A4)

  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxEqualization_HSH               (0x061407A4)

  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A07A4)

  #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C07A4)

#define DDRDATA2CH1_CR_TXTRAINRANK2_REG                                (0x000007A8)

  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A0007A8)

  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A07A8)

  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_TxEqualization_HSH               (0x061407A8)

  #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A07A8)

#define DDRDATA2CH1_CR_TXTRAINRANK3_REG                                (0x000007AC)

  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A0007AC)

  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A07AC)

  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_TxEqualization_HSH               (0x061407AC)

  #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA2CH1_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A07AC)

#define DDRDATA2CH1_CR_TXPERBITLOWRANK0_REG                            (0x000007B0)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x060007B0)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x060607B0)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C07B0)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x061207B0)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x081807B0)

#define DDRDATA2CH1_CR_TXPERBITLOWRANK1_REG                            (0x000007B4)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x060007B4)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x060607B4)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C07B4)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x061207B4)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x081807B4)

#define DDRDATA2CH1_CR_TXPERBITLOWRANK2_REG                            (0x000007B8)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x060007B8)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x060607B8)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C07B8)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x061207B8)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x081807B8)

#define DDRDATA2CH1_CR_TXPERBITLOWRANK3_REG                            (0x000007BC)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x060007BC)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x060607BC)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C07BC)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x061207BC)

  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x081807BC)

#define DDRDATA2CH1_CR_RCOMPDATA0_REG                                  (0x000007C0)

  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x060007C0)

  #define DDRDATA2CH1_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA2CH1_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA2CH1_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA2CH1_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA2CH1_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA2CH1_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA2CH1_CR_RCOMPDATA0_Rsvd_HSH                           (0x080607C0)

  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA2CH1_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E07C0)

  #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA2CH1_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x051407C0)

  #define DDRDATA2CH1_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA2CH1_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA2CH1_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA2CH1_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA2CH1_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA2CH1_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA2CH1_CR_RCOMPDATA0_Spare_HSH                          (0x071907C0)

#define DDRDATA2CH1_CR_RCOMPDATA1_REG                                  (0x000007C4)

  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x060007C4)

  #define DDRDATA2CH1_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA2CH1_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA2CH1_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA2CH1_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA2CH1_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA2CH1_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA2CH1_CR_RCOMPDATA1_spare_HSH                          (0x140607C4)

  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA2CH1_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A07C4)

#define DDRDATA2CH1_CR_DDRCRDATACONTROL8_REG                           (0x000007C8)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x020007C8)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x020207C8)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x020407C8)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x020607C8)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x010807C8)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL8_spare_HSH                   (0x170907C8)

#define DDRDATA2CH1_CR_RCOMPDATA2_REG                                  (0x000007CC)

  #define DDRDATA2CH1_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA2CH1_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA2CH1_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA2CH1_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA2CH1_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA2CH1_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x080007CC)

  #define DDRDATA2CH1_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA2CH1_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA2CH1_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA2CH1_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA2CH1_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA2CH1_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x080807CC)

  #define DDRDATA2CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA2CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA2CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA2CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA2CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA2CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x061007CC)

  #define DDRDATA2CH1_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA2CH1_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA2CH1_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA2CH1_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA2CH1_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA2CH1_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA2CH1_CR_RCOMPDATA2_Spare_HSH                          (0x0A1607CC)

#define DDRDATA2CH1_CR_RXCONTROL2RANK0_REG                             (0x000007D0)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x060007D0)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x060607D0)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C07D0)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x051107D0)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x051607D0)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B07D0)

#define DDRDATA2CH1_CR_RXCONTROL2RANK1_REG                             (0x000007D4)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x060007D4)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x060607D4)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C07D4)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x051107D4)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x051607D4)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B07D4)

#define DDRDATA2CH1_CR_RXCONTROL2RANK2_REG                             (0x000007D8)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x060007D8)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x060607D8)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C07D8)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x051107D8)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x051607D8)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B07D8)

#define DDRDATA2CH1_CR_RXCONTROL2RANK3_REG                             (0x000007DC)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x060007DC)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x060607DC)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C07DC)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x051107DC)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x051607DC)

  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B07DC)

#define DDRDATA2CH1_CR_DATATRAINFEEDBACK_REG                           (0x000007E0)

  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x090007E0)

  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA2CH1_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x170907E0)

#define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_REG                         (0x000007E8)

  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x860007E8)

  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x860607E8)

  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C07E8)

  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x851107E8)

  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x051607E8)

  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B07E8)

#define DDRDATA2CH1_CR_DDRCRDATACONTROL1_REG                           (0x000007EC)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x840007EC)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x020407EC)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x010607EC)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x030707EC)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A07EC)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E07EC)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x031307EC)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x851607EC)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B07EC)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E07EC)

#define DDRDATA2CH1_CR_DDRCRDATACONTROL2_REG                           (0x000007F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x050007F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x010507F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x010607F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x010707F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x010807F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x040907F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D07F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x011207F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x011307F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x011407F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x011507F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x011607F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x011707F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x011807F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x011907F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A07F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D07F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E07F0)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F07F0)

#define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x000007FC)

  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x860007FC)

  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x870607FC)

  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D07FC)

  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x861307FC)

  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x871907FC)

#define DDRDATA2CH1_CR_DDRCRDATACONTROL0_REG                           (0x00000800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01000800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01010800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01020800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01030800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01040800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01050800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01060800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01070800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01080800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01090800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A0800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B0800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C0800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D0800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F0800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02130800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01150800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01160800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01170800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01180800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01190800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A0800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B0800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C0800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D0800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E0800)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F0800)

#define DDRDATA2CH1_CR_DDRCRDATACONTROL3_REG                           (0x00000808)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04000808)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02040808)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01060808)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01070808)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86080808)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E0808)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F0808)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03100808)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01130808)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03140808)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01170808)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01180808)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01190808)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A0808)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E0808)

#define DDRDATA2CH1_CR_DDRCRDATACONTROL4_REG                           (0x0000080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x0100080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x0101080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x0302080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x0105080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x0106080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x0107080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x0108080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x0209080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x0110080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x0111080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x0112080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x0513080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x0518080C)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_spare2_OFF                  (29)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_spare2_WID                  ( 3)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_spare2_MSK                  (0xE0000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_spare2_MIN                  (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_spare2_MAX                  (7) // 0x00000007
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_spare2_DEF                  (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL4_spare2_HSH                  (0x031D080C)

#define DDRDATA2CH1_CR_DDRCRDATACONTROL5_REG                           (0x00000810)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08000810)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01080810)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02090810)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B0810)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F0810)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08100810)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08180810)

#define DDRDATA2CH1_CR_DDRCRDATACONTROL6_REG                           (0x00000814)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01000814)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02010814)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01030814)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05040814)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01090814)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A0814)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B0814)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C0814)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E0814)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F0814)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08100814)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01180814)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01190814)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A0814)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D0814)

#define DDRDATA2CH1_CR_DDRCRDATACONTROL7_REG                           (0x00000818)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06000818)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06060818)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C0818)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06120818)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04180818)

  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA2CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C0818)

#define DDRDATA2CH1_CR_DELTADQSRANK0_REG                               (0x0000081C)

  #define DDRDATA2CH1_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA2CH1_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA2CH1_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA2CH1_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA2CH1_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA2CH1_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A00081C)

  #define DDRDATA2CH1_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA2CH1_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA2CH1_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA2CH1_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA2CH1_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA2CH1_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA2CH1_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A081C)

#define DDRDATA2CH1_CR_DELTADQSRANK1_REG                               (0x00000820)

  #define DDRDATA2CH1_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA2CH1_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA2CH1_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA2CH1_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA2CH1_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA2CH1_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A000820)

  #define DDRDATA2CH1_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA2CH1_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA2CH1_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA2CH1_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA2CH1_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA2CH1_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA2CH1_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A0820)

#define DDRDATA2CH1_CR_DELTADQSRANK2_REG                               (0x00000824)

  #define DDRDATA2CH1_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA2CH1_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA2CH1_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA2CH1_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA2CH1_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA2CH1_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A000824)

  #define DDRDATA2CH1_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA2CH1_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA2CH1_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA2CH1_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA2CH1_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA2CH1_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA2CH1_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A0824)

#define DDRDATA2CH1_CR_DELTADQSRANK3_REG                               (0x00000828)

  #define DDRDATA2CH1_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA2CH1_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA2CH1_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA2CH1_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA2CH1_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA2CH1_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A000828)

  #define DDRDATA2CH1_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA2CH1_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA2CH1_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA2CH1_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA2CH1_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA2CH1_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA2CH1_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A0828)

#define DDRDATA2CH1_CR_RXCONTROL3RANK0_REG                             (0x0000082C)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x0600082C)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x0606082C)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C082C)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x0511082C)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x0516082C)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B082C)

#define DDRDATA2CH1_CR_RXCONTROL3RANK1_REG                             (0x00000830)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x06000830)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x06060830)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C0830)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x05110830)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x05160830)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B0830)

#define DDRDATA2CH1_CR_RXCONTROL3RANK2_REG                             (0x00000834)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x06000834)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x06060834)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C0834)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x05110834)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x05160834)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B0834)

#define DDRDATA2CH1_CR_RXCONTROL3RANK3_REG                             (0x00000838)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x06000838)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x06060838)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C0838)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x05110838)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x05160838)

  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA2CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B0838)

#define DDRDATA2CH1_CR_TXPERBITHIRANK0_REG                             (0x0000083C)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x0600083C)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x0606083C)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C083C)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x0612083C)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK0_Spare_HSH                     (0x0818083C)

#define DDRDATA2CH1_CR_TXPERBITHIRANK1_REG                             (0x00000840)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x06000840)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x06060840)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C0840)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x06120840)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK1_Spare_HSH                     (0x08180840)

#define DDRDATA2CH1_CR_TXPERBITHIRANK2_REG                             (0x00000844)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x06000844)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x06060844)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C0844)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x06120844)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK2_Spare_HSH                     (0x08180844)

#define DDRDATA2CH1_CR_TXPERBITHIRANK3_REG                             (0x00000848)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x06000848)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x06060848)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C0848)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x06120848)

  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_TXPERBITHIRANK3_Spare_HSH                     (0x08180848)

#define DDRDATA2CH1_CR_DCCDATACONTROL0_REG                             (0x0000084C)

  #define DDRDATA2CH1_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x0100084C)

  #define DDRDATA2CH1_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x0201084C)

  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x0103084C)

  #define DDRDATA2CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x0204084C)

  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x0706084C)

  #define DDRDATA2CH1_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D084C)

  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA2CH1_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C084C)

#define DDRDATA2CH1_CR_DCCDATACONTROL1_REG                             (0x00000850)

  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x06000850)

  #define DDRDATA2CH1_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x02060850)

  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x04080850)

  #define DDRDATA2CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C0850)

  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E0850)

  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F0850)

  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F100850)

  #define DDRDATA2CH1_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F0850)

#define DDRDATA2CH1_CR_DCCDATACONTROL2_REG                             (0x00000854)

  #define DDRDATA2CH1_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x06000854)

  #define DDRDATA2CH1_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x03060854)

  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D090854)

  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x05160854)

  #define DDRDATA2CH1_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B0854)

  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C0854)

#define DDRDATA2CH1_CR_DCCDATACONTROL3_REG                             (0x00000858)

  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B000858)

  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B0858)

  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x09140858)

  #define DDRDATA2CH1_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D0858)

#define DDRDATA2CH1_CR_DCCDATACONTROL4_REG                             (0x0000085C)

  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x0900085C)

  #define DDRDATA2CH1_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_Spare_HSH                     (0x0109085C)

  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A085C)

  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x0610085C)

  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x0616085C)

  #define DDRDATA2CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C085C)

#define DDRDATA2CH1_CR_DCCDATACONTROL5_REG                             (0x00000860)

  #define DDRDATA2CH1_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_Spare_HSH                     (0x02000860)

  #define DDRDATA2CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x01020860)

  #define DDRDATA2CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x06030860)

  #define DDRDATA2CH1_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x05090860)

  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E0860)

  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B140860)

  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F0860)

#define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_REG                         (0x00000864)

  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B000864)

  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B0864)

  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x09140864)

  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D0864)

#define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_REG                         (0x00000868)

  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x09000868)

  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x01090868)

  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A0868)

  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B0868)

  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A0868)

  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B0868)

#define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_REG                         (0x0000086C)

  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x1000086C)

  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x0710086C)

  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x0717086C)

  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E086C)

#define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x00000870)

  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B000870)

  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B0870)

  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C0870)

#define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x00000874)

  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x09000874)

  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x11090874)

  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A0874)

#define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x00000878)

  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x09000878)

  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x11090878)

  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A0878)

#define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x0000087C)

  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x0900087C)

  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x1109087C)

  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A087C)

#define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_REG                        (0x00000880)

  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06000880)

  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06060880)

  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C0880)

  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06120880)

  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07180880)

  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F0880)

#define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00000884)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06000884)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06060884)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C0884)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06120884)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06180884)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E0884)

#define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00000888)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06000888)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06060888)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C0888)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06120888)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06180888)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E0888)

#define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_REG                       (0x0000088C)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x0600088C)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x0606088C)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C088C)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x0612088C)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x0618088C)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E088C)

#define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00000890)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06000890)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06060890)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C0890)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06120890)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06180890)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E0890)

#define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00000894)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06000894)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06060894)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C0894)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06120894)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06180894)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E0894)

#define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00000898)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06000898)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06060898)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C0898)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06120898)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02180898)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A0898)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D0898)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E0898)

#define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_REG                       (0x0000089C)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x0600089C)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x0606089C)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C089C)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x0612089C)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x0618089C)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E089C)

#define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_REG                       (0x000008A0)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x060008A0)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x060608A0)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C08A0)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x061208A0)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x061808A0)

  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA2CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E08A0)

#define DDRDATA2CH1_CR_DCCDATADCCPILUT0_REG                            (0x000008A4)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x060008A4)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x060608A4)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C08A4)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x061208A4)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x061808A4)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E08A4)

#define DDRDATA2CH1_CR_DCCDATADCCPILUT1_REG                            (0x000008A8)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x060008A8)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x060608A8)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C08A8)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x061208A8)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x061808A8)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E08A8)

#define DDRDATA2CH1_CR_DCCDATADCCPILUT2_REG                            (0x000008AC)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x060008AC)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x060608AC)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C08AC)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x061208AC)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x061808AC)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E08AC)

#define DDRDATA2CH1_CR_DCCDATADCCPILUT3_REG                            (0x000008B0)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x060008B0)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x060608B0)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C08B0)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x061208B0)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x061808B0)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E08B0)

#define DDRDATA2CH1_CR_DCCDATADCCPILUT4_REG                            (0x000008B4)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x060008B4)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x060608B4)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C08B4)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x061208B4)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x061808B4)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E08B4)

#define DDRDATA2CH1_CR_DCCDATADCCPILUT5_REG                            (0x000008B8)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x060008B8)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x060608B8)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C08B8)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x061208B8)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x061808B8)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E08B8)

#define DDRDATA2CH1_CR_DCCDATADCCPILUT6_REG                            (0x000008BC)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x060008BC)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x060608BC)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C08BC)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x061208BC)

  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA2CH1_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x081808BC)

#define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_REG                        (0x000008C0)

  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x060008C0)

  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x060608C0)

  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C08C0)

  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x061208C0)

  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x061808C0)

  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E08C0)

#define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_REG                        (0x000008C4)

  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x060008C4)

  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x060608C4)

  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C08C4)

  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x061208C4)

  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x061808C4)

  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E08C4)

#define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x000008C8)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x060008C8)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x060608C8)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C08C8)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x061208C8)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x021808C8)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A08C8)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C08C8)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E08C8)

#define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x000008CC)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x060008CC)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x060608CC)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C08CC)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x061208CC)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x081808CC)

#define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x000008D0)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x060008D0)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x060608D0)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C08D0)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x061208D0)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x061808D0)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E08D0)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F08D0)

#define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x000008D4)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x060008D4)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x060608D4)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C08D4)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x061208D4)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x061808D4)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E08D4)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F08D4)

#define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x000008D8)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x060008D8)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x060608D8)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C08D8)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x061208D8)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x061808D8)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E08D8)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F08D8)

#define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x000008DC)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x060008DC)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x060608DC)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C08DC)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x061208DC)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x061808DC)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E08DC)

  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA2CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F08DC)

#define DDRDATA3CH0_CR_RXCONTROL0RANK0_REG                             (0x00000900)

  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B000900)

  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B0900)

  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07120900)

  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07190900)

#define DDRDATA3CH0_CR_RXCONTROL0RANK1_REG                             (0x00000904)

  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B000904)

  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B0904)

  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07120904)

  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07190904)

#define DDRDATA3CH0_CR_RXCONTROL0RANK2_REG                             (0x00000908)

  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B000908)

  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B0908)

  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07120908)

  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07190908)

#define DDRDATA3CH0_CR_RXCONTROL0RANK3_REG                             (0x0000090C)

  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B00090C)

  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B090C)

  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x0712090C)

  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x0719090C)

#define DDRDATA3CH0_CR_RXCONTROL1RANK0_REG                             (0x00000910)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06000910)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06060910)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C0910)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06120910)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02180910)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A0910)

#define DDRDATA3CH0_CR_RXCONTROL1RANK1_REG                             (0x00000914)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06000914)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06060914)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C0914)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06120914)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02180914)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A0914)

#define DDRDATA3CH0_CR_RXCONTROL1RANK2_REG                             (0x00000918)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06000918)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06060918)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C0918)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06120918)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02180918)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A0918)

#define DDRDATA3CH0_CR_RXCONTROL1RANK3_REG                             (0x0000091C)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x0600091C)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x0606091C)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C091C)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x0612091C)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x0218091C)

  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A091C)

#define DDRDATA3CH0_CR_TXTRAINRANK0_REG                                (0x00000920)

  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A000920)

  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A0920)

  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxEqualization_HSH               (0x06140920)

  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A0920)

  #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E0920)

#define DDRDATA3CH0_CR_TXTRAINRANK1_REG                                (0x00000924)

  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A000924)

  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A0924)

  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxEqualization_HSH               (0x06140924)

  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A0924)

  #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C0924)

#define DDRDATA3CH0_CR_TXTRAINRANK2_REG                                (0x00000928)

  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A000928)

  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A0928)

  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_TxEqualization_HSH               (0x06140928)

  #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A0928)

#define DDRDATA3CH0_CR_TXTRAINRANK3_REG                                (0x0000092C)

  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A00092C)

  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A092C)

  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_TxEqualization_HSH               (0x0614092C)

  #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA3CH0_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A092C)

#define DDRDATA3CH0_CR_TXPERBITLOWRANK0_REG                            (0x00000930)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x06000930)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x06060930)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C0930)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x06120930)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x08180930)

#define DDRDATA3CH0_CR_TXPERBITLOWRANK1_REG                            (0x00000934)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x06000934)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x06060934)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C0934)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x06120934)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x08180934)

#define DDRDATA3CH0_CR_TXPERBITLOWRANK2_REG                            (0x00000938)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x06000938)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x06060938)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C0938)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x06120938)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x08180938)

#define DDRDATA3CH0_CR_TXPERBITLOWRANK3_REG                            (0x0000093C)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x0600093C)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x0606093C)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C093C)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x0612093C)

  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x0818093C)

#define DDRDATA3CH0_CR_RCOMPDATA0_REG                                  (0x00000940)

  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x06000940)

  #define DDRDATA3CH0_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA3CH0_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA3CH0_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA3CH0_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA3CH0_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA3CH0_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA3CH0_CR_RCOMPDATA0_Rsvd_HSH                           (0x08060940)

  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA3CH0_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E0940)

  #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA3CH0_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x05140940)

  #define DDRDATA3CH0_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA3CH0_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA3CH0_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA3CH0_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA3CH0_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA3CH0_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA3CH0_CR_RCOMPDATA0_Spare_HSH                          (0x07190940)

#define DDRDATA3CH0_CR_RCOMPDATA1_REG                                  (0x00000944)

  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x06000944)

  #define DDRDATA3CH0_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA3CH0_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA3CH0_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA3CH0_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA3CH0_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA3CH0_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA3CH0_CR_RCOMPDATA1_spare_HSH                          (0x14060944)

  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA3CH0_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A0944)

#define DDRDATA3CH0_CR_DDRCRDATACONTROL8_REG                           (0x00000948)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x02000948)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x02020948)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x02040948)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x02060948)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x01080948)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL8_spare_HSH                   (0x17090948)

#define DDRDATA3CH0_CR_RCOMPDATA2_REG                                  (0x0000094C)

  #define DDRDATA3CH0_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA3CH0_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA3CH0_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA3CH0_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA3CH0_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA3CH0_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x0800094C)

  #define DDRDATA3CH0_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA3CH0_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA3CH0_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA3CH0_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA3CH0_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA3CH0_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x0808094C)

  #define DDRDATA3CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA3CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA3CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA3CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA3CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA3CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x0610094C)

  #define DDRDATA3CH0_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA3CH0_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA3CH0_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA3CH0_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA3CH0_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA3CH0_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA3CH0_CR_RCOMPDATA2_Spare_HSH                          (0x0A16094C)

#define DDRDATA3CH0_CR_RXCONTROL2RANK0_REG                             (0x00000950)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x06000950)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x06060950)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C0950)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x05110950)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x05160950)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B0950)

#define DDRDATA3CH0_CR_RXCONTROL2RANK1_REG                             (0x00000954)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x06000954)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x06060954)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C0954)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x05110954)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x05160954)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B0954)

#define DDRDATA3CH0_CR_RXCONTROL2RANK2_REG                             (0x00000958)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x06000958)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x06060958)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C0958)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x05110958)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x05160958)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B0958)

#define DDRDATA3CH0_CR_RXCONTROL2RANK3_REG                             (0x0000095C)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x0600095C)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x0606095C)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C095C)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x0511095C)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x0516095C)

  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B095C)

#define DDRDATA3CH0_CR_DATATRAINFEEDBACK_REG                           (0x00000960)

  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x09000960)

  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA3CH0_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x17090960)

#define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_REG                         (0x00000968)

  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x86000968)

  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x86060968)

  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C0968)

  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x85110968)

  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x05160968)

  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B0968)

#define DDRDATA3CH0_CR_DDRCRDATACONTROL1_REG                           (0x0000096C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x8400096C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x0204096C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x0106096C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x0307096C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A096C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E096C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x0313096C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x8516096C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B096C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E096C)

#define DDRDATA3CH0_CR_DDRCRDATACONTROL2_REG                           (0x00000970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x05000970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x01050970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x01060970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x01070970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x01080970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x04090970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D0970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x01120970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x01130970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x01140970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x01150970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x01160970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x01170970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x01180970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x01190970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A0970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D0970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E0970)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F0970)

#define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x0000097C)

  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x8600097C)

  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x8706097C)

  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D097C)

  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x8613097C)

  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x8719097C)

#define DDRDATA3CH0_CR_DDRCRDATACONTROL0_REG                           (0x00000980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01000980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01010980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01020980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01030980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01040980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01050980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01060980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01070980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01080980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01090980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A0980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B0980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C0980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D0980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F0980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02130980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01150980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01160980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01170980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01180980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01190980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A0980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B0980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C0980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D0980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E0980)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F0980)

#define DDRDATA3CH0_CR_DDRCRDATACONTROL3_REG                           (0x00000988)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04000988)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02040988)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01060988)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01070988)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86080988)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E0988)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F0988)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03100988)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01130988)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03140988)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01170988)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01180988)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01190988)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A0988)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E0988)

#define DDRDATA3CH0_CR_DDRCRDATACONTROL4_REG                           (0x0000098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x0100098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x0101098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x0302098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x0105098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x0106098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x0107098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x0108098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x0209098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x0110098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x0111098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x0112098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x0513098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x0518098C)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_spare2_OFF                  (29)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_spare2_WID                  ( 3)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_spare2_MSK                  (0xE0000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_spare2_MIN                  (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_spare2_MAX                  (7) // 0x00000007
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_spare2_DEF                  (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL4_spare2_HSH                  (0x031D098C)

#define DDRDATA3CH0_CR_DDRCRDATACONTROL5_REG                           (0x00000990)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08000990)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01080990)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02090990)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B0990)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F0990)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08100990)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08180990)

#define DDRDATA3CH0_CR_DDRCRDATACONTROL6_REG                           (0x00000994)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01000994)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02010994)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01030994)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05040994)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01090994)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A0994)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B0994)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C0994)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E0994)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F0994)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08100994)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01180994)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01190994)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A0994)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D0994)

#define DDRDATA3CH0_CR_DDRCRDATACONTROL7_REG                           (0x00000998)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06000998)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06060998)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C0998)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06120998)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04180998)

  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA3CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C0998)

#define DDRDATA3CH0_CR_DELTADQSRANK0_REG                               (0x0000099C)

  #define DDRDATA3CH0_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA3CH0_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA3CH0_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA3CH0_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA3CH0_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA3CH0_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A00099C)

  #define DDRDATA3CH0_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA3CH0_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA3CH0_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA3CH0_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA3CH0_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA3CH0_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA3CH0_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A099C)

#define DDRDATA3CH0_CR_DELTADQSRANK1_REG                               (0x000009A0)

  #define DDRDATA3CH0_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA3CH0_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA3CH0_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA3CH0_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA3CH0_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA3CH0_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A0009A0)

  #define DDRDATA3CH0_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA3CH0_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA3CH0_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA3CH0_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA3CH0_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA3CH0_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA3CH0_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A09A0)

#define DDRDATA3CH0_CR_DELTADQSRANK2_REG                               (0x000009A4)

  #define DDRDATA3CH0_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA3CH0_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA3CH0_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA3CH0_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA3CH0_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA3CH0_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A0009A4)

  #define DDRDATA3CH0_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA3CH0_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA3CH0_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA3CH0_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA3CH0_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA3CH0_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA3CH0_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A09A4)

#define DDRDATA3CH0_CR_DELTADQSRANK3_REG                               (0x000009A8)

  #define DDRDATA3CH0_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA3CH0_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA3CH0_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA3CH0_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA3CH0_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA3CH0_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A0009A8)

  #define DDRDATA3CH0_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA3CH0_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA3CH0_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA3CH0_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA3CH0_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA3CH0_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA3CH0_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A09A8)

#define DDRDATA3CH0_CR_RXCONTROL3RANK0_REG                             (0x000009AC)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x060009AC)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x060609AC)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C09AC)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x051109AC)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x051609AC)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B09AC)

#define DDRDATA3CH0_CR_RXCONTROL3RANK1_REG                             (0x000009B0)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x060009B0)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x060609B0)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C09B0)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x051109B0)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x051609B0)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B09B0)

#define DDRDATA3CH0_CR_RXCONTROL3RANK2_REG                             (0x000009B4)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x060009B4)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x060609B4)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C09B4)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x051109B4)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x051609B4)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B09B4)

#define DDRDATA3CH0_CR_RXCONTROL3RANK3_REG                             (0x000009B8)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x060009B8)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x060609B8)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C09B8)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x051109B8)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x051609B8)

  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B09B8)

#define DDRDATA3CH0_CR_TXPERBITHIRANK0_REG                             (0x000009BC)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x060009BC)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x060609BC)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C09BC)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x061209BC)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK0_Spare_HSH                     (0x081809BC)

#define DDRDATA3CH0_CR_TXPERBITHIRANK1_REG                             (0x000009C0)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x060009C0)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x060609C0)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C09C0)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x061209C0)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK1_Spare_HSH                     (0x081809C0)

#define DDRDATA3CH0_CR_TXPERBITHIRANK2_REG                             (0x000009C4)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x060009C4)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x060609C4)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C09C4)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x061209C4)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK2_Spare_HSH                     (0x081809C4)

#define DDRDATA3CH0_CR_TXPERBITHIRANK3_REG                             (0x000009C8)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x060009C8)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x060609C8)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C09C8)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x061209C8)

  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_TXPERBITHIRANK3_Spare_HSH                     (0x081809C8)

#define DDRDATA3CH0_CR_DCCDATACONTROL0_REG                             (0x000009CC)

  #define DDRDATA3CH0_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x010009CC)

  #define DDRDATA3CH0_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x020109CC)

  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x010309CC)

  #define DDRDATA3CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x020409CC)

  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x070609CC)

  #define DDRDATA3CH0_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D09CC)

  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA3CH0_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C09CC)

#define DDRDATA3CH0_CR_DCCDATACONTROL1_REG                             (0x000009D0)

  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x060009D0)

  #define DDRDATA3CH0_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x020609D0)

  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x040809D0)

  #define DDRDATA3CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C09D0)

  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E09D0)

  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F09D0)

  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F1009D0)

  #define DDRDATA3CH0_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F09D0)

#define DDRDATA3CH0_CR_DCCDATACONTROL2_REG                             (0x000009D4)

  #define DDRDATA3CH0_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x060009D4)

  #define DDRDATA3CH0_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x030609D4)

  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D0909D4)

  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x051609D4)

  #define DDRDATA3CH0_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B09D4)

  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C09D4)

#define DDRDATA3CH0_CR_DCCDATACONTROL3_REG                             (0x000009D8)

  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B0009D8)

  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B09D8)

  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x091409D8)

  #define DDRDATA3CH0_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D09D8)

#define DDRDATA3CH0_CR_DCCDATACONTROL4_REG                             (0x000009DC)

  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x090009DC)

  #define DDRDATA3CH0_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_Spare_HSH                     (0x010909DC)

  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A09DC)

  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x061009DC)

  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x061609DC)

  #define DDRDATA3CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C09DC)

#define DDRDATA3CH0_CR_DCCDATACONTROL5_REG                             (0x000009E0)

  #define DDRDATA3CH0_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_Spare_HSH                     (0x020009E0)

  #define DDRDATA3CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x010209E0)

  #define DDRDATA3CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x060309E0)

  #define DDRDATA3CH0_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x050909E0)

  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E09E0)

  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B1409E0)

  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F09E0)

#define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_REG                         (0x000009E4)

  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B0009E4)

  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B09E4)

  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x091409E4)

  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D09E4)

#define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_REG                         (0x000009E8)

  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x090009E8)

  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x010909E8)

  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A09E8)

  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B09E8)

  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A09E8)

  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B09E8)

#define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_REG                         (0x000009EC)

  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x100009EC)

  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x071009EC)

  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x071709EC)

  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E09EC)

#define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x000009F0)

  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B0009F0)

  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B09F0)

  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C09F0)

#define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x000009F4)

  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x090009F4)

  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x110909F4)

  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A09F4)

#define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x000009F8)

  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x090009F8)

  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x110909F8)

  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A09F8)

#define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x000009FC)

  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x090009FC)

  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x110909FC)

  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A09FC)

#define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_REG                        (0x00000A00)

  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06000A00)

  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06060A00)

  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C0A00)

  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06120A00)

  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07180A00)

  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F0A00)

#define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00000A04)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06000A04)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06060A04)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C0A04)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06120A04)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06180A04)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E0A04)

#define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00000A08)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06000A08)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06060A08)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C0A08)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06120A08)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06180A08)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E0A08)

#define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_REG                       (0x00000A0C)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x06000A0C)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x06060A0C)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C0A0C)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x06120A0C)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x06180A0C)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E0A0C)

#define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00000A10)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06000A10)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06060A10)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C0A10)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06120A10)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06180A10)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E0A10)

#define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00000A14)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06000A14)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06060A14)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C0A14)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06120A14)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06180A14)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E0A14)

#define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00000A18)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06000A18)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06060A18)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C0A18)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06120A18)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02180A18)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A0A18)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D0A18)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E0A18)

#define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_REG                       (0x00000A1C)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x06000A1C)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x06060A1C)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C0A1C)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x06120A1C)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x06180A1C)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E0A1C)

#define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_REG                       (0x00000A20)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x06000A20)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x06060A20)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C0A20)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x06120A20)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x06180A20)

  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA3CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E0A20)

#define DDRDATA3CH0_CR_DCCDATADCCPILUT0_REG                            (0x00000A24)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x06000A24)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x06060A24)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C0A24)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x06120A24)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x06180A24)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E0A24)

#define DDRDATA3CH0_CR_DCCDATADCCPILUT1_REG                            (0x00000A28)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x06000A28)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x06060A28)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C0A28)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x06120A28)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x06180A28)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E0A28)

#define DDRDATA3CH0_CR_DCCDATADCCPILUT2_REG                            (0x00000A2C)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x06000A2C)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x06060A2C)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C0A2C)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x06120A2C)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x06180A2C)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E0A2C)

#define DDRDATA3CH0_CR_DCCDATADCCPILUT3_REG                            (0x00000A30)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x06000A30)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x06060A30)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C0A30)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x06120A30)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x06180A30)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E0A30)

#define DDRDATA3CH0_CR_DCCDATADCCPILUT4_REG                            (0x00000A34)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x06000A34)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x06060A34)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C0A34)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x06120A34)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x06180A34)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E0A34)

#define DDRDATA3CH0_CR_DCCDATADCCPILUT5_REG                            (0x00000A38)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x06000A38)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x06060A38)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C0A38)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x06120A38)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x06180A38)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E0A38)

#define DDRDATA3CH0_CR_DCCDATADCCPILUT6_REG                            (0x00000A3C)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x06000A3C)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x06060A3C)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C0A3C)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x06120A3C)

  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH0_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x08180A3C)

#define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_REG                        (0x00000A40)

  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x06000A40)

  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x06060A40)

  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C0A40)

  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x06120A40)

  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x06180A40)

  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E0A40)

#define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_REG                        (0x00000A44)

  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x06000A44)

  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x06060A44)

  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C0A44)

  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x06120A44)

  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x06180A44)

  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E0A44)

#define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x00000A48)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x06000A48)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x06060A48)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C0A48)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x06120A48)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x02180A48)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A0A48)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C0A48)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E0A48)

#define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x00000A4C)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x06000A4C)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x06060A4C)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C0A4C)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x06120A4C)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x08180A4C)

#define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x00000A50)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x06000A50)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x06060A50)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C0A50)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x06120A50)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x06180A50)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E0A50)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F0A50)

#define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x00000A54)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x06000A54)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x06060A54)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C0A54)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x06120A54)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x06180A54)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E0A54)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F0A54)

#define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x00000A58)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x06000A58)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x06060A58)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C0A58)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x06120A58)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x06180A58)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E0A58)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F0A58)

#define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x00000A5C)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x06000A5C)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x06060A5C)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C0A5C)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x06120A5C)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x06180A5C)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E0A5C)

  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA3CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F0A5C)

#define DDRDATA3CH1_CR_RXCONTROL0RANK0_REG                             (0x00000A80)

  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B000A80)

  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B0A80)

  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07120A80)

  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07190A80)

#define DDRDATA3CH1_CR_RXCONTROL0RANK1_REG                             (0x00000A84)

  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B000A84)

  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B0A84)

  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07120A84)

  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07190A84)

#define DDRDATA3CH1_CR_RXCONTROL0RANK2_REG                             (0x00000A88)

  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B000A88)

  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B0A88)

  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07120A88)

  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07190A88)

#define DDRDATA3CH1_CR_RXCONTROL0RANK3_REG                             (0x00000A8C)

  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B000A8C)

  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B0A8C)

  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x07120A8C)

  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x07190A8C)

#define DDRDATA3CH1_CR_RXCONTROL1RANK0_REG                             (0x00000A90)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06000A90)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06060A90)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C0A90)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06120A90)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02180A90)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A0A90)

#define DDRDATA3CH1_CR_RXCONTROL1RANK1_REG                             (0x00000A94)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06000A94)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06060A94)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C0A94)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06120A94)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02180A94)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A0A94)

#define DDRDATA3CH1_CR_RXCONTROL1RANK2_REG                             (0x00000A98)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06000A98)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06060A98)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C0A98)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06120A98)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02180A98)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A0A98)

#define DDRDATA3CH1_CR_RXCONTROL1RANK3_REG                             (0x00000A9C)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x06000A9C)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x06060A9C)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C0A9C)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x06120A9C)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x02180A9C)

  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A0A9C)

#define DDRDATA3CH1_CR_TXTRAINRANK0_REG                                (0x00000AA0)

  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A000AA0)

  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A0AA0)

  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxEqualization_HSH               (0x06140AA0)

  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A0AA0)

  #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E0AA0)

#define DDRDATA3CH1_CR_TXTRAINRANK1_REG                                (0x00000AA4)

  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A000AA4)

  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A0AA4)

  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxEqualization_HSH               (0x06140AA4)

  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A0AA4)

  #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C0AA4)

#define DDRDATA3CH1_CR_TXTRAINRANK2_REG                                (0x00000AA8)

  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A000AA8)

  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A0AA8)

  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_TxEqualization_HSH               (0x06140AA8)

  #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A0AA8)

#define DDRDATA3CH1_CR_TXTRAINRANK3_REG                                (0x00000AAC)

  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A000AAC)

  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A0AAC)

  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_TxEqualization_HSH               (0x06140AAC)

  #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA3CH1_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A0AAC)

#define DDRDATA3CH1_CR_TXPERBITLOWRANK0_REG                            (0x00000AB0)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x06000AB0)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x06060AB0)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C0AB0)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x06120AB0)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x08180AB0)

#define DDRDATA3CH1_CR_TXPERBITLOWRANK1_REG                            (0x00000AB4)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x06000AB4)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x06060AB4)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C0AB4)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x06120AB4)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x08180AB4)

#define DDRDATA3CH1_CR_TXPERBITLOWRANK2_REG                            (0x00000AB8)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x06000AB8)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x06060AB8)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C0AB8)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x06120AB8)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x08180AB8)

#define DDRDATA3CH1_CR_TXPERBITLOWRANK3_REG                            (0x00000ABC)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x06000ABC)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x06060ABC)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C0ABC)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x06120ABC)

  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x08180ABC)

#define DDRDATA3CH1_CR_RCOMPDATA0_REG                                  (0x00000AC0)

  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x06000AC0)

  #define DDRDATA3CH1_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA3CH1_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA3CH1_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA3CH1_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA3CH1_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA3CH1_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA3CH1_CR_RCOMPDATA0_Rsvd_HSH                           (0x08060AC0)

  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA3CH1_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E0AC0)

  #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA3CH1_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x05140AC0)

  #define DDRDATA3CH1_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA3CH1_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA3CH1_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA3CH1_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA3CH1_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA3CH1_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA3CH1_CR_RCOMPDATA0_Spare_HSH                          (0x07190AC0)

#define DDRDATA3CH1_CR_RCOMPDATA1_REG                                  (0x00000AC4)

  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x06000AC4)

  #define DDRDATA3CH1_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA3CH1_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA3CH1_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA3CH1_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA3CH1_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA3CH1_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA3CH1_CR_RCOMPDATA1_spare_HSH                          (0x14060AC4)

  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA3CH1_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A0AC4)

#define DDRDATA3CH1_CR_DDRCRDATACONTROL8_REG                           (0x00000AC8)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x02000AC8)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x02020AC8)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x02040AC8)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x02060AC8)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x01080AC8)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL8_spare_HSH                   (0x17090AC8)

#define DDRDATA3CH1_CR_RCOMPDATA2_REG                                  (0x00000ACC)

  #define DDRDATA3CH1_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA3CH1_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA3CH1_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA3CH1_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA3CH1_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA3CH1_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x08000ACC)

  #define DDRDATA3CH1_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA3CH1_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA3CH1_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA3CH1_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA3CH1_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA3CH1_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x08080ACC)

  #define DDRDATA3CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA3CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA3CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA3CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA3CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA3CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x06100ACC)

  #define DDRDATA3CH1_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA3CH1_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA3CH1_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA3CH1_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA3CH1_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA3CH1_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA3CH1_CR_RCOMPDATA2_Spare_HSH                          (0x0A160ACC)

#define DDRDATA3CH1_CR_RXCONTROL2RANK0_REG                             (0x00000AD0)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x06000AD0)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x06060AD0)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C0AD0)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x05110AD0)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x05160AD0)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B0AD0)

#define DDRDATA3CH1_CR_RXCONTROL2RANK1_REG                             (0x00000AD4)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x06000AD4)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x06060AD4)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C0AD4)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x05110AD4)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x05160AD4)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B0AD4)

#define DDRDATA3CH1_CR_RXCONTROL2RANK2_REG                             (0x00000AD8)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x06000AD8)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x06060AD8)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C0AD8)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x05110AD8)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x05160AD8)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B0AD8)

#define DDRDATA3CH1_CR_RXCONTROL2RANK3_REG                             (0x00000ADC)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x06000ADC)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x06060ADC)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C0ADC)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x05110ADC)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x05160ADC)

  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B0ADC)

#define DDRDATA3CH1_CR_DATATRAINFEEDBACK_REG                           (0x00000AE0)

  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x09000AE0)

  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA3CH1_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x17090AE0)

#define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_REG                         (0x00000AE8)

  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x86000AE8)

  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x86060AE8)

  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C0AE8)

  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x85110AE8)

  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x05160AE8)

  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B0AE8)

#define DDRDATA3CH1_CR_DDRCRDATACONTROL1_REG                           (0x00000AEC)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x84000AEC)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x02040AEC)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x01060AEC)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x03070AEC)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A0AEC)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E0AEC)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x03130AEC)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x85160AEC)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B0AEC)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E0AEC)

#define DDRDATA3CH1_CR_DDRCRDATACONTROL2_REG                           (0x00000AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x05000AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x01050AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x01060AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x01070AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x01080AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x04090AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D0AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x01120AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x01130AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x01140AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x01150AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x01160AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x01170AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x01180AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x01190AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A0AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D0AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E0AF0)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F0AF0)

#define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x00000AFC)

  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x86000AFC)

  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x87060AFC)

  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D0AFC)

  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x86130AFC)

  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x87190AFC)

#define DDRDATA3CH1_CR_DDRCRDATACONTROL0_REG                           (0x00000B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01000B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01010B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01020B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01030B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01040B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01050B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01060B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01070B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01080B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01090B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A0B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B0B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C0B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D0B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F0B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02130B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01150B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01160B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01170B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01180B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01190B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A0B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B0B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C0B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D0B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E0B00)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F0B00)

#define DDRDATA3CH1_CR_DDRCRDATACONTROL3_REG                           (0x00000B08)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04000B08)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02040B08)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01060B08)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01070B08)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86080B08)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E0B08)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F0B08)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03100B08)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01130B08)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03140B08)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01170B08)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01180B08)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01190B08)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A0B08)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E0B08)

#define DDRDATA3CH1_CR_DDRCRDATACONTROL4_REG                           (0x00000B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x01000B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x01010B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x03020B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x01050B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x01060B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x01070B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x01080B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x02090B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B0B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C0B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D0B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E0B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F0B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x01100B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x01110B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x01120B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x05130B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x05180B0C)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_spare2_OFF                  (29)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_spare2_WID                  ( 3)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_spare2_MSK                  (0xE0000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_spare2_MIN                  (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_spare2_MAX                  (7) // 0x00000007
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_spare2_DEF                  (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL4_spare2_HSH                  (0x031D0B0C)

#define DDRDATA3CH1_CR_DDRCRDATACONTROL5_REG                           (0x00000B10)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08000B10)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01080B10)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02090B10)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B0B10)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F0B10)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08100B10)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08180B10)

#define DDRDATA3CH1_CR_DDRCRDATACONTROL6_REG                           (0x00000B14)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01000B14)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02010B14)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01030B14)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05040B14)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01090B14)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A0B14)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B0B14)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C0B14)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E0B14)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F0B14)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08100B14)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01180B14)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01190B14)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A0B14)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D0B14)

#define DDRDATA3CH1_CR_DDRCRDATACONTROL7_REG                           (0x00000B18)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06000B18)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06060B18)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C0B18)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06120B18)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04180B18)

  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA3CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C0B18)

#define DDRDATA3CH1_CR_DELTADQSRANK0_REG                               (0x00000B1C)

  #define DDRDATA3CH1_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA3CH1_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA3CH1_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA3CH1_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA3CH1_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA3CH1_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A000B1C)

  #define DDRDATA3CH1_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA3CH1_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA3CH1_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA3CH1_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA3CH1_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA3CH1_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA3CH1_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A0B1C)

#define DDRDATA3CH1_CR_DELTADQSRANK1_REG                               (0x00000B20)

  #define DDRDATA3CH1_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA3CH1_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA3CH1_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA3CH1_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA3CH1_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA3CH1_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A000B20)

  #define DDRDATA3CH1_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA3CH1_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA3CH1_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA3CH1_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA3CH1_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA3CH1_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA3CH1_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A0B20)

#define DDRDATA3CH1_CR_DELTADQSRANK2_REG                               (0x00000B24)

  #define DDRDATA3CH1_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA3CH1_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA3CH1_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA3CH1_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA3CH1_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA3CH1_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A000B24)

  #define DDRDATA3CH1_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA3CH1_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA3CH1_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA3CH1_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA3CH1_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA3CH1_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA3CH1_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A0B24)

#define DDRDATA3CH1_CR_DELTADQSRANK3_REG                               (0x00000B28)

  #define DDRDATA3CH1_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA3CH1_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA3CH1_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA3CH1_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA3CH1_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA3CH1_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A000B28)

  #define DDRDATA3CH1_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA3CH1_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA3CH1_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA3CH1_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA3CH1_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA3CH1_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA3CH1_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A0B28)

#define DDRDATA3CH1_CR_RXCONTROL3RANK0_REG                             (0x00000B2C)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x06000B2C)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x06060B2C)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C0B2C)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x05110B2C)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x05160B2C)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B0B2C)

#define DDRDATA3CH1_CR_RXCONTROL3RANK1_REG                             (0x00000B30)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x06000B30)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x06060B30)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C0B30)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x05110B30)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x05160B30)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B0B30)

#define DDRDATA3CH1_CR_RXCONTROL3RANK2_REG                             (0x00000B34)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x06000B34)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x06060B34)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C0B34)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x05110B34)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x05160B34)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B0B34)

#define DDRDATA3CH1_CR_RXCONTROL3RANK3_REG                             (0x00000B38)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x06000B38)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x06060B38)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C0B38)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x05110B38)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x05160B38)

  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA3CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B0B38)

#define DDRDATA3CH1_CR_TXPERBITHIRANK0_REG                             (0x00000B3C)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x06000B3C)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x06060B3C)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C0B3C)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x06120B3C)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK0_Spare_HSH                     (0x08180B3C)

#define DDRDATA3CH1_CR_TXPERBITHIRANK1_REG                             (0x00000B40)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x06000B40)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x06060B40)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C0B40)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x06120B40)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK1_Spare_HSH                     (0x08180B40)

#define DDRDATA3CH1_CR_TXPERBITHIRANK2_REG                             (0x00000B44)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x06000B44)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x06060B44)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C0B44)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x06120B44)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK2_Spare_HSH                     (0x08180B44)

#define DDRDATA3CH1_CR_TXPERBITHIRANK3_REG                             (0x00000B48)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x06000B48)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x06060B48)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C0B48)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x06120B48)

  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_TXPERBITHIRANK3_Spare_HSH                     (0x08180B48)

#define DDRDATA3CH1_CR_DCCDATACONTROL0_REG                             (0x00000B4C)

  #define DDRDATA3CH1_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x01000B4C)

  #define DDRDATA3CH1_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x02010B4C)

  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x01030B4C)

  #define DDRDATA3CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x02040B4C)

  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x07060B4C)

  #define DDRDATA3CH1_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D0B4C)

  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA3CH1_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C0B4C)

#define DDRDATA3CH1_CR_DCCDATACONTROL1_REG                             (0x00000B50)

  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x06000B50)

  #define DDRDATA3CH1_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x02060B50)

  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x04080B50)

  #define DDRDATA3CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C0B50)

  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E0B50)

  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F0B50)

  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F100B50)

  #define DDRDATA3CH1_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F0B50)

#define DDRDATA3CH1_CR_DCCDATACONTROL2_REG                             (0x00000B54)

  #define DDRDATA3CH1_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x06000B54)

  #define DDRDATA3CH1_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x03060B54)

  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D090B54)

  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x05160B54)

  #define DDRDATA3CH1_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B0B54)

  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C0B54)

#define DDRDATA3CH1_CR_DCCDATACONTROL3_REG                             (0x00000B58)

  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B000B58)

  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B0B58)

  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x09140B58)

  #define DDRDATA3CH1_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D0B58)

#define DDRDATA3CH1_CR_DCCDATACONTROL4_REG                             (0x00000B5C)

  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x09000B5C)

  #define DDRDATA3CH1_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_Spare_HSH                     (0x01090B5C)

  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A0B5C)

  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x06100B5C)

  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x06160B5C)

  #define DDRDATA3CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C0B5C)

#define DDRDATA3CH1_CR_DCCDATACONTROL5_REG                             (0x00000B60)

  #define DDRDATA3CH1_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_Spare_HSH                     (0x02000B60)

  #define DDRDATA3CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x01020B60)

  #define DDRDATA3CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x06030B60)

  #define DDRDATA3CH1_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x05090B60)

  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E0B60)

  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B140B60)

  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F0B60)

#define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_REG                         (0x00000B64)

  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B000B64)

  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B0B64)

  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x09140B64)

  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D0B64)

#define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_REG                         (0x00000B68)

  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x09000B68)

  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x01090B68)

  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A0B68)

  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B0B68)

  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A0B68)

  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B0B68)

#define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_REG                         (0x00000B6C)

  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x10000B6C)

  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x07100B6C)

  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x07170B6C)

  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E0B6C)

#define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x00000B70)

  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B000B70)

  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B0B70)

  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C0B70)

#define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x00000B74)

  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x09000B74)

  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x11090B74)

  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A0B74)

#define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x00000B78)

  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x09000B78)

  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x11090B78)

  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A0B78)

#define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x00000B7C)

  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x09000B7C)

  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x11090B7C)

  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A0B7C)

#define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_REG                        (0x00000B80)

  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06000B80)

  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06060B80)

  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C0B80)

  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06120B80)

  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07180B80)

  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F0B80)

#define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00000B84)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06000B84)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06060B84)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C0B84)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06120B84)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06180B84)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E0B84)

#define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00000B88)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06000B88)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06060B88)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C0B88)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06120B88)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06180B88)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E0B88)

#define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_REG                       (0x00000B8C)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x06000B8C)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x06060B8C)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C0B8C)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x06120B8C)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x06180B8C)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E0B8C)

#define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00000B90)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06000B90)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06060B90)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C0B90)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06120B90)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06180B90)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E0B90)

#define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00000B94)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06000B94)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06060B94)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C0B94)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06120B94)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06180B94)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E0B94)

#define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00000B98)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06000B98)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06060B98)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C0B98)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06120B98)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02180B98)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A0B98)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D0B98)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E0B98)

#define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_REG                       (0x00000B9C)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x06000B9C)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x06060B9C)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C0B9C)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x06120B9C)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x06180B9C)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E0B9C)

#define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_REG                       (0x00000BA0)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x06000BA0)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x06060BA0)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C0BA0)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x06120BA0)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x06180BA0)

  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA3CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E0BA0)

#define DDRDATA3CH1_CR_DCCDATADCCPILUT0_REG                            (0x00000BA4)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x06000BA4)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x06060BA4)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C0BA4)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x06120BA4)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x06180BA4)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E0BA4)

#define DDRDATA3CH1_CR_DCCDATADCCPILUT1_REG                            (0x00000BA8)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x06000BA8)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x06060BA8)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C0BA8)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x06120BA8)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x06180BA8)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E0BA8)

#define DDRDATA3CH1_CR_DCCDATADCCPILUT2_REG                            (0x00000BAC)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x06000BAC)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x06060BAC)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C0BAC)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x06120BAC)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x06180BAC)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E0BAC)

#define DDRDATA3CH1_CR_DCCDATADCCPILUT3_REG                            (0x00000BB0)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x06000BB0)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x06060BB0)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C0BB0)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x06120BB0)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x06180BB0)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E0BB0)

#define DDRDATA3CH1_CR_DCCDATADCCPILUT4_REG                            (0x00000BB4)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x06000BB4)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x06060BB4)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C0BB4)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x06120BB4)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x06180BB4)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E0BB4)

#define DDRDATA3CH1_CR_DCCDATADCCPILUT5_REG                            (0x00000BB8)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x06000BB8)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x06060BB8)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C0BB8)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x06120BB8)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x06180BB8)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E0BB8)

#define DDRDATA3CH1_CR_DCCDATADCCPILUT6_REG                            (0x00000BBC)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x06000BBC)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x06060BBC)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C0BBC)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x06120BBC)

  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA3CH1_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x08180BBC)

#define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_REG                        (0x00000BC0)

  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x06000BC0)

  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x06060BC0)

  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C0BC0)

  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x06120BC0)

  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x06180BC0)

  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E0BC0)

#define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_REG                        (0x00000BC4)

  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x06000BC4)

  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x06060BC4)

  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C0BC4)

  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x06120BC4)

  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x06180BC4)

  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E0BC4)

#define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x00000BC8)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x06000BC8)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x06060BC8)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C0BC8)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x06120BC8)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x02180BC8)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A0BC8)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C0BC8)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E0BC8)

#define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x00000BCC)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x06000BCC)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x06060BCC)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C0BCC)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x06120BCC)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x08180BCC)

#define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x00000BD0)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x06000BD0)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x06060BD0)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C0BD0)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x06120BD0)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x06180BD0)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E0BD0)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F0BD0)

#define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x00000BD4)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x06000BD4)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x06060BD4)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C0BD4)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x06120BD4)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x06180BD4)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E0BD4)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F0BD4)

#define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x00000BD8)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x06000BD8)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x06060BD8)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C0BD8)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x06120BD8)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x06180BD8)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E0BD8)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F0BD8)

#define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x00000BDC)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x06000BDC)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x06060BDC)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C0BDC)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x06120BDC)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x06180BDC)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E0BDC)

  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA3CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F0BDC)

#define DDRDATA4CH0_CR_RXCONTROL0RANK0_REG                             (0x00000C00)

  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B000C00)

  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B0C00)

  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07120C00)

  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07190C00)

#define DDRDATA4CH0_CR_RXCONTROL0RANK1_REG                             (0x00000C04)

  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B000C04)

  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B0C04)

  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07120C04)

  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07190C04)

#define DDRDATA4CH0_CR_RXCONTROL0RANK2_REG                             (0x00000C08)

  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B000C08)

  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B0C08)

  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07120C08)

  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07190C08)

#define DDRDATA4CH0_CR_RXCONTROL0RANK3_REG                             (0x00000C0C)

  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B000C0C)

  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B0C0C)

  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x07120C0C)

  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x07190C0C)

#define DDRDATA4CH0_CR_RXCONTROL1RANK0_REG                             (0x00000C10)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06000C10)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06060C10)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C0C10)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06120C10)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02180C10)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A0C10)

#define DDRDATA4CH0_CR_RXCONTROL1RANK1_REG                             (0x00000C14)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06000C14)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06060C14)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C0C14)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06120C14)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02180C14)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A0C14)

#define DDRDATA4CH0_CR_RXCONTROL1RANK2_REG                             (0x00000C18)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06000C18)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06060C18)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C0C18)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06120C18)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02180C18)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A0C18)

#define DDRDATA4CH0_CR_RXCONTROL1RANK3_REG                             (0x00000C1C)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x06000C1C)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x06060C1C)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C0C1C)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x06120C1C)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x02180C1C)

  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A0C1C)

#define DDRDATA4CH0_CR_TXTRAINRANK0_REG                                (0x00000C20)

  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A000C20)

  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A0C20)

  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxEqualization_HSH               (0x06140C20)

  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A0C20)

  #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E0C20)

#define DDRDATA4CH0_CR_TXTRAINRANK1_REG                                (0x00000C24)

  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A000C24)

  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A0C24)

  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxEqualization_HSH               (0x06140C24)

  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A0C24)

  #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C0C24)

#define DDRDATA4CH0_CR_TXTRAINRANK2_REG                                (0x00000C28)

  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A000C28)

  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A0C28)

  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_TxEqualization_HSH               (0x06140C28)

  #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A0C28)

#define DDRDATA4CH0_CR_TXTRAINRANK3_REG                                (0x00000C2C)

  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A000C2C)

  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A0C2C)

  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_TxEqualization_HSH               (0x06140C2C)

  #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA4CH0_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A0C2C)

#define DDRDATA4CH0_CR_TXPERBITLOWRANK0_REG                            (0x00000C30)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x06000C30)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x06060C30)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C0C30)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x06120C30)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x08180C30)

#define DDRDATA4CH0_CR_TXPERBITLOWRANK1_REG                            (0x00000C34)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x06000C34)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x06060C34)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C0C34)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x06120C34)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x08180C34)

#define DDRDATA4CH0_CR_TXPERBITLOWRANK2_REG                            (0x00000C38)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x06000C38)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x06060C38)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C0C38)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x06120C38)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x08180C38)

#define DDRDATA4CH0_CR_TXPERBITLOWRANK3_REG                            (0x00000C3C)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x06000C3C)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x06060C3C)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C0C3C)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x06120C3C)

  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x08180C3C)

#define DDRDATA4CH0_CR_RCOMPDATA0_REG                                  (0x00000C40)

  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x06000C40)

  #define DDRDATA4CH0_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA4CH0_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA4CH0_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA4CH0_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA4CH0_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA4CH0_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA4CH0_CR_RCOMPDATA0_Rsvd_HSH                           (0x08060C40)

  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA4CH0_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E0C40)

  #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA4CH0_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x05140C40)

  #define DDRDATA4CH0_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA4CH0_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA4CH0_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA4CH0_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA4CH0_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA4CH0_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA4CH0_CR_RCOMPDATA0_Spare_HSH                          (0x07190C40)

#define DDRDATA4CH0_CR_RCOMPDATA1_REG                                  (0x00000C44)

  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x06000C44)

  #define DDRDATA4CH0_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA4CH0_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA4CH0_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA4CH0_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA4CH0_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA4CH0_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA4CH0_CR_RCOMPDATA1_spare_HSH                          (0x14060C44)

  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA4CH0_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A0C44)

#define DDRDATA4CH0_CR_DDRCRDATACONTROL8_REG                           (0x00000C48)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x02000C48)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x02020C48)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x02040C48)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x02060C48)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x01080C48)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL8_spare_HSH                   (0x17090C48)

#define DDRDATA4CH0_CR_RCOMPDATA2_REG                                  (0x00000C4C)

  #define DDRDATA4CH0_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA4CH0_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA4CH0_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA4CH0_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA4CH0_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA4CH0_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x08000C4C)

  #define DDRDATA4CH0_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA4CH0_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA4CH0_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA4CH0_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA4CH0_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA4CH0_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x08080C4C)

  #define DDRDATA4CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA4CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA4CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA4CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA4CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA4CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x06100C4C)

  #define DDRDATA4CH0_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA4CH0_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA4CH0_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA4CH0_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA4CH0_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA4CH0_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA4CH0_CR_RCOMPDATA2_Spare_HSH                          (0x0A160C4C)

#define DDRDATA4CH0_CR_RXCONTROL2RANK0_REG                             (0x00000C50)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x06000C50)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x06060C50)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C0C50)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x05110C50)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x05160C50)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B0C50)

#define DDRDATA4CH0_CR_RXCONTROL2RANK1_REG                             (0x00000C54)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x06000C54)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x06060C54)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C0C54)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x05110C54)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x05160C54)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B0C54)

#define DDRDATA4CH0_CR_RXCONTROL2RANK2_REG                             (0x00000C58)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x06000C58)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x06060C58)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C0C58)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x05110C58)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x05160C58)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B0C58)

#define DDRDATA4CH0_CR_RXCONTROL2RANK3_REG                             (0x00000C5C)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x06000C5C)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x06060C5C)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C0C5C)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x05110C5C)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x05160C5C)

  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B0C5C)

#define DDRDATA4CH0_CR_DATATRAINFEEDBACK_REG                           (0x00000C60)

  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x09000C60)

  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA4CH0_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x17090C60)

#define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_REG                         (0x00000C68)

  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x86000C68)

  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x86060C68)

  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C0C68)

  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x85110C68)

  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x05160C68)

  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B0C68)

#define DDRDATA4CH0_CR_DDRCRDATACONTROL1_REG                           (0x00000C6C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x84000C6C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x02040C6C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x01060C6C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x03070C6C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A0C6C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E0C6C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x03130C6C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x85160C6C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B0C6C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E0C6C)

#define DDRDATA4CH0_CR_DDRCRDATACONTROL2_REG                           (0x00000C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x05000C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x01050C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x01060C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x01070C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x01080C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x04090C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D0C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x01120C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x01130C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x01140C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x01150C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x01160C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x01170C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x01180C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x01190C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A0C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D0C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E0C70)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F0C70)

#define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x00000C7C)

  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x86000C7C)

  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x87060C7C)

  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D0C7C)

  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x86130C7C)

  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x87190C7C)

#define DDRDATA4CH0_CR_DDRCRDATACONTROL0_REG                           (0x00000C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01000C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01010C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01020C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01030C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01040C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01050C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01060C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01070C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01080C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01090C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A0C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B0C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C0C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D0C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F0C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02130C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01150C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01160C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01170C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01180C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01190C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A0C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B0C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C0C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D0C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E0C80)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F0C80)

#define DDRDATA4CH0_CR_DDRCRDATACONTROL3_REG                           (0x00000C88)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04000C88)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02040C88)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01060C88)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01070C88)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86080C88)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E0C88)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F0C88)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03100C88)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01130C88)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03140C88)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01170C88)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01180C88)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01190C88)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A0C88)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E0C88)

#define DDRDATA4CH0_CR_DDRCRDATACONTROL4_REG                           (0x00000C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x01000C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x01010C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x03020C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x01050C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x01060C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x01070C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x01080C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x02090C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B0C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C0C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D0C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E0C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F0C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x01100C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x01110C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x01120C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x05130C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x05180C8C)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_spare2_OFF                  (29)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_spare2_WID                  ( 3)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_spare2_MSK                  (0xE0000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_spare2_MIN                  (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_spare2_MAX                  (7) // 0x00000007
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_spare2_DEF                  (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL4_spare2_HSH                  (0x031D0C8C)

#define DDRDATA4CH0_CR_DDRCRDATACONTROL5_REG                           (0x00000C90)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08000C90)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01080C90)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02090C90)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B0C90)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F0C90)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08100C90)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08180C90)

#define DDRDATA4CH0_CR_DDRCRDATACONTROL6_REG                           (0x00000C94)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01000C94)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02010C94)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01030C94)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05040C94)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01090C94)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A0C94)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B0C94)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C0C94)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E0C94)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F0C94)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08100C94)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01180C94)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01190C94)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A0C94)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D0C94)

#define DDRDATA4CH0_CR_DDRCRDATACONTROL7_REG                           (0x00000C98)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06000C98)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06060C98)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C0C98)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06120C98)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04180C98)

  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA4CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C0C98)

#define DDRDATA4CH0_CR_DELTADQSRANK0_REG                               (0x00000C9C)

  #define DDRDATA4CH0_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA4CH0_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA4CH0_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA4CH0_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA4CH0_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA4CH0_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A000C9C)

  #define DDRDATA4CH0_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA4CH0_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA4CH0_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA4CH0_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA4CH0_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA4CH0_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA4CH0_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A0C9C)

#define DDRDATA4CH0_CR_DELTADQSRANK1_REG                               (0x00000CA0)

  #define DDRDATA4CH0_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA4CH0_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA4CH0_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA4CH0_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA4CH0_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA4CH0_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A000CA0)

  #define DDRDATA4CH0_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA4CH0_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA4CH0_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA4CH0_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA4CH0_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA4CH0_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA4CH0_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A0CA0)

#define DDRDATA4CH0_CR_DELTADQSRANK2_REG                               (0x00000CA4)

  #define DDRDATA4CH0_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA4CH0_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA4CH0_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA4CH0_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA4CH0_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA4CH0_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A000CA4)

  #define DDRDATA4CH0_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA4CH0_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA4CH0_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA4CH0_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA4CH0_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA4CH0_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA4CH0_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A0CA4)

#define DDRDATA4CH0_CR_DELTADQSRANK3_REG                               (0x00000CA8)

  #define DDRDATA4CH0_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA4CH0_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA4CH0_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA4CH0_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA4CH0_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA4CH0_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A000CA8)

  #define DDRDATA4CH0_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA4CH0_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA4CH0_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA4CH0_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA4CH0_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA4CH0_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA4CH0_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A0CA8)

#define DDRDATA4CH0_CR_RXCONTROL3RANK0_REG                             (0x00000CAC)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x06000CAC)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x06060CAC)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C0CAC)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x05110CAC)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x05160CAC)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B0CAC)

#define DDRDATA4CH0_CR_RXCONTROL3RANK1_REG                             (0x00000CB0)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x06000CB0)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x06060CB0)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C0CB0)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x05110CB0)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x05160CB0)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B0CB0)

#define DDRDATA4CH0_CR_RXCONTROL3RANK2_REG                             (0x00000CB4)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x06000CB4)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x06060CB4)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C0CB4)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x05110CB4)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x05160CB4)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B0CB4)

#define DDRDATA4CH0_CR_RXCONTROL3RANK3_REG                             (0x00000CB8)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x06000CB8)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x06060CB8)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C0CB8)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x05110CB8)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x05160CB8)

  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B0CB8)

#define DDRDATA4CH0_CR_TXPERBITHIRANK0_REG                             (0x00000CBC)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x06000CBC)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x06060CBC)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C0CBC)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x06120CBC)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK0_Spare_HSH                     (0x08180CBC)

#define DDRDATA4CH0_CR_TXPERBITHIRANK1_REG                             (0x00000CC0)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x06000CC0)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x06060CC0)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C0CC0)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x06120CC0)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK1_Spare_HSH                     (0x08180CC0)

#define DDRDATA4CH0_CR_TXPERBITHIRANK2_REG                             (0x00000CC4)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x06000CC4)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x06060CC4)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C0CC4)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x06120CC4)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK2_Spare_HSH                     (0x08180CC4)

#define DDRDATA4CH0_CR_TXPERBITHIRANK3_REG                             (0x00000CC8)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x06000CC8)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x06060CC8)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C0CC8)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x06120CC8)

  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_TXPERBITHIRANK3_Spare_HSH                     (0x08180CC8)

#define DDRDATA4CH0_CR_DCCDATACONTROL0_REG                             (0x00000CCC)

  #define DDRDATA4CH0_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x01000CCC)

  #define DDRDATA4CH0_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x02010CCC)

  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x01030CCC)

  #define DDRDATA4CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x02040CCC)

  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x07060CCC)

  #define DDRDATA4CH0_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D0CCC)

  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA4CH0_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C0CCC)

#define DDRDATA4CH0_CR_DCCDATACONTROL1_REG                             (0x00000CD0)

  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x06000CD0)

  #define DDRDATA4CH0_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x02060CD0)

  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x04080CD0)

  #define DDRDATA4CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C0CD0)

  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E0CD0)

  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F0CD0)

  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F100CD0)

  #define DDRDATA4CH0_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F0CD0)

#define DDRDATA4CH0_CR_DCCDATACONTROL2_REG                             (0x00000CD4)

  #define DDRDATA4CH0_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x06000CD4)

  #define DDRDATA4CH0_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x03060CD4)

  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D090CD4)

  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x05160CD4)

  #define DDRDATA4CH0_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B0CD4)

  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C0CD4)

#define DDRDATA4CH0_CR_DCCDATACONTROL3_REG                             (0x00000CD8)

  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B000CD8)

  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B0CD8)

  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x09140CD8)

  #define DDRDATA4CH0_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D0CD8)

#define DDRDATA4CH0_CR_DCCDATACONTROL4_REG                             (0x00000CDC)

  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x09000CDC)

  #define DDRDATA4CH0_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_Spare_HSH                     (0x01090CDC)

  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A0CDC)

  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x06100CDC)

  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x06160CDC)

  #define DDRDATA4CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C0CDC)

#define DDRDATA4CH0_CR_DCCDATACONTROL5_REG                             (0x00000CE0)

  #define DDRDATA4CH0_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_Spare_HSH                     (0x02000CE0)

  #define DDRDATA4CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x01020CE0)

  #define DDRDATA4CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x06030CE0)

  #define DDRDATA4CH0_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x05090CE0)

  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E0CE0)

  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B140CE0)

  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F0CE0)

#define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_REG                         (0x00000CE4)

  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B000CE4)

  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B0CE4)

  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x09140CE4)

  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D0CE4)

#define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_REG                         (0x00000CE8)

  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x09000CE8)

  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x01090CE8)

  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A0CE8)

  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B0CE8)

  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A0CE8)

  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B0CE8)

#define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_REG                         (0x00000CEC)

  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x10000CEC)

  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x07100CEC)

  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x07170CEC)

  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E0CEC)

#define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x00000CF0)

  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B000CF0)

  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B0CF0)

  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C0CF0)

#define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x00000CF4)

  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x09000CF4)

  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x11090CF4)

  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A0CF4)

#define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x00000CF8)

  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x09000CF8)

  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x11090CF8)

  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A0CF8)

#define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x00000CFC)

  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x09000CFC)

  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x11090CFC)

  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A0CFC)

#define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_REG                        (0x00000D00)

  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06000D00)

  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06060D00)

  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C0D00)

  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06120D00)

  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07180D00)

  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F0D00)

#define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00000D04)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06000D04)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06060D04)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C0D04)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06120D04)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06180D04)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E0D04)

#define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00000D08)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06000D08)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06060D08)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C0D08)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06120D08)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06180D08)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E0D08)

#define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_REG                       (0x00000D0C)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x06000D0C)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x06060D0C)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C0D0C)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x06120D0C)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x06180D0C)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E0D0C)

#define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00000D10)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06000D10)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06060D10)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C0D10)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06120D10)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06180D10)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E0D10)

#define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00000D14)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06000D14)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06060D14)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C0D14)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06120D14)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06180D14)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E0D14)

#define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00000D18)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06000D18)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06060D18)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C0D18)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06120D18)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02180D18)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A0D18)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D0D18)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E0D18)

#define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_REG                       (0x00000D1C)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x06000D1C)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x06060D1C)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C0D1C)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x06120D1C)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x06180D1C)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E0D1C)

#define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_REG                       (0x00000D20)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x06000D20)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x06060D20)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C0D20)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x06120D20)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x06180D20)

  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA4CH0_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E0D20)

#define DDRDATA4CH0_CR_DCCDATADCCPILUT0_REG                            (0x00000D24)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x06000D24)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x06060D24)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C0D24)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x06120D24)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x06180D24)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E0D24)

#define DDRDATA4CH0_CR_DCCDATADCCPILUT1_REG                            (0x00000D28)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x06000D28)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x06060D28)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C0D28)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x06120D28)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x06180D28)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E0D28)

#define DDRDATA4CH0_CR_DCCDATADCCPILUT2_REG                            (0x00000D2C)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x06000D2C)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x06060D2C)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C0D2C)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x06120D2C)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x06180D2C)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E0D2C)

#define DDRDATA4CH0_CR_DCCDATADCCPILUT3_REG                            (0x00000D30)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x06000D30)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x06060D30)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C0D30)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x06120D30)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x06180D30)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E0D30)

#define DDRDATA4CH0_CR_DCCDATADCCPILUT4_REG                            (0x00000D34)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x06000D34)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x06060D34)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C0D34)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x06120D34)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x06180D34)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E0D34)

#define DDRDATA4CH0_CR_DCCDATADCCPILUT5_REG                            (0x00000D38)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x06000D38)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x06060D38)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C0D38)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x06120D38)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x06180D38)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E0D38)

#define DDRDATA4CH0_CR_DCCDATADCCPILUT6_REG                            (0x00000D3C)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x06000D3C)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x06060D3C)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C0D3C)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x06120D3C)

  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH0_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x08180D3C)

#define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_REG                        (0x00000D40)

  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x06000D40)

  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x06060D40)

  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C0D40)

  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x06120D40)

  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x06180D40)

  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E0D40)

#define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_REG                        (0x00000D44)

  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x06000D44)

  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x06060D44)

  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C0D44)

  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x06120D44)

  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x06180D44)

  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E0D44)

#define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x00000D48)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x06000D48)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x06060D48)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C0D48)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x06120D48)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x02180D48)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A0D48)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C0D48)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E0D48)

#define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x00000D4C)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x06000D4C)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x06060D4C)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C0D4C)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x06120D4C)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x08180D4C)

#define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x00000D50)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x06000D50)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x06060D50)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C0D50)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x06120D50)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x06180D50)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E0D50)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F0D50)

#define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x00000D54)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x06000D54)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x06060D54)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C0D54)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x06120D54)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x06180D54)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E0D54)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F0D54)

#define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x00000D58)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x06000D58)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x06060D58)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C0D58)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x06120D58)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x06180D58)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E0D58)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F0D58)

#define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x00000D5C)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x06000D5C)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x06060D5C)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C0D5C)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x06120D5C)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x06180D5C)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E0D5C)

  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA4CH0_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F0D5C)

#define DDRDATA4CH1_CR_RXCONTROL0RANK0_REG                             (0x00000D80)

  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B000D80)

  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B0D80)

  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07120D80)

  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07190D80)

#define DDRDATA4CH1_CR_RXCONTROL0RANK1_REG                             (0x00000D84)

  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B000D84)

  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B0D84)

  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07120D84)

  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07190D84)

#define DDRDATA4CH1_CR_RXCONTROL0RANK2_REG                             (0x00000D88)

  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B000D88)

  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B0D88)

  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07120D88)

  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07190D88)

#define DDRDATA4CH1_CR_RXCONTROL0RANK3_REG                             (0x00000D8C)

  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B000D8C)

  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B0D8C)

  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x07120D8C)

  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x07190D8C)

#define DDRDATA4CH1_CR_RXCONTROL1RANK0_REG                             (0x00000D90)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06000D90)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06060D90)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C0D90)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06120D90)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02180D90)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A0D90)

#define DDRDATA4CH1_CR_RXCONTROL1RANK1_REG                             (0x00000D94)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06000D94)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06060D94)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C0D94)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06120D94)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02180D94)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A0D94)

#define DDRDATA4CH1_CR_RXCONTROL1RANK2_REG                             (0x00000D98)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06000D98)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06060D98)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C0D98)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06120D98)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02180D98)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A0D98)

#define DDRDATA4CH1_CR_RXCONTROL1RANK3_REG                             (0x00000D9C)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x06000D9C)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x06060D9C)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C0D9C)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x06120D9C)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x02180D9C)

  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A0D9C)

#define DDRDATA4CH1_CR_TXTRAINRANK0_REG                                (0x00000DA0)

  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A000DA0)

  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A0DA0)

  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxEqualization_HSH               (0x06140DA0)

  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A0DA0)

  #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E0DA0)

#define DDRDATA4CH1_CR_TXTRAINRANK1_REG                                (0x00000DA4)

  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A000DA4)

  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A0DA4)

  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxEqualization_HSH               (0x06140DA4)

  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A0DA4)

  #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C0DA4)

#define DDRDATA4CH1_CR_TXTRAINRANK2_REG                                (0x00000DA8)

  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A000DA8)

  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A0DA8)

  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_TxEqualization_HSH               (0x06140DA8)

  #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A0DA8)

#define DDRDATA4CH1_CR_TXTRAINRANK3_REG                                (0x00000DAC)

  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A000DAC)

  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A0DAC)

  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_TxEqualization_HSH               (0x06140DAC)

  #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA4CH1_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A0DAC)

#define DDRDATA4CH1_CR_TXPERBITLOWRANK0_REG                            (0x00000DB0)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x06000DB0)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x06060DB0)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C0DB0)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x06120DB0)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x08180DB0)

#define DDRDATA4CH1_CR_TXPERBITLOWRANK1_REG                            (0x00000DB4)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x06000DB4)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x06060DB4)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C0DB4)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x06120DB4)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x08180DB4)

#define DDRDATA4CH1_CR_TXPERBITLOWRANK2_REG                            (0x00000DB8)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x06000DB8)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x06060DB8)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C0DB8)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x06120DB8)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x08180DB8)

#define DDRDATA4CH1_CR_TXPERBITLOWRANK3_REG                            (0x00000DBC)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x06000DBC)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x06060DBC)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C0DBC)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x06120DBC)

  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x08180DBC)

#define DDRDATA4CH1_CR_RCOMPDATA0_REG                                  (0x00000DC0)

  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x06000DC0)

  #define DDRDATA4CH1_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA4CH1_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA4CH1_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA4CH1_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA4CH1_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA4CH1_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA4CH1_CR_RCOMPDATA0_Rsvd_HSH                           (0x08060DC0)

  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA4CH1_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E0DC0)

  #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA4CH1_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x05140DC0)

  #define DDRDATA4CH1_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA4CH1_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA4CH1_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA4CH1_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA4CH1_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA4CH1_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA4CH1_CR_RCOMPDATA0_Spare_HSH                          (0x07190DC0)

#define DDRDATA4CH1_CR_RCOMPDATA1_REG                                  (0x00000DC4)

  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x06000DC4)

  #define DDRDATA4CH1_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA4CH1_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA4CH1_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA4CH1_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA4CH1_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA4CH1_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA4CH1_CR_RCOMPDATA1_spare_HSH                          (0x14060DC4)

  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA4CH1_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A0DC4)

#define DDRDATA4CH1_CR_DDRCRDATACONTROL8_REG                           (0x00000DC8)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x02000DC8)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x02020DC8)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x02040DC8)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x02060DC8)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x01080DC8)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL8_spare_HSH                   (0x17090DC8)

#define DDRDATA4CH1_CR_RCOMPDATA2_REG                                  (0x00000DCC)

  #define DDRDATA4CH1_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA4CH1_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA4CH1_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA4CH1_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA4CH1_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA4CH1_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x08000DCC)

  #define DDRDATA4CH1_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA4CH1_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA4CH1_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA4CH1_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA4CH1_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA4CH1_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x08080DCC)

  #define DDRDATA4CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA4CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA4CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA4CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA4CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA4CH1_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x06100DCC)

  #define DDRDATA4CH1_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA4CH1_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA4CH1_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA4CH1_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA4CH1_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA4CH1_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA4CH1_CR_RCOMPDATA2_Spare_HSH                          (0x0A160DCC)

#define DDRDATA4CH1_CR_RXCONTROL2RANK0_REG                             (0x00000DD0)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x06000DD0)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x06060DD0)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C0DD0)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x05110DD0)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x05160DD0)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B0DD0)

#define DDRDATA4CH1_CR_RXCONTROL2RANK1_REG                             (0x00000DD4)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x06000DD4)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x06060DD4)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C0DD4)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x05110DD4)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x05160DD4)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B0DD4)

#define DDRDATA4CH1_CR_RXCONTROL2RANK2_REG                             (0x00000DD8)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x06000DD8)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x06060DD8)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C0DD8)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x05110DD8)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x05160DD8)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B0DD8)

#define DDRDATA4CH1_CR_RXCONTROL2RANK3_REG                             (0x00000DDC)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x06000DDC)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x06060DDC)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C0DDC)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x05110DDC)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x05160DDC)

  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B0DDC)

#define DDRDATA4CH1_CR_DATATRAINFEEDBACK_REG                           (0x00000DE0)

  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x09000DE0)

  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA4CH1_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x17090DE0)

#define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_REG                         (0x00000DE8)

  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x86000DE8)

  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x86060DE8)

  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C0DE8)

  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x85110DE8)

  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x05160DE8)

  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B0DE8)

#define DDRDATA4CH1_CR_DDRCRDATACONTROL1_REG                           (0x00000DEC)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x84000DEC)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x02040DEC)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x01060DEC)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x03070DEC)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A0DEC)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E0DEC)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x03130DEC)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x85160DEC)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B0DEC)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E0DEC)

#define DDRDATA4CH1_CR_DDRCRDATACONTROL2_REG                           (0x00000DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x05000DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x01050DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x01060DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x01070DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x01080DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x04090DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D0DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x01120DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x01130DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x01140DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x01150DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x01160DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x01170DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x01180DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x01190DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A0DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D0DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E0DF0)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F0DF0)

#define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x00000DFC)

  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x86000DFC)

  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x87060DFC)

  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D0DFC)

  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x86130DFC)

  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x87190DFC)

#define DDRDATA4CH1_CR_DDRCRDATACONTROL0_REG                           (0x00000E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01000E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01010E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01020E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01030E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01040E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01050E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01060E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01070E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01080E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01090E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A0E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B0E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C0E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D0E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F0E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02130E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01150E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01160E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01170E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01180E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01190E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A0E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B0E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C0E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D0E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E0E00)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F0E00)

#define DDRDATA4CH1_CR_DDRCRDATACONTROL3_REG                           (0x00000E08)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04000E08)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02040E08)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01060E08)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01070E08)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86080E08)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E0E08)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F0E08)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03100E08)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01130E08)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03140E08)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01170E08)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01180E08)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01190E08)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A0E08)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E0E08)

#define DDRDATA4CH1_CR_DDRCRDATACONTROL4_REG                           (0x00000E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x01000E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x01010E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x03020E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x01050E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x01060E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x01070E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x01080E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x02090E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B0E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C0E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D0E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E0E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F0E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x01100E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x01110E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x01120E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x05130E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x05180E0C)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_spare2_OFF                  (29)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_spare2_WID                  ( 3)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_spare2_MSK                  (0xE0000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_spare2_MIN                  (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_spare2_MAX                  (7) // 0x00000007
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_spare2_DEF                  (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL4_spare2_HSH                  (0x031D0E0C)

#define DDRDATA4CH1_CR_DDRCRDATACONTROL5_REG                           (0x00000E10)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08000E10)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01080E10)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02090E10)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B0E10)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F0E10)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08100E10)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08180E10)

#define DDRDATA4CH1_CR_DDRCRDATACONTROL6_REG                           (0x00000E14)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01000E14)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02010E14)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01030E14)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05040E14)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01090E14)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A0E14)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B0E14)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C0E14)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E0E14)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F0E14)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08100E14)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01180E14)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01190E14)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A0E14)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D0E14)

#define DDRDATA4CH1_CR_DDRCRDATACONTROL7_REG                           (0x00000E18)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06000E18)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06060E18)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C0E18)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06120E18)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04180E18)

  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA4CH1_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C0E18)

#define DDRDATA4CH1_CR_DELTADQSRANK0_REG                               (0x00000E1C)

  #define DDRDATA4CH1_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA4CH1_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA4CH1_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA4CH1_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA4CH1_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA4CH1_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A000E1C)

  #define DDRDATA4CH1_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA4CH1_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA4CH1_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA4CH1_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA4CH1_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA4CH1_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA4CH1_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A0E1C)

#define DDRDATA4CH1_CR_DELTADQSRANK1_REG                               (0x00000E20)

  #define DDRDATA4CH1_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA4CH1_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA4CH1_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA4CH1_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA4CH1_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA4CH1_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A000E20)

  #define DDRDATA4CH1_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA4CH1_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA4CH1_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA4CH1_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA4CH1_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA4CH1_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA4CH1_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A0E20)

#define DDRDATA4CH1_CR_DELTADQSRANK2_REG                               (0x00000E24)

  #define DDRDATA4CH1_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA4CH1_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA4CH1_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA4CH1_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA4CH1_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA4CH1_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A000E24)

  #define DDRDATA4CH1_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA4CH1_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA4CH1_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA4CH1_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA4CH1_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA4CH1_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA4CH1_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A0E24)

#define DDRDATA4CH1_CR_DELTADQSRANK3_REG                               (0x00000E28)

  #define DDRDATA4CH1_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA4CH1_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA4CH1_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA4CH1_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA4CH1_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA4CH1_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A000E28)

  #define DDRDATA4CH1_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA4CH1_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA4CH1_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA4CH1_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA4CH1_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA4CH1_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA4CH1_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A0E28)

#define DDRDATA4CH1_CR_RXCONTROL3RANK0_REG                             (0x00000E2C)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x06000E2C)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x06060E2C)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C0E2C)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x05110E2C)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x05160E2C)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B0E2C)

#define DDRDATA4CH1_CR_RXCONTROL3RANK1_REG                             (0x00000E30)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x06000E30)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x06060E30)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C0E30)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x05110E30)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x05160E30)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B0E30)

#define DDRDATA4CH1_CR_RXCONTROL3RANK2_REG                             (0x00000E34)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x06000E34)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x06060E34)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C0E34)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x05110E34)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x05160E34)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B0E34)

#define DDRDATA4CH1_CR_RXCONTROL3RANK3_REG                             (0x00000E38)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x06000E38)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x06060E38)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C0E38)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x05110E38)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x05160E38)

  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA4CH1_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B0E38)

#define DDRDATA4CH1_CR_TXPERBITHIRANK0_REG                             (0x00000E3C)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x06000E3C)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x06060E3C)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C0E3C)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x06120E3C)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK0_Spare_HSH                     (0x08180E3C)

#define DDRDATA4CH1_CR_TXPERBITHIRANK1_REG                             (0x00000E40)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x06000E40)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x06060E40)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C0E40)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x06120E40)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK1_Spare_HSH                     (0x08180E40)

#define DDRDATA4CH1_CR_TXPERBITHIRANK2_REG                             (0x00000E44)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x06000E44)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x06060E44)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C0E44)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x06120E44)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK2_Spare_HSH                     (0x08180E44)

#define DDRDATA4CH1_CR_TXPERBITHIRANK3_REG                             (0x00000E48)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x06000E48)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x06060E48)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C0E48)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x06120E48)

  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_TXPERBITHIRANK3_Spare_HSH                     (0x08180E48)

#define DDRDATA4CH1_CR_DCCDATACONTROL0_REG                             (0x00000E4C)

  #define DDRDATA4CH1_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x01000E4C)

  #define DDRDATA4CH1_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x02010E4C)

  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x01030E4C)

  #define DDRDATA4CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x02040E4C)

  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x07060E4C)

  #define DDRDATA4CH1_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D0E4C)

  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA4CH1_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C0E4C)

#define DDRDATA4CH1_CR_DCCDATACONTROL1_REG                             (0x00000E50)

  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x06000E50)

  #define DDRDATA4CH1_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x02060E50)

  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x04080E50)

  #define DDRDATA4CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C0E50)

  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E0E50)

  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F0E50)

  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F100E50)

  #define DDRDATA4CH1_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F0E50)

#define DDRDATA4CH1_CR_DCCDATACONTROL2_REG                             (0x00000E54)

  #define DDRDATA4CH1_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x06000E54)

  #define DDRDATA4CH1_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x03060E54)

  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D090E54)

  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x05160E54)

  #define DDRDATA4CH1_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B0E54)

  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C0E54)

#define DDRDATA4CH1_CR_DCCDATACONTROL3_REG                             (0x00000E58)

  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B000E58)

  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B0E58)

  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x09140E58)

  #define DDRDATA4CH1_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D0E58)

#define DDRDATA4CH1_CR_DCCDATACONTROL4_REG                             (0x00000E5C)

  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x09000E5C)

  #define DDRDATA4CH1_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_Spare_HSH                     (0x01090E5C)

  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A0E5C)

  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x06100E5C)

  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x06160E5C)

  #define DDRDATA4CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C0E5C)

#define DDRDATA4CH1_CR_DCCDATACONTROL5_REG                             (0x00000E60)

  #define DDRDATA4CH1_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_Spare_HSH                     (0x02000E60)

  #define DDRDATA4CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x01020E60)

  #define DDRDATA4CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x06030E60)

  #define DDRDATA4CH1_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x05090E60)

  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E0E60)

  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B140E60)

  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F0E60)

#define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_REG                         (0x00000E64)

  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B000E64)

  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B0E64)

  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x09140E64)

  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D0E64)

#define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_REG                         (0x00000E68)

  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x09000E68)

  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x01090E68)

  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A0E68)

  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B0E68)

  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A0E68)

  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B0E68)

#define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_REG                         (0x00000E6C)

  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x10000E6C)

  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x07100E6C)

  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x07170E6C)

  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E0E6C)

#define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x00000E70)

  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B000E70)

  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B0E70)

  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C0E70)

#define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x00000E74)

  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x09000E74)

  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x11090E74)

  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A0E74)

#define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x00000E78)

  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x09000E78)

  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x11090E78)

  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A0E78)

#define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x00000E7C)

  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x09000E7C)

  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x11090E7C)

  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A0E7C)

#define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_REG                        (0x00000E80)

  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_OFF    ( 0)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_WID    ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MSK    (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MIN    (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_DEF    (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp0_HSH    (0x06000E80)

  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_OFF    ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_WID    ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MSK    (0x00000FC0)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MIN    (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_DEF    (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp1_HSH    (0x06060E80)

  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_OFF    (12)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_WID    ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MSK    (0x0003F000)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MIN    (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_DEF    (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp2_HSH    (0x060C0E80)

  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_OFF    (18)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_WID    ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MSK    (0x00FC0000)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MIN    (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_DEF    (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaTrain_GVp3_HSH    (0x06120E80)

  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_OFF    (24)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_WID    ( 7)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MSK    (0x7F000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MIN    (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_MAX    (127) // 0x0000007F
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_ReplicaOffsetPrev_HSH    (0x07180E80)

  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_Spare_OFF                (31)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_Spare_WID                ( 1)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_Spare_MSK                (0x80000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_Spare_MIN                (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_Spare_MAX                (1) // 0x00000001
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_Spare_DEF                (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINREPLICA0_Spare_HSH                (0x011F0E80)

#define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_REG                       (0x00000E84)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_OFF           ( 0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq0DccVal_HSH           (0x06000E84)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_OFF           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq1DccVal_HSH           (0x06060E84)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_OFF           (12)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq2DccVal_HSH           (0x060C0E84)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_OFF           (18)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq3DccVal_HSH           (0x06120E84)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_OFF           (24)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_Dq4DccVal_HSH           (0x06180E84)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_OFF          (30)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_WID          ( 2)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK0_DqDccAipCb_HSH          (0x021E0E84)

#define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_REG                       (0x00000E88)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_OFF           ( 0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq0DccVal_HSH           (0x06000E88)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_OFF           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq1DccVal_HSH           (0x06060E88)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_OFF           (12)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq2DccVal_HSH           (0x060C0E88)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_OFF           (18)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq3DccVal_HSH           (0x06120E88)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_OFF           (24)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_Dq4DccVal_HSH           (0x06180E88)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_OFF          (30)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_WID          ( 2)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK1_DqDccAipCb_HSH          (0x021E0E88)

#define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_REG                       (0x00000E8C)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_OFF           ( 0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq0DccVal_HSH           (0x06000E8C)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_OFF           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq1DccVal_HSH           (0x06060E8C)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_OFF           (12)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq2DccVal_HSH           (0x060C0E8C)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_OFF           (18)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq3DccVal_HSH           (0x06120E8C)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_OFF           (24)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_Dq4DccVal_HSH           (0x06180E8C)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_OFF          (30)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_WID          ( 2)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK2_DqDccAipCb_HSH          (0x021E0E8C)

#define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_REG                       (0x00000E90)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_OFF           ( 0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MSK           (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq0DccVal_HSH           (0x06000E90)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_OFF           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MSK           (0x00000FC0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq1DccVal_HSH           (0x06060E90)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_OFF           (12)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MSK           (0x0003F000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq2DccVal_HSH           (0x060C0E90)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_OFF           (18)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MSK           (0x00FC0000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq3DccVal_HSH           (0x06120E90)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_OFF           (24)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MSK           (0x3F000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_Dq4DccVal_HSH           (0x06180E90)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_OFF          (30)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_WID          ( 2)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MSK          (0xC0000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_MAX          (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_DEF          (0x00000001)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL0RANK3_DqDccAipCb_HSH          (0x021E0E90)

#define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_REG                       (0x00000E94)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_OFF           ( 0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq5DccVal_HSH           (0x06000E94)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_OFF           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq6DccVal_HSH           (0x06060E94)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_OFF           (12)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_Dq7DccVal_HSH           (0x060C0E94)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_OFF           (18)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccVal_HSH           (0x06120E94)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_OFF (24)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_WID ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MSK (0x3F000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MIN (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_MAX (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_DEF (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_ReplicaShadowDccVal_HSH (0x06180E94)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_OFF         (30)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_WID         ( 2)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MIN         (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK0_DqsDccAipCb_HSH         (0x021E0E94)

#define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_REG                       (0x00000E98)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_OFF           ( 0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq5DccVal_HSH           (0x06000E98)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_OFF           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq6DccVal_HSH           (0x06060E98)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_OFF           (12)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_Dq7DccVal_HSH           (0x060C0E98)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_OFF           (18)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccVal_HSH           (0x06120E98)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_spare2_OFF              (24)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_spare2_WID              ( 2)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MSK              (0x03000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MIN              (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_spare2_MAX              (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_spare2_DEF              (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_spare2_HSH              (0x02180E98)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_OFF (26)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_WID ( 3)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MSK (0x1C000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MIN (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_MAX (7) // 0x00000007
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_DEF (0x00000005)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_binfsmsteptosavecnts_HSH (0x031A0E98)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_OFF (29)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_WID ( 1)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MSK (0x20000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MIN (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_MAX (1) // 0x00000001
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_DEF (0x00000001)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_savecntsatchosenbinstep_HSH (0x011D0E98)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_OFF         (30)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_WID         ( 2)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MIN         (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK1_DqsDccAipCb_HSH         (0x021E0E98)

#define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_REG                       (0x00000E9C)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_OFF           ( 0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq5DccVal_HSH           (0x06000E9C)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_OFF           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq6DccVal_HSH           (0x06060E9C)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_OFF           (12)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Dq7DccVal_HSH           (0x060C0E9C)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_OFF           (18)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccVal_HSH           (0x06120E9C)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Spare_OFF               (24)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Spare_WID               ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MSK               (0x3F000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MIN               (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Spare_DEF               (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_Spare_HSH               (0x06180E9C)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_OFF         (30)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_WID         ( 2)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MIN         (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK2_DqsDccAipCb_HSH         (0x021E0E9C)

#define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_REG                       (0x00000EA0)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_OFF           ( 0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MSK           (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq5DccVal_HSH           (0x06000EA0)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_OFF           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MSK           (0x00000FC0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq6DccVal_HSH           (0x06060EA0)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_OFF           (12)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MSK           (0x0003F000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Dq7DccVal_HSH           (0x060C0EA0)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_OFF           (18)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_WID           ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MSK           (0x00FC0000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MIN           (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_MAX           (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_DEF           (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccVal_HSH           (0x06120EA0)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Spare_OFF               (24)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Spare_WID               ( 6)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MSK               (0x3F000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MIN               (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Spare_MAX               (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Spare_DEF               (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_Spare_HSH               (0x06180EA0)

  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_OFF         (30)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_WID         ( 2)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MSK         (0xC0000000)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MIN         (0)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_MAX         (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_DEF         (0x00000001)
  #define DDRDATA4CH1_CR_DCCDATATRAINVAL1RANK3_DqsDccAipCb_HSH         (0x021E0EA0)

#define DDRDATA4CH1_CR_DCCDATADCCPILUT0_REG                            (0x00000EA4)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_OFF         ( 0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_WID         ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MSK         (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MIN         (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_DEF         (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_0_HSH         (0x06000EA4)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_OFF         ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_WID         ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MSK         (0x00000FC0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MIN         (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_DEF         (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_4_HSH         (0x06060EA4)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_OFF         (12)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_WID         ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MSK         (0x0003F000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MIN         (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_MAX         (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_DEF         (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_8_HSH         (0x060C0EA4)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_OFF        (18)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MSK        (0x00FC0000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_12_HSH        (0x06120EA4)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_OFF        (24)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MSK        (0x3F000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_DccPiForPiCode_16_HSH        (0x06180EA4)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_Spare_OFF                    (30)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_Spare_WID                    ( 2)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_Spare_MSK                    (0xC0000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_Spare_MIN                    (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT0_Spare_HSH                    (0x021E0EA4)

#define DDRDATA4CH1_CR_DCCDATADCCPILUT1_REG                            (0x00000EA8)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_OFF        ( 0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MSK        (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_20_HSH        (0x06000EA8)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_OFF        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MSK        (0x00000FC0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_24_HSH        (0x06060EA8)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_OFF        (12)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MSK        (0x0003F000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_28_HSH        (0x060C0EA8)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_OFF        (18)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MSK        (0x00FC0000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_32_HSH        (0x06120EA8)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_OFF        (24)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MSK        (0x3F000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_DccPiForPiCode_36_HSH        (0x06180EA8)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_Spare_OFF                    (30)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_Spare_WID                    ( 2)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_Spare_MSK                    (0xC0000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_Spare_MIN                    (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT1_Spare_HSH                    (0x021E0EA8)

#define DDRDATA4CH1_CR_DCCDATADCCPILUT2_REG                            (0x00000EAC)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_OFF        ( 0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MSK        (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_40_HSH        (0x06000EAC)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_OFF        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MSK        (0x00000FC0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_44_HSH        (0x06060EAC)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_OFF        (12)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MSK        (0x0003F000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_48_HSH        (0x060C0EAC)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_OFF        (18)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MSK        (0x00FC0000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_52_HSH        (0x06120EAC)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_OFF        (24)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MSK        (0x3F000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_DccPiForPiCode_56_HSH        (0x06180EAC)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_Spare_OFF                    (30)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_Spare_WID                    ( 2)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_Spare_MSK                    (0xC0000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_Spare_MIN                    (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT2_Spare_HSH                    (0x021E0EAC)

#define DDRDATA4CH1_CR_DCCDATADCCPILUT3_REG                            (0x00000EB0)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_OFF        ( 0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MSK        (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_60_HSH        (0x06000EB0)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_OFF        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MSK        (0x00000FC0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_64_HSH        (0x06060EB0)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_OFF        (12)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MSK        (0x0003F000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_68_HSH        (0x060C0EB0)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_OFF        (18)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MSK        (0x00FC0000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_72_HSH        (0x06120EB0)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_OFF        (24)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MSK        (0x3F000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_DccPiForPiCode_76_HSH        (0x06180EB0)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_Spare_OFF                    (30)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_Spare_WID                    ( 2)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_Spare_MSK                    (0xC0000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_Spare_MIN                    (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT3_Spare_HSH                    (0x021E0EB0)

#define DDRDATA4CH1_CR_DCCDATADCCPILUT4_REG                            (0x00000EB4)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_OFF        ( 0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MSK        (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_80_HSH        (0x06000EB4)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_OFF        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MSK        (0x00000FC0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_84_HSH        (0x06060EB4)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_OFF        (12)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MSK        (0x0003F000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_88_HSH        (0x060C0EB4)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_OFF        (18)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MSK        (0x00FC0000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_92_HSH        (0x06120EB4)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_OFF        (24)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_WID        ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MSK        (0x3F000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MIN        (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_DccPiForPiCode_96_HSH        (0x06180EB4)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_Spare_OFF                    (30)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_Spare_WID                    ( 2)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_Spare_MSK                    (0xC0000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_Spare_MIN                    (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_Spare_MAX                    (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT4_Spare_HSH                    (0x021E0EB4)

#define DDRDATA4CH1_CR_DCCDATADCCPILUT5_REG                            (0x00000EB8)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_OFF       ( 0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_WID       ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MSK       (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MIN       (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_MAX       (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_DEF       (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_100_HSH       (0x06000EB8)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_OFF       ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_WID       ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MSK       (0x00000FC0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MIN       (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_MAX       (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_DEF       (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_104_HSH       (0x06060EB8)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_OFF       (12)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_WID       ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MSK       (0x0003F000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MIN       (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_MAX       (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_DEF       (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_108_HSH       (0x060C0EB8)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_OFF       (18)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_WID       ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MSK       (0x00FC0000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MIN       (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_MAX       (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_DEF       (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_112_HSH       (0x06120EB8)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_OFF       (24)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_WID       ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MSK       (0x3F000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MIN       (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_MAX       (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_DEF       (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiForPiCode_116_HSH       (0x06180EB8)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_OFF               (30)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_WID               ( 2)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MSK               (0xC0000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MIN               (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_MAX               (3) // 0x00000003
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_DEF               (0x00000001)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT5_DccPiAipCb_HSH               (0x021E0EB8)

#define DDRDATA4CH1_CR_DCCDATADCCPILUT6_REG                            (0x00000EBC)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_OFF       ( 0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_WID       ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MSK       (0x0000003F)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MIN       (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_MAX       (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_DEF       (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_120_HSH       (0x06000EBC)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_OFF       ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_WID       ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MSK       (0x00000FC0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MIN       (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_MAX       (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_DEF       (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiForPiCode_124_HSH       (0x06060EBC)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_OFF          (12)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_WID          ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MSK          (0x0003F000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MIN          (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_MAX          (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_DEF          (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiStaticCode_HSH          (0x060C0EBC)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_OFF     (18)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_WID     ( 6)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MSK     (0x00FC0000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MIN     (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_MAX     (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_DEF     (0x00000020)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_DccPiStaticCodeGear1_HSH     (0x06120EBC)

  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_Spare_OFF                    (24)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_Spare_WID                    ( 8)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_Spare_MSK                    (0xFF000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_Spare_MIN                    (0)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_Spare_DEF                    (0x00000000)
  #define DDRDATA4CH1_CR_DCCDATADCCPILUT6_Spare_HSH                    (0x08180EBC)

#define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_REG                        (0x00000EC0)

  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_OFF        ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_WID        ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MSK        (0x0000003F)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MIN        (0)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit0_HSH        (0x06000EC0)

  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_OFF        ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_WID        ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MSK        (0x00000FC0)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MIN        (0)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit1_HSH        (0x06060EC0)

  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_OFF        (12)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_WID        ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MSK        (0x0003F000)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MIN        (0)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit2_HSH        (0x060C0EC0)

  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_OFF        (18)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_WID        ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MSK        (0x00FC0000)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MIN        (0)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqTcoCompBit3_HSH        (0x06120EC0)

  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_OFF          (24)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_WID          ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MSK          (0x3F000000)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MIN          (0)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_DEF          (0x00000020)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_DqsNTcoComp_HSH          (0x06180EC0)

  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_Spare_OFF                (30)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_Spare_WID                ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_Spare_MSK                (0xC0000000)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_Spare_MIN                (0)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_Spare_MAX                (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_Spare_DEF                (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL0_Spare_HSH                (0x021E0EC0)

#define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_REG                        (0x00000EC4)

  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_OFF        ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_WID        ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MSK        (0x0000003F)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MIN        (0)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit4_HSH        (0x06000EC4)

  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_OFF        ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_WID        ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MSK        (0x00000FC0)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MIN        (0)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit5_HSH        (0x06060EC4)

  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_OFF        (12)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_WID        ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MSK        (0x0003F000)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MIN        (0)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit6_HSH        (0x060C0EC4)

  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_OFF        (18)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_WID        ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MSK        (0x00FC0000)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MIN        (0)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_MAX        (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_DEF        (0x00000020)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqTcoCompBit7_HSH        (0x06120EC4)

  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_OFF          (24)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_WID          ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MSK          (0x3F000000)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MIN          (0)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_MAX          (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_DEF          (0x00000020)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_DqsPTcoComp_HSH          (0x06180EC4)

  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_Spare_OFF                (30)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_Spare_WID                ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_Spare_MSK                (0xC0000000)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_Spare_MIN                (0)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_Spare_MAX                (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_Spare_DEF                (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATATCOCONTROL1_Spare_HSH                (0x021E0EC4)

#define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_REG                  (0x00000EC8)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_OFF ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_WID ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MSK (0x0000003F)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MIN (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_MAX (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank0_HSH (0x06000EC8)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_OFF ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_WID ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MSK (0x00000FC0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MIN (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_MAX (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit6Rank1_HSH (0x06060EC8)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_OFF (12)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_WID ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MSK (0x0003F000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MIN (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_MAX (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank0_HSH (0x060C0EC8)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_OFF (18)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_WID ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MSK (0x00FC0000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MIN (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_MAX (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DqDfeDlyBit7Rank1_HSH (0x06120EC8)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_OFF (24)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_WID ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MSK (0x03000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MIN (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_MAX (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank0_HSH (0x02180EC8)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_OFF (26)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_WID ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MSK (0x0C000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MIN (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_MAX (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank1_HSH (0x021A0EC8)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_OFF (28)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_WID ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MSK (0x30000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MIN (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_MAX (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank2_HSH (0x021C0EC8)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_OFF (30)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_WID ( 2)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MSK (0xC0000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MIN (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_MAX (3) // 0x00000003
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK01_DfeDlyModeRank3_HSH (0x021E0EC8)

#define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_REG                  (0x00000ECC)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_OFF ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_WID ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MSK (0x0000003F)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MIN (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_MAX (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank2_HSH (0x06000ECC)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_OFF ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_WID ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MSK (0x00000FC0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MIN (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_MAX (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit6Rank3_HSH (0x06060ECC)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_OFF (12)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_WID ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MSK (0x0003F000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MIN (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_MAX (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank2_HSH (0x060C0ECC)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_OFF (18)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_WID ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MSK (0x00FC0000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MIN (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_MAX (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_DEF (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_DqDfeDlyBit7Rank3_HSH (0x06120ECC)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_OFF          (24)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_WID          ( 8)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MSK          (0xFF000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MIN          (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_MAX          (255) // 0x000000FF
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_DEF          (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL1RANK23_Spare_HSH          (0x08180ECC)

#define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_REG                   (0x00000ED0)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit1_HSH    (0x06000ED0)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit2_HSH    (0x06060ED0)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit3_HSH    (0x060C0ED0)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit4_HSH    (0x06120ED0)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeDlyBit5_HSH    (0x06180ED0)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_OFF         (30)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_WID         ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MIN         (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqDfeEn_HSH         (0x011E0ED0)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_OFF        (31)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_WID        ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MIN        (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK0_DqsDfeEn_HSH        (0x011F0ED0)

#define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_REG                   (0x00000ED4)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit1_HSH    (0x06000ED4)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit2_HSH    (0x06060ED4)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit3_HSH    (0x060C0ED4)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit4_HSH    (0x06120ED4)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeDlyBit5_HSH    (0x06180ED4)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_OFF         (30)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_WID         ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MIN         (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqDfeEn_HSH         (0x011E0ED4)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_OFF        (31)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_WID        ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MIN        (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK1_DqsDfeEn_HSH        (0x011F0ED4)

#define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_REG                   (0x00000ED8)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit1_HSH    (0x06000ED8)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit2_HSH    (0x06060ED8)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit3_HSH    (0x060C0ED8)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit4_HSH    (0x06120ED8)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeDlyBit5_HSH    (0x06180ED8)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_OFF         (30)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_WID         ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MIN         (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqDfeEn_HSH         (0x011E0ED8)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_OFF        (31)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_WID        ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MIN        (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK2_DqsDfeEn_HSH        (0x011F0ED8)

#define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_REG                   (0x00000EDC)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_OFF    ( 0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MSK    (0x0000003F)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit1_HSH    (0x06000EDC)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_OFF    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MSK    (0x00000FC0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit2_HSH    (0x06060EDC)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_OFF    (12)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MSK    (0x0003F000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit3_HSH    (0x060C0EDC)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_OFF    (18)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MSK    (0x00FC0000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit4_HSH    (0x06120EDC)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_OFF    (24)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_WID    ( 6)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MSK    (0x3F000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MIN    (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_MAX    (63) // 0x0000003F
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_DEF    (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeDlyBit5_HSH    (0x06180EDC)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_OFF         (30)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_WID         ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MSK         (0x40000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MIN         (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_MAX         (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_DEF         (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqDfeEn_HSH         (0x011E0EDC)

  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_OFF        (31)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_WID        ( 1)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MSK        (0x80000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MIN        (0)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_MAX        (1) // 0x00000001
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_DEF        (0x00000000)
  #define DDRDATA4CH1_CR_DDRCRDATADFECONTROL0RANK3_DqsDfeEn_HSH        (0x011F0EDC)

#define DDRDATA5CH0_CR_RXCONTROL0RANK0_REG                             (0x00000F00)

  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_WID                 (11)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MIN                 (0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxRcvEnPi_HSH                 (0x0B000F00)

  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxDqsPPi_OFF                  (11)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxDqsPPi_WID                  ( 7)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MIN                  (0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxDqsPPi_HSH                  (0x070B0F00)

  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxEq_OFF                      (18)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxEq_WID                      ( 7)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxEq_MIN                      (0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxEq_DEF                      (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxEq_HSH                      (0x07120F00)

  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxDqsNPi_OFF                  (25)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxDqsNPi_WID                  ( 7)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MIN                  (0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK0_RxDqsNPi_HSH                  (0x07190F00)

#define DDRDATA5CH0_CR_RXCONTROL0RANK1_REG                             (0x00000F04)

  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_WID                 (11)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MIN                 (0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxRcvEnPi_HSH                 (0x0B000F04)

  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxDqsPPi_OFF                  (11)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxDqsPPi_WID                  ( 7)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MIN                  (0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxDqsPPi_HSH                  (0x070B0F04)

  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxEq_OFF                      (18)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxEq_WID                      ( 7)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxEq_MIN                      (0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxEq_DEF                      (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxEq_HSH                      (0x07120F04)

  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxDqsNPi_OFF                  (25)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxDqsNPi_WID                  ( 7)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MIN                  (0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK1_RxDqsNPi_HSH                  (0x07190F04)

#define DDRDATA5CH0_CR_RXCONTROL0RANK2_REG                             (0x00000F08)

  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_WID                 (11)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MIN                 (0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxRcvEnPi_HSH                 (0x0B000F08)

  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxDqsPPi_OFF                  (11)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxDqsPPi_WID                  ( 7)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MIN                  (0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxDqsPPi_HSH                  (0x070B0F08)

  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxEq_OFF                      (18)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxEq_WID                      ( 7)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxEq_MIN                      (0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxEq_DEF                      (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxEq_HSH                      (0x07120F08)

  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxDqsNPi_OFF                  (25)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxDqsNPi_WID                  ( 7)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MIN                  (0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK2_RxDqsNPi_HSH                  (0x07190F08)

#define DDRDATA5CH0_CR_RXCONTROL0RANK3_REG                             (0x00000F0C)

  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_OFF                 ( 0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_WID                 (11)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MSK                 (0x000007FF)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MIN                 (0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_MAX                 (2047) // 0x000007FF
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_DEF                 (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxRcvEnPi_HSH                 (0x0B000F0C)

  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxDqsPPi_OFF                  (11)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxDqsPPi_WID                  ( 7)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MSK                  (0x0003F800)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MIN                  (0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxDqsPPi_MAX                  (127) // 0x0000007F
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxDqsPPi_DEF                  (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxDqsPPi_HSH                  (0x070B0F0C)

  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxEq_OFF                      (18)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxEq_WID                      ( 7)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxEq_MSK                      (0x01FC0000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxEq_MIN                      (0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxEq_MAX                      (127) // 0x0000007F
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxEq_DEF                      (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxEq_HSH                      (0x07120F0C)

  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxDqsNPi_OFF                  (25)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxDqsNPi_WID                  ( 7)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MSK                  (0xFE000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MIN                  (0)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxDqsNPi_MAX                  (127) // 0x0000007F
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxDqsNPi_DEF                  (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL0RANK3_RxDqsNPi_HSH                  (0x07190F0C)

#define DDRDATA5CH0_CR_RXCONTROL1RANK0_REG                             (0x00000F10)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane3PerBitDeskew_HSH         (0x06000F10)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane2PerBitDeskew_HSH         (0x06060F10)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane1PerBitDeskew_HSH         (0x060C0F10)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_Lane0PerBitDeskew_HSH         (0x06120F10)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_OFF               (24)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MIN               (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_DqsDfeCoeff_HSH               (0x02180F10)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK0_DqDfeDlyBit0_HSH              (0x061A0F10)

#define DDRDATA5CH0_CR_RXCONTROL1RANK1_REG                             (0x00000F14)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane3PerBitDeskew_HSH         (0x06000F14)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane2PerBitDeskew_HSH         (0x06060F14)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane1PerBitDeskew_HSH         (0x060C0F14)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_Lane0PerBitDeskew_HSH         (0x06120F14)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_OFF               (24)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MIN               (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_DqsDfeCoeff_HSH               (0x02180F14)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK1_DqDfeDlyBit0_HSH              (0x061A0F14)

#define DDRDATA5CH0_CR_RXCONTROL1RANK2_REG                             (0x00000F18)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane3PerBitDeskew_HSH         (0x06000F18)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane2PerBitDeskew_HSH         (0x06060F18)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane1PerBitDeskew_HSH         (0x060C0F18)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_Lane0PerBitDeskew_HSH         (0x06120F18)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_OFF               (24)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MIN               (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_DqsDfeCoeff_HSH               (0x02180F18)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK2_DqDfeDlyBit0_HSH              (0x061A0F18)

#define DDRDATA5CH0_CR_RXCONTROL1RANK3_REG                             (0x00000F1C)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane3PerBitDeskew_HSH         (0x06000F1C)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane2PerBitDeskew_HSH         (0x06060F1C)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_OFF         (12)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MSK         (0x0003F000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane1PerBitDeskew_HSH         (0x060C0F1C)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_OFF         (18)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MSK         (0x00FC0000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_Lane0PerBitDeskew_HSH         (0x06120F1C)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_OFF               (24)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_WID               ( 2)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MSK               (0x03000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MIN               (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_MAX               (3) // 0x00000003
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_DEF               (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_DqsDfeCoeff_HSH               (0x02180F1C)

  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_OFF              (26)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_WID              ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MSK              (0xFC000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MIN              (0)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_MAX              (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_DEF              (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL1RANK3_DqDfeDlyBit0_HSH              (0x061A0F1C)

#define DDRDATA5CH0_CR_TXTRAINRANK0_REG                                (0x00000F20)

  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_OFF                    ( 0)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_WID                    (10)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_MIN                    (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqDelay_HSH                    (0x0A000F20)

  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_OFF                   (10)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_WID                   (10)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_MIN                   (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxDqsDelay_HSH                   (0x0A0A0F20)

  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_OFF               (20)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_WID               ( 6)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_MIN               (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_DEF               (0x00000030)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxEqualization_HSH               (0x06140F20)

  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxRankMuxDelay_OFF               (26)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxRankMuxDelay_WID               ( 4)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MSK               (0x3C000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MIN               (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxRankMuxDelay_MAX               (15) // 0x0000000F
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxRankMuxDelay_DEF               (0x00000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_TxRankMuxDelay_HSH               (0x041A0F20)

  #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_OFF                       (30)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_WID                       ( 2)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_MSK                       (0xC0000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_MIN                       (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_MAX                       (3) // 0x00000003
  #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_DEF                       (0x00000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK0_Spare1_HSH                       (0x021E0F20)

#define DDRDATA5CH0_CR_TXTRAINRANK1_REG                                (0x00000F24)

  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_OFF                    ( 0)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_WID                    (10)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_MIN                    (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqDelay_HSH                    (0x0A000F24)

  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_OFF                   (10)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_WID                   (10)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_MIN                   (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxDqsDelay_HSH                   (0x0A0A0F24)

  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_OFF               (20)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_WID               ( 6)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_MIN               (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_DEF               (0x00000030)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxEqualization_HSH               (0x06140F24)

  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_OFF (26)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MSK (0x0C000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_TxRankMuxDelay_2nd_stage_offset_HSH (0x021A0F24)

  #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_OFF                       (28)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_WID                       ( 4)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_MSK                       (0xF0000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_MIN                       (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_MAX                       (15) // 0x0000000F
  #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_DEF                       (0x00000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK1_Spare1_HSH                       (0x041C0F24)

#define DDRDATA5CH0_CR_TXTRAINRANK2_REG                                (0x00000F28)

  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_OFF                    ( 0)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_WID                    (10)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_MIN                    (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqDelay_HSH                    (0x0A000F28)

  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_OFF                   (10)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_WID                   (10)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_MIN                   (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxDqsDelay_HSH                   (0x0A0A0F28)

  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_OFF               (20)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_WID               ( 6)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_MIN               (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_DEF               (0x00000030)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_TxEqualization_HSH               (0x06140F28)

  #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_OFF                       (26)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_WID                       ( 6)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_MSK                       (0xFC000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_MIN                       (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_DEF                       (0x00000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK2_Spare1_HSH                       (0x061A0F28)

#define DDRDATA5CH0_CR_TXTRAINRANK3_REG                                (0x00000F2C)

  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_OFF                    ( 0)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_WID                    (10)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_MSK                    (0x000003FF)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_MIN                    (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_MAX                    (1023) // 0x000003FF
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqDelay_HSH                    (0x0A000F2C)

  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_OFF                   (10)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_WID                   (10)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_MSK                   (0x000FFC00)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_MIN                   (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_MAX                   (1023) // 0x000003FF
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_DEF                   (0x00000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxDqsDelay_HSH                   (0x0A0A0F2C)

  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_OFF               (20)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_WID               ( 6)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_MSK               (0x03F00000)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_MIN               (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_MAX               (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_DEF               (0x00000030)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_TxEqualization_HSH               (0x06140F2C)

  #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_OFF                       (26)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_WID                       ( 6)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_MSK                       (0xFC000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_MIN                       (0)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_MAX                       (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_DEF                       (0x00000000)
  #define DDRDATA5CH0_CR_TXTRAINRANK3_Spare1_HSH                       (0x061A0F2C)

#define DDRDATA5CH0_CR_TXPERBITLOWRANK0_REG                            (0x00000F30)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane0_OFF                    ( 0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane0_WID                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane0_MSK                    (0x0000003F)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane0_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane0_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane0_HSH                    (0x06000F30)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane1_OFF                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane1_WID                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane1_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane1_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane1_HSH                    (0x06060F30)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane2_OFF                    (12)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane2_WID                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane2_MSK                    (0x0003F000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane2_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane2_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane2_HSH                    (0x060C0F30)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane3_OFF                    (18)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane3_WID                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane3_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane3_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Lane3_HSH                    (0x06120F30)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Spare_OFF                    (24)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Spare_WID                    ( 8)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Spare_MSK                    (0xFF000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Spare_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK0_Spare_HSH                    (0x08180F30)

#define DDRDATA5CH0_CR_TXPERBITLOWRANK1_REG                            (0x00000F34)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane0_OFF                    ( 0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane0_WID                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane0_MSK                    (0x0000003F)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane0_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane0_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane0_HSH                    (0x06000F34)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane1_OFF                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane1_WID                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane1_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane1_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane1_HSH                    (0x06060F34)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane2_OFF                    (12)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane2_WID                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane2_MSK                    (0x0003F000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane2_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane2_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane2_HSH                    (0x060C0F34)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane3_OFF                    (18)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane3_WID                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane3_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane3_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Lane3_HSH                    (0x06120F34)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Spare_OFF                    (24)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Spare_WID                    ( 8)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Spare_MSK                    (0xFF000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Spare_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK1_Spare_HSH                    (0x08180F34)

#define DDRDATA5CH0_CR_TXPERBITLOWRANK2_REG                            (0x00000F38)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane0_OFF                    ( 0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane0_WID                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane0_MSK                    (0x0000003F)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane0_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane0_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane0_HSH                    (0x06000F38)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane1_OFF                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane1_WID                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane1_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane1_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane1_HSH                    (0x06060F38)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane2_OFF                    (12)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane2_WID                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane2_MSK                    (0x0003F000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane2_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane2_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane2_HSH                    (0x060C0F38)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane3_OFF                    (18)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane3_WID                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane3_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane3_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Lane3_HSH                    (0x06120F38)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Spare_OFF                    (24)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Spare_WID                    ( 8)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Spare_MSK                    (0xFF000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Spare_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK2_Spare_HSH                    (0x08180F38)

#define DDRDATA5CH0_CR_TXPERBITLOWRANK3_REG                            (0x00000F3C)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane0_OFF                    ( 0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane0_WID                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane0_MSK                    (0x0000003F)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane0_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane0_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane0_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane0_HSH                    (0x06000F3C)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane1_OFF                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane1_WID                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane1_MSK                    (0x00000FC0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane1_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane1_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane1_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane1_HSH                    (0x06060F3C)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane2_OFF                    (12)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane2_WID                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane2_MSK                    (0x0003F000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane2_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane2_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane2_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane2_HSH                    (0x060C0F3C)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane3_OFF                    (18)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane3_WID                    ( 6)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane3_MSK                    (0x00FC0000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane3_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane3_MAX                    (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane3_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Lane3_HSH                    (0x06120F3C)

  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Spare_OFF                    (24)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Spare_WID                    ( 8)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Spare_MSK                    (0xFF000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Spare_MIN                    (0)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Spare_MAX                    (255) // 0x000000FF
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Spare_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITLOWRANK3_Spare_HSH                    (0x08180F3C)

#define DDRDATA5CH0_CR_RCOMPDATA0_REG                                  (0x00000F40)

  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_OFF                     ( 0)
  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_WID                     ( 6)
  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_MSK                     (0x0000003F)
  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_MIN                     (0)
  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvUp_HSH                     (0x06000F40)

  #define DDRDATA5CH0_CR_RCOMPDATA0_Rsvd_OFF                           ( 6)
  #define DDRDATA5CH0_CR_RCOMPDATA0_Rsvd_WID                           ( 8)
  #define DDRDATA5CH0_CR_RCOMPDATA0_Rsvd_MSK                           (0x00003FC0)
  #define DDRDATA5CH0_CR_RCOMPDATA0_Rsvd_MIN                           (0)
  #define DDRDATA5CH0_CR_RCOMPDATA0_Rsvd_MAX                           (255) // 0x000000FF
  #define DDRDATA5CH0_CR_RCOMPDATA0_Rsvd_DEF                           (0x00000000)
  #define DDRDATA5CH0_CR_RCOMPDATA0_Rsvd_HSH                           (0x08060F40)

  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_OFF                   (14)
  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_WID                   ( 6)
  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_MSK                   (0x000FC000)
  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_MIN                   (0)
  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_MAX                   (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_DEF                   (0x00000000)
  #define DDRDATA5CH0_CR_RCOMPDATA0_RcompDrvDown_HSH                   (0x060E0F40)

  #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_OFF                   (20)
  #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_WID                   ( 5)
  #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_MSK                   (0x01F00000)
  #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_MIN                   (0)
  #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_MAX                   (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_DEF                   (0x00000000)
  #define DDRDATA5CH0_CR_RCOMPDATA0_SlewRateComp_HSH                   (0x05140F40)

  #define DDRDATA5CH0_CR_RCOMPDATA0_Spare_OFF                          (25)
  #define DDRDATA5CH0_CR_RCOMPDATA0_Spare_WID                          ( 7)
  #define DDRDATA5CH0_CR_RCOMPDATA0_Spare_MSK                          (0xFE000000)
  #define DDRDATA5CH0_CR_RCOMPDATA0_Spare_MIN                          (0)
  #define DDRDATA5CH0_CR_RCOMPDATA0_Spare_MAX                          (127) // 0x0000007F
  #define DDRDATA5CH0_CR_RCOMPDATA0_Spare_DEF                          (0x00000000)
  #define DDRDATA5CH0_CR_RCOMPDATA0_Spare_HSH                          (0x07190F40)

#define DDRDATA5CH0_CR_RCOMPDATA1_REG                                  (0x00000F44)

  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_OFF                     ( 0)
  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_WID                     ( 6)
  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_MSK                     (0x0000003F)
  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_MIN                     (0)
  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtUp_HSH                     (0x06000F44)

  #define DDRDATA5CH0_CR_RCOMPDATA1_spare_OFF                          ( 6)
  #define DDRDATA5CH0_CR_RCOMPDATA1_spare_WID                          (20)
  #define DDRDATA5CH0_CR_RCOMPDATA1_spare_MSK                          (0x03FFFFC0)
  #define DDRDATA5CH0_CR_RCOMPDATA1_spare_MIN                          (0)
  #define DDRDATA5CH0_CR_RCOMPDATA1_spare_MAX                          (1048575) // 0x000FFFFF
  #define DDRDATA5CH0_CR_RCOMPDATA1_spare_DEF                          (0x00000000)
  #define DDRDATA5CH0_CR_RCOMPDATA1_spare_HSH                          (0x14060F44)

  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_OFF                   (26)
  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_WID                   ( 6)
  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_MSK                   (0xFC000000)
  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_MIN                   (0)
  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_MAX                   (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_DEF                   (0x00000000)
  #define DDRDATA5CH0_CR_RCOMPDATA1_RcompOdtDown_HSH                   (0x061A0F44)

#define DDRDATA5CH0_CR_DDRCRDATACONTROL8_REG                           (0x00000F48)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_OFF         ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_WID         ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MSK         (0x00000003)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MIN         (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_MAX         (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank0_HSH         (0x02000F48)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_OFF         ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_WID         ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MSK         (0x0000000C)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MIN         (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_MAX         (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank1_HSH         (0x02020F48)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_OFF         ( 4)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_WID         ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MSK         (0x00000030)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MIN         (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_MAX         (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank2_HSH         (0x02040F48)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_OFF         ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_WID         ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MSK         (0x000000C0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MIN         (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_MAX         (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_DqDfeCoeffRank3_HSH         (0x02060F48)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_OFF   ( 8)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_WID   ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MSK   (0x00000100)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MIN   (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_MAX   (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_DEF   (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_en_rcvenpre_zero_fill_HSH   (0x01080F48)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_spare_OFF                   ( 9)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_spare_WID                   (23)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_spare_MSK                   (0xFFFFFE00)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_spare_MIN                   (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_spare_DEF                   (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL8_spare_HSH                   (0x17090F48)

#define DDRDATA5CH0_CR_RCOMPDATA2_REG                                  (0x00000F4C)

  #define DDRDATA5CH0_CR_RCOMPDATA2_PanicVttUp_OFF                     ( 0)
  #define DDRDATA5CH0_CR_RCOMPDATA2_PanicVttUp_WID                     ( 8)
  #define DDRDATA5CH0_CR_RCOMPDATA2_PanicVttUp_MSK                     (0x000000FF)
  #define DDRDATA5CH0_CR_RCOMPDATA2_PanicVttUp_MIN                     (0)
  #define DDRDATA5CH0_CR_RCOMPDATA2_PanicVttUp_MAX                     (255) // 0x000000FF
  #define DDRDATA5CH0_CR_RCOMPDATA2_PanicVttUp_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_RCOMPDATA2_PanicVttUp_HSH                     (0x08000F4C)

  #define DDRDATA5CH0_CR_RCOMPDATA2_PanicVttDn_OFF                     ( 8)
  #define DDRDATA5CH0_CR_RCOMPDATA2_PanicVttDn_WID                     ( 8)
  #define DDRDATA5CH0_CR_RCOMPDATA2_PanicVttDn_MSK                     (0x0000FF00)
  #define DDRDATA5CH0_CR_RCOMPDATA2_PanicVttDn_MIN                     (0)
  #define DDRDATA5CH0_CR_RCOMPDATA2_PanicVttDn_MAX                     (255) // 0x000000FF
  #define DDRDATA5CH0_CR_RCOMPDATA2_PanicVttDn_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_RCOMPDATA2_PanicVttDn_HSH                     (0x08080F4C)

  #define DDRDATA5CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_OFF               (16)
  #define DDRDATA5CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_WID               ( 6)
  #define DDRDATA5CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MSK               (0x003F0000)
  #define DDRDATA5CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MIN               (0)
  #define DDRDATA5CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_MAX               (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_DEF               (0x00000000)
  #define DDRDATA5CH0_CR_RCOMPDATA2_RcompCmdDn200ohm_HSH               (0x06100F4C)

  #define DDRDATA5CH0_CR_RCOMPDATA2_Spare_OFF                          (22)
  #define DDRDATA5CH0_CR_RCOMPDATA2_Spare_WID                          (10)
  #define DDRDATA5CH0_CR_RCOMPDATA2_Spare_MSK                          (0xFFC00000)
  #define DDRDATA5CH0_CR_RCOMPDATA2_Spare_MIN                          (0)
  #define DDRDATA5CH0_CR_RCOMPDATA2_Spare_MAX                          (1023) // 0x000003FF
  #define DDRDATA5CH0_CR_RCOMPDATA2_Spare_DEF                          (0x00000000)
  #define DDRDATA5CH0_CR_RCOMPDATA2_Spare_HSH                          (0x0A160F4C)

#define DDRDATA5CH0_CR_RXCONTROL2RANK0_REG                             (0x00000F50)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane4PerBitDeskew_HSH         (0x06000F50)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane5PerBitDeskew_HSH         (0x06060F50)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane0RxOffsetVDq_HSH          (0x050C0F50)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane1RxOffsetVDq_HSH          (0x05110F50)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane2RxOffsetVDq_HSH          (0x05160F50)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK0_Lane3RxOffsetVDq_HSH          (0x051B0F50)

#define DDRDATA5CH0_CR_RXCONTROL2RANK1_REG                             (0x00000F54)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane4PerBitDeskew_HSH         (0x06000F54)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane5PerBitDeskew_HSH         (0x06060F54)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane0RxOffsetVDq_HSH          (0x050C0F54)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane1RxOffsetVDq_HSH          (0x05110F54)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane2RxOffsetVDq_HSH          (0x05160F54)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK1_Lane3RxOffsetVDq_HSH          (0x051B0F54)

#define DDRDATA5CH0_CR_RXCONTROL2RANK2_REG                             (0x00000F58)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane4PerBitDeskew_HSH         (0x06000F58)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane5PerBitDeskew_HSH         (0x06060F58)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane0RxOffsetVDq_HSH          (0x050C0F58)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane1RxOffsetVDq_HSH          (0x05110F58)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane2RxOffsetVDq_HSH          (0x05160F58)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK2_Lane3RxOffsetVDq_HSH          (0x051B0F58)

#define DDRDATA5CH0_CR_RXCONTROL2RANK3_REG                             (0x00000F5C)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane4PerBitDeskew_HSH         (0x06000F5C)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane5PerBitDeskew_HSH         (0x06060F5C)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_OFF          (12)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane0RxOffsetVDq_HSH          (0x050C0F5C)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_OFF          (17)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane1RxOffsetVDq_HSH          (0x05110F5C)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_OFF          (22)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane2RxOffsetVDq_HSH          (0x05160F5C)

  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_OFF          (27)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL2RANK3_Lane3RxOffsetVDq_HSH          (0x051B0F5C)

#define DDRDATA5CH0_CR_DATATRAINFEEDBACK_REG                           (0x00000F60)

  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_OFF       ( 0)
  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_WID       ( 9)
  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MSK       (0x000001FF)
  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MIN       (0)
  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_MAX       (511) // 0x000001FF
  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_DEF       (0x00000000)
  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_DataTrainFeedback_HSH       (0x09000F60)

  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_OFF                   ( 9)
  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_WID                   (23)
  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_MSK                   (0xFFFFFE00)
  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_MIN                   (0)
  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_MAX                   (8388607) // 0x007FFFFF
  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_DEF                   (0x00000000)
  #define DDRDATA5CH0_CR_DATATRAINFEEDBACK_Spare_HSH                   (0x17090F60)

#define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_REG                         (0x00000F68)

  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_OFF     ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_WID     ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MSK     (0x0000003F)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MIN     (-32)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_MAX     (31) // 0x0000001F
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_DEF     (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvUpCompOffset_HSH     (0x86000F68)

  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_OFF   ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_WID   ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MSK   (0x00000FC0)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MIN   (-32)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_MAX   (31) // 0x0000001F
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_DEF   (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqDrvDownCompOffset_HSH   (0x86060F68)

  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_OFF     (12)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_WID     ( 5)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MSK     (0x0001F000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MIN     (-16)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_MAX     (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_DEF     (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtUpCompOffset_HSH     (0x850C0F68)

  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_OFF   (17)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_WID   ( 5)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MSK   (0x003E0000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MIN   (-16)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_MAX   (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_DEF   (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqOdtDownCompOffset_HSH   (0x85110F68)

  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_Spare_OFF                 (22)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_Spare_WID                 ( 5)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MSK                 (0x07C00000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MIN                 (0)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_Spare_MAX                 (31) // 0x0000001F
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_Spare_DEF                 (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_Spare_HSH                 (0x05160F68)

  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_OFF  (27)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_WID  ( 5)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MSK  (0xF8000000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MIN  (-16)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_MAX  (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_DEF  (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETCOMP_DqSlewRateCompOffset_HSH  (0x851B0F68)

#define DDRDATA5CH0_CR_DDRCRDATACONTROL1_REG                           (0x00000F6C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_OFF                   ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_WID                   ( 4)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_MSK                   (0x0000000F)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_MIN                   (-8)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_MAX                   (7) // 0x00000007
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_DEF                   (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RefPi_HSH                   (0x84000F6C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_OFF                 ( 4)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_WID                 ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_MSK                 (0x00000030)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_MIN                 (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_MAX                 (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_DEF                 (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllMask_HSH                 (0x02040F6C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_OFF             ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_WID             ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MSK             (0x00000040)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MIN             (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_MAX             (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_DEF             (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_DllWeakLock_HSH             (0x01060F6C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_OFF      ( 7)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_WID      ( 3)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MSK      (0x00000380)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MIN      (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_MAX      (7) // 0x00000007
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_DEF      (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SdllSegmentDisable_HSH      (0x03070F6C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_OFF               (10)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_WID               ( 4)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MSK               (0x00003C00)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MIN               (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_MAX               (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_DEF               (0x00000008)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_RxBiasCtl_HSH               (0x040A0F6C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_OFF                (14)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_WID                ( 5)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_MSK                (0x0007C000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_MIN                (-16)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_MAX                (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_DEF                (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDelay_HSH                (0x850E0F6C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_OFF             (19)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_WID             ( 3)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_MSK             (0x00380000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_MIN             (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_MAX             (7) // 0x00000007
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_DEF             (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_OdtDuration_HSH             (0x03130F6C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_OFF           (22)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_WID           ( 5)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MSK           (0x07C00000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MIN           (-16)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_MAX           (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_DEF           (0x0000001C)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDelay_HSH           (0x85160F6C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_OFF        (27)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_WID        ( 3)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MSK        (0x38000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MIN        (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_MAX        (7) // 0x00000007
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_DEF        (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_SenseAmpDuration_HSH        (0x031B0F6C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_OFF                (30)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_WID                ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MSK                (0xC0000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MIN                (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_MAX                (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_DEF                (0x00000001)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL1_CBEnAmp2_HSH                (0x021E0F6C)

#define DDRDATA5CH0_CR_DDRCRDATACONTROL2_REG                           (0x00000F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_OFF            ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_WID            ( 5)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MSK            (0x0000001F)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MIN            (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_MAX            (31) // 0x0000001F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_DEF            (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxStaggerCtl_HSH            (0x05000F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_OFF             ( 5)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_WID             ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MSK             (0x00000020)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MIN             (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_MAX             (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_DEF             (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceBiasOn_HSH             (0x01050F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_OFF               ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_WID               ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MSK               (0x00000040)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MIN               (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_MAX               (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_DEF               (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_ForceRxOn_HSH               (0x01060F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_OFF     ( 7)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_WID     ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MSK     (0x00000080)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MIN     (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_MAX     (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_DEF     (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_DisableDqsOdtStatic_HSH     (0x01070F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_OFF          ( 8)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_WID          ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MSK          (0x00000100)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MIN          (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_MAX          (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_LpDdrLongOdtEn_HSH          (0x01080F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_OFF          ( 9)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_WID          ( 4)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MSK          (0x00001E00)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MIN          (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_MAX          (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxRankMuxDelay_HSH          (0x04090F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_OFF             (13)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_WID             ( 5)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MSK             (0x0003E000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MIN             (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_MAX             (31) // 0x0000001F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_DEF             (0x00000011)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxClkStgNum_HSH             (0x050D0F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_OFF             (18)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_WID             ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MSK             (0x00040000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MIN             (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_MAX             (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_DEF             (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_WlLongDelEn_HSH             (0x01120F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_OFF         (19)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_WID         ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MSK         (0x00080000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MIN         (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_MAX         (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_DEF         (0x00000001)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnableVrefPwrDn_HSH         (0x01130F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_OFF                (20)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_WID                ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MSK                (0x00100000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MIN                (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_MAX                (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_DEF                (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Ddr4Mode_HSH                (0x01140F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_OFF               (21)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_WID               ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MSK               (0x00200000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MIN               (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_MAX               (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_DEF               (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnVddqOdt_HSH               (0x01150F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnVttOdt_OFF                (22)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnVttOdt_WID                ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MSK                (0x00400000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MIN                (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnVttOdt_MAX                (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnVttOdt_DEF                (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnVttOdt_HSH                (0x01160F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_OFF            (23)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_WID            ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MSK            (0x00800000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MIN            (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_MAX            (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_DEF            (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_EnConstZEqTx_HSH            (0x01170F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_TxEqDis_OFF                 (24)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_TxEqDis_WID                 ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_TxEqDis_MSK                 (0x01000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_TxEqDis_MIN                 (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_TxEqDis_MAX                 (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_TxEqDis_DEF                 (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_TxEqDis_HSH                 (0x01180F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_OFF           (25)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_WID           ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MSK           (0x02000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MIN           (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_MAX           (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_DEF           (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxVrefProgMFC_HSH           (0x01190F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Cben_OFF                    (26)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Cben_WID                    ( 3)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Cben_MSK                    (0x1C000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Cben_MIN                    (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Cben_MAX                    (7) // 0x00000007
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Cben_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_Cben_HSH                    (0x031A0F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_OFF         (29)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_WID         ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MSK         (0x20000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MIN         (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_TxDeskewDisable_HSH         (0x011D0F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_OFF         (30)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_WID         ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MSK         (0x40000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MIN         (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_MAX         (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_RxDeskewDisable_HSH         (0x011E0F70)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_OFF         (31)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_WID         ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MSK         (0x80000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MIN         (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_MAX         (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL2_DqSlewDlyByPass_HSH         (0x011F0F70)

#define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_REG                        (0x00000F7C)

  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_OFF          ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_WID          ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MSK          (0x0000003F)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MIN          (-32)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RcvEnOffset_HSH          (0x86000F7C)

  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_OFF          ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_WID          ( 7)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MSK          (0x00001FC0)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MIN          (-64)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_MAX          (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_RxDqsOffset_HSH          (0x87060F7C)

  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_OFF           (13)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_WID           ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MSK           (0x0007E000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MIN           (-32)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_MAX           (31) // 0x0000001F
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_DEF           (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqOffset_HSH           (0x860D0F7C)

  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_OFF          (19)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_WID          ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MSK          (0x01F80000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MIN          (-32)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_TxDqsOffset_HSH          (0x86130F7C)

  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_OFF           (25)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_WID           ( 7)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MSK           (0xFE000000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MIN           (-64)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_MAX           (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_DEF           (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATAOFFSETTRAIN_VrefOffset_HSH           (0x87190F7C)

#define DDRDATA5CH0_CR_DDRCRDATACONTROL0_REG                           (0x00000F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_OFF          ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_WID          ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MSK          (0x00000001)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MIN          (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxTrainingMode_HSH          (0x01000F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_OFF          ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_WID          ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MSK          (0x00000002)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MIN          (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_WLTrainingMode_HSH          (0x01010F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_OFF          ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_WID          ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MSK          (0x00000004)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MIN          (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_MAX          (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RLTrainingMode_HSH          (0x01020F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_OFF    ( 3)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_WID    ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MSK    (0x00000008)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_MAX    (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_SenseampTrainingMode_HSH    (0x01030F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_OFF                    ( 4)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_WID                    ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_MSK                    (0x00000010)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_MIN                    (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_MAX                    (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxOn_HSH                    (0x01040F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_OFF              ( 5)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_WID              ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MSK              (0x00000020)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MIN              (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_MAX              (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_DEF              (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LPDDR_Mode_HSH              (0x01050F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_OFF                  ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_WID                  ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_MSK                  (0x00000040)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_MIN                  (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_DEF                  (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxPiOn_HSH                  (0x01060F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_OFF                  ( 7)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_WID                  ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_MSK                  (0x00000080)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_MIN                  (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_MAX                  (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_DEF                  (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxPiOn_HSH                  (0x01070F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_OFF        ( 8)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_WID        ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MSK        (0x00000100)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MIN        (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_DEF        (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_InternalClocksOn_HSH        (0x01080F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_OFF        ( 9)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_WID        ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MSK        (0x00000200)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MIN        (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_MAX        (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_DEF        (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RepeaterClocksOn_HSH        (0x01090F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_OFF               (10)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_WID               ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_MSK               (0x00000400)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_MIN               (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_MAX               (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_DEF               (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_TxDisable_HSH               (0x010A0F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_OFF               (11)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_WID               ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_MSK               (0x00000800)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_MIN               (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_MAX               (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_DEF               (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDisable_HSH               (0x010B0F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_Spare2_OFF                  (12)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_Spare2_WID                  ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_Spare2_MSK                  (0x00001000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_Spare2_MIN                  (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_Spare2_MAX                  (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_Spare2_DEF                  (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_Spare2_HSH                  (0x010C0F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_OFF               (13)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_WID               ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MSK               (0x00006000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MIN               (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_MAX               (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_DEF               (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxDqsCtle_HSH               (0x020D0F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_OFF           (15)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_WID           ( 4)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MSK           (0x00078000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MIN           (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_MAX           (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_DEF           (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_RxReadPointer_HSH           (0x040F0F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_OFF      (19)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_WID      ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MSK      (0x00180000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MIN      (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_MAX      (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_DEF      (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_xover_mindelay_ctl_HSH      (0x02130F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_OFF           (21)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_WID           ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MSK           (0x00200000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MIN           (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_MAX           (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_DEF           (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DQDQSLowsupEn_HSH           (0x01150F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_OFF             (22)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_WID             ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MSK             (0x00400000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MIN             (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_MAX             (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_DEF             (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DqTcoBypass_HSH             (0x01160F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_viewQclkDis_OFF             (23)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_viewQclkDis_WID             ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MSK             (0x00800000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MIN             (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_viewQclkDis_MAX             (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_viewQclkDis_DEF             (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_viewQclkDis_HSH             (0x01170F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_OFF              (24)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_WID              ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MSK              (0x01000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MIN              (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_MAX              (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_DEF              (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_ForceOdtOn_HSH              (0x01180F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_OFF              (25)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_WID              ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MSK              (0x02000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MIN              (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_MAX              (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_DEF              (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampOff_HSH              (0x01190F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_OFF        (26)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_WID        ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MSK        (0x04000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MIN        (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_MAX        (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_DEF        (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DisableOdtStatic_HSH        (0x011A0F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_OFF         (27)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_WID         ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MSK         (0x08000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MIN         (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_MAX         (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_DdrCRForceODTOn_HSH         (0x011B0F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_spare_OFF                   (28)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_spare_WID                   ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_spare_MSK                   (0x10000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_spare_MIN                   (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_spare_MAX                   (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_spare_DEF                   (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_spare_HSH                   (0x011C0F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_OFF              (29)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_WID              ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MSK              (0x20000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MIN              (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_MAX              (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_DEF              (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_LongOdtR2W_HSH              (0x011D0F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_OFF         (30)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_WID         ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MSK         (0x40000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MIN         (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_MAX         (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_OdtSampExtendEn_HSH         (0x011E0F80)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_OFF            (31)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_WID            ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MSK            (0x80000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MIN            (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_MAX            (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_DEF            (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL0_EarlyRleakEn_HSH            (0x011F0F80)

#define DDRDATA5CH0_CR_DDRCRDATACONTROL3_REG                           (0x00000F88)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_OFF       ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_WID       ( 4)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MSK       (0x0000000F)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MIN       (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_MAX       (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_DEF       (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_HSH       (0x04000F88)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_OFF ( 4)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_WID ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MSK (0x00000030)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MIN (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_MAX (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_DEF (0x00000002)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_TxDqsRankMuxDelay_2nd_stage_offset_HSH (0x02040F88)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_OFF   ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_WID   ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MSK   (0x00000040)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MIN   (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_MAX   (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_DEF   (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_ForceDqsOnQuickOdtOff_HSH   (0x01060F88)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_OFF     ( 7)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_WID     ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MSK     (0x00000080)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MIN     (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_MAX     (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_DEF     (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_Strong2WeakOnDqsOdt_HSH     (0x01070F88)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_OFF             ( 8)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_WID             ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MSK             (0x00003F00)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MIN             (-32)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_MAX             (31) // 0x0000001F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_DEF             (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtDelay_HSH             (0x86080F88)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_OFF  (14)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_WID  ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MSK  (0x00004000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MIN  (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_MAX  (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_DEF  (0x00000001)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_vrefinten_atckepwrdown_HSH  (0x010E0F88)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_OFF      (15)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_WID      ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MSK      (0x00008000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MIN      (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_MAX      (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_DEF      (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtSampExtendEn_HSH      (0x010F0F88)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_OFF          (16)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_WID          ( 3)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MSK          (0x00070000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MIN          (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_MAX          (7) // 0x00000007
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_DqsOdtDuration_HSH          (0x03100F88)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_OFF  (19)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_WID  ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MSK  (0x00080000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MIN  (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_MAX  (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_DEF  (0x00000001)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_AllowOvrdOdtOnAsyncDrv_HSH  (0x01130F88)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_LeakerComp_OFF              (20)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_LeakerComp_WID              ( 3)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_LeakerComp_MSK              (0x00700000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_LeakerComp_MIN              (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_LeakerComp_MAX              (7) // 0x00000007
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_LeakerComp_DEF              (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_LeakerComp_HSH              (0x03140F88)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_OFF          (23)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_WID          ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MSK          (0x00800000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MIN          (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_MAX          (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_rxclkstgnummsb_HSH          (0x01170F88)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_NomPgDis_OFF                (24)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_NomPgDis_WID                ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_NomPgDis_MSK                (0x01000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_NomPgDis_MIN                (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_NomPgDis_MAX                (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_NomPgDis_DEF                (0x00000001)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_NomPgDis_HSH                (0x01180F88)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_OFF   (25)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_WID   ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MSK   (0x02000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MIN   (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_MAX   (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_DEF   (0x00000001)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_rcven_four_cycle_fill_HSH   (0x01190F88)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_OFF          (26)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_WID          ( 4)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MSK          (0x3C000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MIN          (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_MAX          (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_StrongWkLeaker_HSH          (0x041A0F88)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_OFF                (30)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_WID                ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MSK                (0xC0000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MIN                (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_MAX                (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_DEF                (0x00000001)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL3_CBEnAmp1_HSH                (0x021E0F88)

#define DDRDATA5CH0_CR_DDRCRDATACONTROL4_REG                           (0x00000F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_OFF    ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_WID    ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MSK    (0x00000001)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_MAX    (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_leakerwithtxanalogen_HSH    (0x01000F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_OFF   ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_WID   ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MSK   (0x00000002)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MIN   (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_MAX   (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_DEF   (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_glbdrv_clkgate_enable_HSH   (0x01010F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_biasrcomp_OFF               ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_biasrcomp_WID               ( 3)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_biasrcomp_MSK               (0x0000001C)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_biasrcomp_MIN               (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_biasrcomp_MAX               (7) // 0x00000007
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_biasrcomp_DEF               (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_biasrcomp_HSH               (0x03020F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_txdeskewcal_OFF             ( 5)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_txdeskewcal_WID             ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MSK             (0x00000020)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MIN             (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_txdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_txdeskewcal_DEF             (0x00000001)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_txdeskewcal_HSH             (0x01050F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_OFF      ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_WID      ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MSK      (0x00000040)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MIN      (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_txdeskewdqscodesel_HSH      (0x01060F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_OFF             ( 7)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_WID             ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MSK             (0x00000080)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MIN             (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_MAX             (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_DEF             (0x00000001)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxdeskewcal_HSH             (0x01070F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_OFF      ( 8)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_WID      ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MSK      (0x00000100)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MIN      (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_MAX      (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_DEF      (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxdeskewdqscodesel_HSH      (0x01080F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_OFF             ( 9)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_WID             ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MSK             (0x00000600)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MIN             (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_MAX             (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_DEF             (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_DisPanicDrv_HSH             (0x02090F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dllnbiassel_OFF             (11)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dllnbiassel_WID             ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MSK             (0x00000800)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MIN             (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dllnbiassel_MAX             (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dllnbiassel_DEF             (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dllnbiassel_HSH             (0x010B0F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxsel_OFF                   (12)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxsel_WID                   ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxsel_MSK                   (0x00001000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxsel_MIN                   (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxsel_MAX                   (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxsel_DEF                   (0x00000001)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_rxsel_HSH                   (0x010C0F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_ampoffseten_OFF             (13)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_ampoffseten_WID             ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_ampoffseten_MSK             (0x00002000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_ampoffseten_MIN             (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_ampoffseten_MAX             (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_ampoffseten_DEF             (0x00000001)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_ampoffseten_HSH             (0x010D0F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_OFF              (14)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_WID              ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MSK              (0x00004000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MIN              (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_MAX              (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_DEF              (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_LpDdr4Mode_HSH              (0x010E0F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_OFF  (15)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_WID  ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MSK  (0x00008000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MIN  (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_MAX  (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_DEF  (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_lpddr4wrlongpreambleen_HSH  (0x010F0F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_OFF    (16)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_WID    ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MSK    (0x00010000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_MAX    (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_ddr4wrlongpreambleen_HSH    (0x01100F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_OFF       (17)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_WID       ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MSK       (0x00020000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MIN       (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_MAX       (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_DEF       (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_VssODTSingleSegEn_HSH       (0x01110F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_VssODTEn_OFF                (18)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_VssODTEn_WID                ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_VssODTEn_MSK                (0x00040000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_VssODTEn_MIN                (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_VssODTEn_MAX                (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_VssODTEn_DEF                (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_VssODTEn_HSH                (0x01120F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_OFF    (19)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_WID    ( 5)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MSK    (0x00F80000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_MAX    (31) // 0x0000001F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dqsodtdowncompoffset_HSH    (0x05130F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_OFF      (24)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_WID      ( 5)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MSK      (0x1F000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MIN      (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_MAX      (31) // 0x0000001F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_DEF      (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_dqsodtupcompoffset_HSH      (0x05180F8C)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_spare2_OFF                  (29)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_spare2_WID                  ( 3)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_spare2_MSK                  (0xE0000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_spare2_MIN                  (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_spare2_MAX                  (7) // 0x00000007
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_spare2_DEF                  (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL4_spare2_HSH                  (0x031D0F8C)

#define DDRDATA5CH0_CR_DDRCRDATACONTROL5_REG                           (0x00000F90)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_RxVref_OFF                  ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_RxVref_WID                  ( 8)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_RxVref_MSK                  (0x000000FF)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_RxVref_MIN                  (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_RxVref_MAX                  (255) // 0x000000FF
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_RxVref_DEF                  (0x00000060)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_RxVref_HSH                  (0x08000F90)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_OFF       ( 8)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_WID       ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MSK       (0x00000100)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MIN       (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_MAX       (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_DEF       (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrdqsmaskcnten_HSH       (0x01080F90)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_OFF        ( 9)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_WID        ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MSK        (0x00000600)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MIN        (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_MAX        (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_DEF        (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrnumofpulses_HSH        (0x02090F90)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_OFF (11)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_WID ( 4)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MSK (0x00007800)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MIN (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_MAX (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_ddrcrmaskcntpulsenumstart_HSH (0x040B0F90)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_OFF       (15)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_WID       ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MSK       (0x00008000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MIN       (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_MAX       (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_DEF       (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_Lp4xVoltageSelect_HSH       (0x010F0F90)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_OFF         (16)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_WID         ( 8)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MSK         (0x00FF0000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MIN         (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_MAX         (255) // 0x000000FF
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdModeEn_HSH         (0x08100F90)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_OFF           (24)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_WID           ( 8)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MSK           (0xFF000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MIN           (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_MAX           (255) // 0x000000FF
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_DEF           (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL5_DdrDqOvrdData_HSH           (0x08180F90)

#define DDRDATA5CH0_CR_DDRCRDATACONTROL6_REG                           (0x00000F94)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RankOvrd_OFF                ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RankOvrd_WID                ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RankOvrd_MSK                (0x00000001)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RankOvrd_MIN                (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RankOvrd_MAX                (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RankOvrd_DEF                (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RankOvrd_HSH                (0x01000F94)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RankValue_OFF               ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RankValue_WID               ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RankValue_MSK               (0x00000006)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RankValue_MIN               (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RankValue_MAX               (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RankValue_DEF               (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RankValue_HSH               (0x02010F94)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_Gear1_OFF                   ( 3)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_Gear1_WID                   ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_Gear1_MSK                   (0x00000008)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_Gear1_MIN                   (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_Gear1_MAX                   (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_Gear1_DEF                   (0x00000001)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_Gear1_HSH                   (0x01030F94)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_OFF          ( 4)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_WID          ( 5)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MSK          (0x000001F0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MIN          (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RxDqsAmpOffset_HSH          (0x05040F94)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_OFF    ( 9)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_WID    ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MSK    (0x00000200)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MIN    (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_MAX    (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_DEF    (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_fast_dqsoutputenable_HSH    (0x01090F94)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_OFF (10)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_WID ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MSK (0x00000400)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MIN (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_MAX (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_tx_clock_on_with_txanalogen_HSH (0x010A0F94)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_OFF         (11)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_WID         ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MSK         (0x00000800)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MIN         (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_MAX         (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_DEF         (0x00000001)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_local_gate_d0tx_HSH         (0x010B0F94)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_OFF       (12)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_WID       ( 2)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MSK       (0x00003000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MIN       (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_MAX       (3) // 0x00000003
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_DEF       (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_strongwkleakermsb_HSH       (0x020C0F94)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_OFF   (14)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_WID   ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MSK   (0x00004000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MIN   (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_DEF   (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_forcedqsponwithleaker_HSH   (0x010E0F94)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_OFF   (15)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_WID   ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MSK   (0x00008000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MIN   (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_MAX   (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_DEF   (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_forcedqsnonwithleaker_HSH   (0x010F0F94)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_OFF              (16)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_WID              ( 8)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MSK              (0x00FF0000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MIN              (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_MAX              (255) // 0x000000FF
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_DEF              (0x00000002)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_RxBiasCtl1_HSH              (0x08100F94)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_OFF             (24)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_WID             ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MSK             (0x01000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MIN             (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_MAX             (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_DEF             (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_ForceDqsPon_HSH             (0x01180F94)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_OFF             (25)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_WID             ( 1)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MSK             (0x02000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MIN             (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_MAX             (1) // 0x00000001
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_DEF             (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_ForceDqsNon_HSH             (0x01190F94)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_sdll_picb_OFF               (26)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_sdll_picb_WID               ( 3)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_sdll_picb_MSK               (0x1C000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_sdll_picb_MIN               (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_sdll_picb_MAX               (7) // 0x00000007
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_sdll_picb_DEF               (0x00000002)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_sdll_picb_HSH               (0x031A0F94)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_d0_picb_OFF                 (29)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_d0_picb_WID                 ( 3)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_d0_picb_MSK                 (0xE0000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_d0_picb_MIN                 (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_d0_picb_MAX                 (7) // 0x00000007
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_d0_picb_DEF                 (0x00000002)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL6_d0_picb_HSH                 (0x031D0F94)

#define DDRDATA5CH0_CR_DDRCRDATACONTROL7_REG                           (0x00000F98)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_OFF          ( 0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_WID          ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MSK          (0x0000003F)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MIN          (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_MAX          (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank0_HSH          (0x06000F98)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_OFF          ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_WID          ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MSK          (0x00000FC0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MIN          (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_MAX          (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank1_HSH          (0x06060F98)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_OFF          (12)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_WID          ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MSK          (0x0003F000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MIN          (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_MAX          (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank2_HSH          (0x060C0F98)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_OFF          (18)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_WID          ( 6)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MSK          (0x00FC0000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MIN          (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_MAX          (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_DqsDfeDlyRank3_HSH          (0x06120F98)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_OFF            (24)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_WID            ( 4)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MSK            (0x0F000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MIN            (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_MAX            (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_DEF            (0x00000004)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_sdll_bw_ctrl_HSH            (0x04180F98)

  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_OFF              (28)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_WID              ( 4)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MSK              (0xF0000000)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MIN              (0)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_MAX              (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_DEF              (0x00000004)
  #define DDRDATA5CH0_CR_DDRCRDATACONTROL7_d0_bw_ctrl_HSH              (0x041C0F98)

#define DDRDATA5CH0_CR_DELTADQSRANK0_REG                               (0x00000F9C)

  #define DDRDATA5CH0_CR_DELTADQSRANK0_DeltaDQS_OFF                    ( 0)
  #define DDRDATA5CH0_CR_DELTADQSRANK0_DeltaDQS_WID                    (10)
  #define DDRDATA5CH0_CR_DELTADQSRANK0_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA5CH0_CR_DELTADQSRANK0_DeltaDQS_MIN                    (0)
  #define DDRDATA5CH0_CR_DELTADQSRANK0_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA5CH0_CR_DELTADQSRANK0_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_DELTADQSRANK0_DeltaDQS_HSH                    (0x0A000F9C)

  #define DDRDATA5CH0_CR_DELTADQSRANK0_Spare1_OFF                      (10)
  #define DDRDATA5CH0_CR_DELTADQSRANK0_Spare1_WID                      (22)
  #define DDRDATA5CH0_CR_DELTADQSRANK0_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA5CH0_CR_DELTADQSRANK0_Spare1_MIN                      (0)
  #define DDRDATA5CH0_CR_DELTADQSRANK0_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA5CH0_CR_DELTADQSRANK0_Spare1_DEF                      (0x00000000)
  #define DDRDATA5CH0_CR_DELTADQSRANK0_Spare1_HSH                      (0x160A0F9C)

#define DDRDATA5CH0_CR_DELTADQSRANK1_REG                               (0x00000FA0)

  #define DDRDATA5CH0_CR_DELTADQSRANK1_DeltaDQS_OFF                    ( 0)
  #define DDRDATA5CH0_CR_DELTADQSRANK1_DeltaDQS_WID                    (10)
  #define DDRDATA5CH0_CR_DELTADQSRANK1_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA5CH0_CR_DELTADQSRANK1_DeltaDQS_MIN                    (0)
  #define DDRDATA5CH0_CR_DELTADQSRANK1_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA5CH0_CR_DELTADQSRANK1_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_DELTADQSRANK1_DeltaDQS_HSH                    (0x0A000FA0)

  #define DDRDATA5CH0_CR_DELTADQSRANK1_Spare1_OFF                      (10)
  #define DDRDATA5CH0_CR_DELTADQSRANK1_Spare1_WID                      (22)
  #define DDRDATA5CH0_CR_DELTADQSRANK1_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA5CH0_CR_DELTADQSRANK1_Spare1_MIN                      (0)
  #define DDRDATA5CH0_CR_DELTADQSRANK1_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA5CH0_CR_DELTADQSRANK1_Spare1_DEF                      (0x00000000)
  #define DDRDATA5CH0_CR_DELTADQSRANK1_Spare1_HSH                      (0x160A0FA0)

#define DDRDATA5CH0_CR_DELTADQSRANK2_REG                               (0x00000FA4)

  #define DDRDATA5CH0_CR_DELTADQSRANK2_DeltaDQS_OFF                    ( 0)
  #define DDRDATA5CH0_CR_DELTADQSRANK2_DeltaDQS_WID                    (10)
  #define DDRDATA5CH0_CR_DELTADQSRANK2_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA5CH0_CR_DELTADQSRANK2_DeltaDQS_MIN                    (0)
  #define DDRDATA5CH0_CR_DELTADQSRANK2_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA5CH0_CR_DELTADQSRANK2_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_DELTADQSRANK2_DeltaDQS_HSH                    (0x0A000FA4)

  #define DDRDATA5CH0_CR_DELTADQSRANK2_Spare1_OFF                      (10)
  #define DDRDATA5CH0_CR_DELTADQSRANK2_Spare1_WID                      (22)
  #define DDRDATA5CH0_CR_DELTADQSRANK2_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA5CH0_CR_DELTADQSRANK2_Spare1_MIN                      (0)
  #define DDRDATA5CH0_CR_DELTADQSRANK2_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA5CH0_CR_DELTADQSRANK2_Spare1_DEF                      (0x00000000)
  #define DDRDATA5CH0_CR_DELTADQSRANK2_Spare1_HSH                      (0x160A0FA4)

#define DDRDATA5CH0_CR_DELTADQSRANK3_REG                               (0x00000FA8)

  #define DDRDATA5CH0_CR_DELTADQSRANK3_DeltaDQS_OFF                    ( 0)
  #define DDRDATA5CH0_CR_DELTADQSRANK3_DeltaDQS_WID                    (10)
  #define DDRDATA5CH0_CR_DELTADQSRANK3_DeltaDQS_MSK                    (0x000003FF)
  #define DDRDATA5CH0_CR_DELTADQSRANK3_DeltaDQS_MIN                    (0)
  #define DDRDATA5CH0_CR_DELTADQSRANK3_DeltaDQS_MAX                    (1023) // 0x000003FF
  #define DDRDATA5CH0_CR_DELTADQSRANK3_DeltaDQS_DEF                    (0x00000000)
  #define DDRDATA5CH0_CR_DELTADQSRANK3_DeltaDQS_HSH                    (0x0A000FA8)

  #define DDRDATA5CH0_CR_DELTADQSRANK3_Spare1_OFF                      (10)
  #define DDRDATA5CH0_CR_DELTADQSRANK3_Spare1_WID                      (22)
  #define DDRDATA5CH0_CR_DELTADQSRANK3_Spare1_MSK                      (0xFFFFFC00)
  #define DDRDATA5CH0_CR_DELTADQSRANK3_Spare1_MIN                      (0)
  #define DDRDATA5CH0_CR_DELTADQSRANK3_Spare1_MAX                      (4194303) // 0x003FFFFF
  #define DDRDATA5CH0_CR_DELTADQSRANK3_Spare1_DEF                      (0x00000000)
  #define DDRDATA5CH0_CR_DELTADQSRANK3_Spare1_HSH                      (0x160A0FA8)

#define DDRDATA5CH0_CR_RXCONTROL3RANK0_REG                             (0x00000FAC)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane6PerBitDeskew_HSH         (0x06000FAC)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane7PerBitDeskew_HSH         (0x06060FAC)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane4RxOffsetVDq_HSH          (0x050C0FAC)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane5RxOffsetVDq_HSH          (0x05110FAC)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane6RxOffsetVDq_HSH          (0x05160FAC)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK0_Lane7RxOffsetVDq_HSH          (0x051B0FAC)

#define DDRDATA5CH0_CR_RXCONTROL3RANK1_REG                             (0x00000FB0)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane6PerBitDeskew_HSH         (0x06000FB0)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane7PerBitDeskew_HSH         (0x06060FB0)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane4RxOffsetVDq_HSH          (0x050C0FB0)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane5RxOffsetVDq_HSH          (0x05110FB0)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane6RxOffsetVDq_HSH          (0x05160FB0)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK1_Lane7RxOffsetVDq_HSH          (0x051B0FB0)

#define DDRDATA5CH0_CR_RXCONTROL3RANK2_REG                             (0x00000FB4)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane6PerBitDeskew_HSH         (0x06000FB4)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane7PerBitDeskew_HSH         (0x06060FB4)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane4RxOffsetVDq_HSH          (0x050C0FB4)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane5RxOffsetVDq_HSH          (0x05110FB4)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane6RxOffsetVDq_HSH          (0x05160FB4)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK2_Lane7RxOffsetVDq_HSH          (0x051B0FB4)

#define DDRDATA5CH0_CR_RXCONTROL3RANK3_REG                             (0x00000FB8)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_OFF         ( 0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MSK         (0x0000003F)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane6PerBitDeskew_HSH         (0x06000FB8)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_OFF         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_WID         ( 6)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MSK         (0x00000FC0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MIN         (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_MAX         (63) // 0x0000003F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane7PerBitDeskew_HSH         (0x06060FB8)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_OFF          (12)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MSK          (0x0001F000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane4RxOffsetVDq_HSH          (0x050C0FB8)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_OFF          (17)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MSK          (0x003E0000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane5RxOffsetVDq_HSH          (0x05110FB8)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_OFF          (22)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MSK          (0x07C00000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane6RxOffsetVDq_HSH          (0x05160FB8)

  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_OFF          (27)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_WID          ( 5)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MSK          (0xF8000000)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MIN          (0)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_DEF          (0x00000008)
  #define DDRDATA5CH0_CR_RXCONTROL3RANK3_Lane7RxOffsetVDq_HSH          (0x051B0FB8)

#define DDRDATA5CH0_CR_TXPERBITHIRANK0_REG                             (0x00000FBC)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane4_OFF                     ( 0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane4_WID                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane4_MSK                     (0x0000003F)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane4_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane4_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane4_HSH                     (0x06000FBC)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane5_OFF                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane5_WID                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane5_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane5_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane5_HSH                     (0x06060FBC)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane6_OFF                     (12)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane6_WID                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane6_MSK                     (0x0003F000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane6_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane6_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane6_HSH                     (0x060C0FBC)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane7_OFF                     (18)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane7_WID                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane7_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane7_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Lane7_HSH                     (0x06120FBC)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Spare_OFF                     (24)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Spare_WID                     ( 8)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Spare_MSK                     (0xFF000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Spare_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Spare_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK0_Spare_HSH                     (0x08180FBC)

#define DDRDATA5CH0_CR_TXPERBITHIRANK1_REG                             (0x00000FC0)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane4_OFF                     ( 0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane4_WID                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane4_MSK                     (0x0000003F)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane4_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane4_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane4_HSH                     (0x06000FC0)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane5_OFF                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane5_WID                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane5_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane5_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane5_HSH                     (0x06060FC0)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane6_OFF                     (12)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane6_WID                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane6_MSK                     (0x0003F000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane6_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane6_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane6_HSH                     (0x060C0FC0)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane7_OFF                     (18)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane7_WID                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane7_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane7_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Lane7_HSH                     (0x06120FC0)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Spare_OFF                     (24)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Spare_WID                     ( 8)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Spare_MSK                     (0xFF000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Spare_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Spare_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK1_Spare_HSH                     (0x08180FC0)

#define DDRDATA5CH0_CR_TXPERBITHIRANK2_REG                             (0x00000FC4)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane4_OFF                     ( 0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane4_WID                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane4_MSK                     (0x0000003F)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane4_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane4_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane4_HSH                     (0x06000FC4)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane5_OFF                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane5_WID                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane5_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane5_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane5_HSH                     (0x06060FC4)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane6_OFF                     (12)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane6_WID                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane6_MSK                     (0x0003F000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane6_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane6_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane6_HSH                     (0x060C0FC4)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane7_OFF                     (18)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane7_WID                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane7_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane7_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Lane7_HSH                     (0x06120FC4)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Spare_OFF                     (24)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Spare_WID                     ( 8)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Spare_MSK                     (0xFF000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Spare_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Spare_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK2_Spare_HSH                     (0x08180FC4)

#define DDRDATA5CH0_CR_TXPERBITHIRANK3_REG                             (0x00000FC8)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane4_OFF                     ( 0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane4_WID                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane4_MSK                     (0x0000003F)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane4_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane4_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane4_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane4_HSH                     (0x06000FC8)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane5_OFF                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane5_WID                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane5_MSK                     (0x00000FC0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane5_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane5_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane5_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane5_HSH                     (0x06060FC8)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane6_OFF                     (12)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane6_WID                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane6_MSK                     (0x0003F000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane6_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane6_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane6_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane6_HSH                     (0x060C0FC8)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane7_OFF                     (18)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane7_WID                     ( 6)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane7_MSK                     (0x00FC0000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane7_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane7_MAX                     (63) // 0x0000003F
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane7_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Lane7_HSH                     (0x06120FC8)

  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Spare_OFF                     (24)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Spare_WID                     ( 8)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Spare_MSK                     (0xFF000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Spare_MIN                     (0)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Spare_MAX                     (255) // 0x000000FF
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Spare_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_TXPERBITHIRANK3_Spare_HSH                     (0x08180FC8)

#define DDRDATA5CH0_CR_DCCDATACONTROL0_REG                             (0x00000FCC)

  #define DDRDATA5CH0_CR_DCCDATACONTROL0_GVPointG1_OFF                 ( 0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_GVPointG1_WID                 ( 1)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_GVPointG1_MSK                 (0x00000001)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_GVPointG1_MIN                 (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_GVPointG1_MAX                 (1) // 0x00000001
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_GVPointG1_DEF                 (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_GVPointG1_HSH                 (0x01000FCC)

  #define DDRDATA5CH0_CR_DCCDATACONTROL0_GVPointG2_OFF                 ( 1)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_GVPointG2_WID                 ( 2)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_GVPointG2_MSK                 (0x00000006)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_GVPointG2_MIN                 (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_GVPointG2_MAX                 (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_GVPointG2_DEF                 (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_GVPointG2_HSH                 (0x02010FCC)

  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_OFF          ( 3)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_WID          ( 1)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MSK          (0x00000008)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_MAX          (1) // 0x00000001
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ReplicaOffsetUse_HSH          (0x01030FCC)

  #define DDRDATA5CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_OFF           ( 4)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_WID           ( 2)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MSK           (0x00000030)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_MAX           (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_DEF           (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_VTCompOffsetUse_HSH           (0x02040FCC)

  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ExtOffset_OFF                 ( 6)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ExtOffset_WID                 ( 7)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ExtOffset_MSK                 (0x00001FC0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ExtOffset_MIN                 (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ExtOffset_MAX                 (127) // 0x0000007F
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ExtOffset_DEF                 (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ExtOffset_HSH                 (0x07060FCC)

  #define DDRDATA5CH0_CR_DCCDATACONTROL0_BiasOffset_OFF                (13)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_BiasOffset_WID                (15)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_BiasOffset_MSK                (0x0FFFE000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_BiasOffset_MIN                (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_BiasOffset_MAX                (32767) // 0x00007FFF
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_BiasOffset_DEF                (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_BiasOffset_HSH                (0x0F0D0FCC)

  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ActiveRanks_OFF               (28)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ActiveRanks_WID               ( 4)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ActiveRanks_MSK               (0xF0000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ActiveRanks_MIN               (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ActiveRanks_MAX               (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ActiveRanks_DEF               (0x00000003)
  #define DDRDATA5CH0_CR_DCCDATACONTROL0_ActiveRanks_HSH               (0x041C0FCC)

#define DDRDATA5CH0_CR_DCCDATACONTROL1_REG                             (0x00000FD0)

  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DccCodeOvrd_OFF               ( 0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DccCodeOvrd_WID               ( 6)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MSK               (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MIN               (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DccCodeOvrd_MAX               (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DccCodeOvrd_DEF               (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DccCodeOvrd_HSH               (0x06000FD0)

  #define DDRDATA5CH0_CR_DCCDATACONTROL1_RepDccAipCb_OFF               ( 6)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_RepDccAipCb_WID               ( 2)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_RepDccAipCb_MSK               (0x000000C0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_RepDccAipCb_MIN               (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_RepDccAipCb_MAX               (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_RepDccAipCb_DEF               (0x00000001)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_RepDccAipCb_HSH               (0x02060FD0)

  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DccPtrOvrd_OFF                ( 8)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DccPtrOvrd_WID                ( 4)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MSK                (0x00000F00)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MIN                (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DccPtrOvrd_MAX                (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DccPtrOvrd_DEF                (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DccPtrOvrd_HSH                (0x04080FD0)

  #define DDRDATA5CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_OFF                (12)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_WID                ( 2)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MSK                (0x00003000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MIN                (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_MAX                (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_DEF                (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_RnkPtrOvrd_HSH                (0x020C0FD0)

  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_OFF              (14)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_WID              ( 1)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MSK              (0x00004000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MIN              (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_DEF              (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdDigEnOvrd_HSH              (0x010E0FD0)

  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_OFF              (15)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_WID              ( 1)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MSK              (0x00008000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MIN              (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_MAX              (1) // 0x00000001
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_DEF              (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdAnaEnOvrd_HSH              (0x010F0FD0)

  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdWindow_OFF                 (16)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdWindow_WID                 (15)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdWindow_MSK                 (0x7FFF0000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdWindow_MIN                 (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdWindow_MAX                 (32767) // 0x00007FFF
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdWindow_DEF                 (0x00000800)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_DcdWindow_HSH                 (0x0F100FD0)

  #define DDRDATA5CH0_CR_DCCDATACONTROL1_Spare_OFF                     (31)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_Spare_WID                     ( 1)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_Spare_MSK                     (0x80000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_Spare_MIN                     (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_Spare_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL1_Spare_HSH                     (0x011F0FD0)

#define DDRDATA5CH0_CR_DCCDATACONTROL2_REG                             (0x00000FD4)

  #define DDRDATA5CH0_CR_DCCDATACONTROL2_StartBinCode_OFF              ( 0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_StartBinCode_WID              ( 6)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_StartBinCode_MSK              (0x0000003F)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_StartBinCode_MIN              (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_StartBinCode_MAX              (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_StartBinCode_DEF              (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_StartBinCode_HSH              (0x06000FD4)

  #define DDRDATA5CH0_CR_DCCDATACONTROL2_CodePtrStartBit_OFF           ( 6)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_CodePtrStartBit_WID           ( 3)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MSK           (0x000001C0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MIN           (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_CodePtrStartBit_MAX           (7) // 0x00000007
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_CodePtrStartBit_DEF           (0x00000005)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_CodePtrStartBit_HSH           (0x03060FD4)

  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DccTrshOld_OFF                ( 9)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DccTrshOld_WID                (13)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DccTrshOld_MSK                (0x003FFE00)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DccTrshOld_MIN                (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DccTrshOld_MAX                (8191) // 0x00001FFF
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DccTrshOld_DEF                (0x00000008)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DccTrshOld_HSH                (0x0D090FD4)

  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_OFF          (22)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_WID          ( 5)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MSK          (0x07C00000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_MAX          (31) // 0x0000001F
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_DEF          (0x00000003)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DcdCntsStartDiff_HSH          (0x05160FD4)

  #define DDRDATA5CH0_CR_DCCDATACONTROL2_ClkGateDisable_OFF            (27)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_ClkGateDisable_WID            ( 1)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_ClkGateDisable_MSK            (0x08000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_ClkGateDisable_MIN            (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_ClkGateDisable_MAX            (1) // 0x00000001
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_ClkGateDisable_DEF            (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_ClkGateDisable_HSH            (0x011B0FD4)

  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_OFF        (28)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_WID        ( 4)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MSK        (0xF0000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_MAX        (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_DEF        (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL2_DccDataViewSelect0_HSH        (0x041C0FD4)

#define DDRDATA5CH0_CR_DCCDATACONTROL3_REG                             (0x00000FD8)

  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank0_OFF            ( 0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank0_WID            (11)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MSK            (0x000007FF)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MIN            (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank0_MAX            (2047) // 0x000007FF
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank0_DEF            (0x000007FF)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank0_HSH            (0x0B000FD8)

  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank1_OFF            (11)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank1_WID            ( 9)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MSK            (0x000FF800)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MIN            (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank1_MAX            (511) // 0x000001FF
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank1_DEF            (0x000001FF)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank1_HSH            (0x090B0FD8)

  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank2_OFF            (20)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank2_WID            ( 9)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MSK            (0x1FF00000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MIN            (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank2_MAX            (511) // 0x000001FF
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank2_DEF            (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_ActiveDccRank2_HSH            (0x09140FD8)

  #define DDRDATA5CH0_CR_DCCDATACONTROL3_Spare_OFF                     (29)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_Spare_WID                     ( 3)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_Spare_MSK                     (0xE0000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_Spare_MIN                     (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_Spare_MAX                     (7) // 0x00000007
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_Spare_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL3_Spare_HSH                     (0x031D0FD8)

#define DDRDATA5CH0_CR_DCCDATACONTROL4_REG                             (0x00000FDC)

  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ActiveDccRank3_OFF            ( 0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ActiveDccRank3_WID            ( 9)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MSK            (0x000001FF)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MIN            (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ActiveDccRank3_MAX            (511) // 0x000001FF
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ActiveDccRank3_DEF            (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ActiveDccRank3_HSH            (0x09000FDC)

  #define DDRDATA5CH0_CR_DCCDATACONTROL4_Spare_OFF                     ( 9)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_Spare_WID                     ( 1)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_Spare_MSK                     (0x00000200)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_Spare_MIN                     (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_Spare_MAX                     (1) // 0x00000001
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_Spare_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_Spare_HSH                     (0x01090FDC)

  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_OFF          (10)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_WID          ( 6)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MSK          (0x0000FC00)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_MAX          (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_DEF          (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp0_HSH          (0x060A0FDC)

  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_OFF          (16)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_WID          ( 6)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MSK          (0x003F0000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_MAX          (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_DEF          (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp1_HSH          (0x06100FDC)

  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_OFF          (22)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_WID          ( 6)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MSK          (0x0FC00000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_MAX          (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_DEF          (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_ReplicaPrev_GVp2_HSH          (0x06160FDC)

  #define DDRDATA5CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_OFF        (28)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_WID        ( 4)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MSK        (0xF0000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MIN        (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_MAX        (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_DEF        (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL4_DccDataViewSelect1_HSH        (0x041C0FDC)

#define DDRDATA5CH0_CR_DCCDATACONTROL5_REG                             (0x00000FE0)

  #define DDRDATA5CH0_CR_DCCDATACONTROL5_Spare_OFF                     ( 0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_Spare_WID                     ( 2)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_Spare_MSK                     (0x00000003)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_Spare_MIN                     (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_Spare_MAX                     (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_Spare_DEF                     (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_Spare_HSH                     (0x02000FE0)

  #define DDRDATA5CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_OFF       ( 2)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_WID       ( 1)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MSK       (0x00000004)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MIN       (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_MAX       (1) // 0x00000001
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_DEF       (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_vtcompoffsetmsgwren_HSH       (0x01020FE0)

  #define DDRDATA5CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_OFF          ( 3)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_WID          ( 6)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MSK          (0x000001F8)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_MAX          (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_DEF          (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_ReplicaPrev_GVp3_HSH          (0x06030FE0)

  #define DDRDATA5CH0_CR_DCCDATACONTROL5_BubbleCntVal_OFF              ( 9)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_BubbleCntVal_WID              ( 5)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_BubbleCntVal_MSK              (0x00003E00)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_BubbleCntVal_MIN              (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_BubbleCntVal_MAX              (31) // 0x0000001F
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_BubbleCntVal_DEF              (0x0000000B)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_BubbleCntVal_HSH              (0x05090FE0)

  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_OFF      (14)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_WID      ( 6)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MSK      (0x000FC000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MIN      (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_MAX      (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_DEF      (0x00000020)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicSyncVal_HSH      (0x060E0FE0)

  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicCntVal_OFF       (20)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicCntVal_WID       (11)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MSK       (0x7FF00000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MIN       (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicCntVal_MAX       (2047) // 0x000007FF
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicCntVal_DEF       (0x0000010E)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicCntVal_HSH       (0x0B140FE0)

  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicMode_OFF         (31)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicMode_WID         ( 1)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicMode_MSK         (0x80000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicMode_MIN         (0)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicMode_MAX         (1) // 0x00000001
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicMode_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATACONTROL5_DeterministicMode_HSH         (0x011F0FE0)

#define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_REG                         (0x00000FE4)

  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_OFF          ( 0)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_WID          (11)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MSK          (0x000007FF)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_MAX          (2047) // 0x000007FF
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank0DccDone_HSH          (0x0B000FE4)

  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_OFF          (11)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_WID          ( 9)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MSK          (0x000FF800)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank1DccDone_HSH          (0x090B0FE4)

  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_OFF          (20)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_WID          ( 9)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MSK          (0x1FF00000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Rank2DccDone_HSH          (0x09140FE4)

  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Spare_OFF                 (29)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Spare_WID                 ( 3)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Spare_MSK                 (0xE0000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Spare_MIN                 (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Spare_MAX                 (7) // 0x00000007
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Spare_DEF                 (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS0_Spare_HSH                 (0x031D0FE4)

#define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_REG                         (0x00000FE8)

  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_OFF          ( 0)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_WID          ( 9)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MSK          (0x000001FF)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_MAX          (511) // 0x000001FF
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Rank3DccDone_HSH          (0x09000FE8)

  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Spare0_OFF                ( 9)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Spare0_WID                ( 1)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Spare0_MSK                (0x00000200)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Spare0_MIN                (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Spare0_MAX                (1) // 0x00000001
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Spare0_DEF                (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Spare0_HSH                (0x01090FE8)

  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_CntDone_OFF               (10)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_CntDone_WID               ( 1)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_CntDone_MSK               (0x00000400)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_CntDone_MIN               (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_CntDone_MAX               (1) // 0x00000001
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_CntDone_DEF               (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_CntDone_HSH               (0x010A0FE8)

  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_OFF             (11)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_WID             (15)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MSK             (0x03FFF800)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MIN             (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_MAX             (32767) // 0x00007FFF
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_DEF             (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Dcd_O_Cnt_HSH             (0x0F0B0FE8)

  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Spare1_OFF                (26)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Spare1_WID                ( 1)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Spare1_MSK                (0x04000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Spare1_MIN                (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Spare1_MAX                (1) // 0x00000001
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Spare1_DEF                (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_Spare1_HSH                (0x011A0FE8)

  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_OFF       (27)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_WID       ( 5)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MSK       (0xF8000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MIN       (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_MAX       (31) // 0x0000001F
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_DEF       (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS1_BinFsmCurrState_HSH       (0x051B0FE8)

#define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_REG                         (0x00000FEC)

  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_OFF                ( 0)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_WID                (16)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MSK                (0x0000FFFF)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MIN                (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_MAX                (65535) // 0x0000FFFF
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_DEF                (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_AuxCnt_HSH                (0x10000FEC)

  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_OFF         (16)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_WID         ( 7)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MSK         (0x007F0000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MIN         (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_MAX         (127) // 0x0000007F
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_DEF         (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_ReplicaOffset_HSH         (0x07100FEC)

  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_OFF          (23)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_WID          ( 7)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MSK          (0x3F800000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_MAX          (127) // 0x0000007F
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_VTCompOffset_HSH          (0x07170FEC)

  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_Spare_OFF                 (30)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_Spare_WID                 ( 2)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_Spare_MSK                 (0xC0000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_Spare_MIN                 (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_Spare_MAX                 (3) // 0x00000003
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_Spare_DEF                 (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINSTATUS2_Spare_HSH                 (0x021E0FEC)

#define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_REG                  (0x00000FF0)

  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_OFF ( 0)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_WID (11)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MSK (0x000007FF)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MIN (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_MAX (2047) // 0x000007FF
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_DccConvergeErr_HSH (0x0B000FF0)

  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_OFF (11)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_WID (17)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MSK (0x0FFFF800)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MIN (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_MaxConvergeErr_HSH (0x110B0FF0)

  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_OFF          (28)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_WID          ( 4)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MSK          (0xF0000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_MAX          (15) // 0x0000000F
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK0_Spare_HSH          (0x041C0FF0)

#define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_REG                  (0x00000FF4)

  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_OFF ( 0)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_WID ( 9)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MIN (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_DccConvergeErr_HSH (0x09000FF4)

  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_OFF ( 9)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_WID (17)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MIN (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_MaxConvergeErr_HSH (0x11090FF4)

  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_OFF          (26)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_WID          ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MSK          (0xFC000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK1_Spare_HSH          (0x061A0FF4)

#define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_REG                  (0x00000FF8)

  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_OFF ( 0)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_WID ( 9)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MIN (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_DccConvergeErr_HSH (0x09000FF8)

  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_OFF ( 9)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_WID (17)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MIN (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_MaxConvergeErr_HSH (0x11090FF8)

  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_OFF          (26)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_WID          ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MSK          (0xFC000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK2_Spare_HSH          (0x061A0FF8)

#define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_REG                  (0x00000FFC)

  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_OFF ( 0)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_WID ( 9)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MSK (0x000001FF)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MIN (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_MAX (511) // 0x000001FF
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_DccConvergeErr_HSH (0x09000FFC)

  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_OFF ( 9)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_WID (17)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MSK (0x03FFFE00)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MIN (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_MAX (131071) // 0x0001FFFF
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_DEF (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_MaxConvergeErr_HSH (0x11090FFC)

  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_OFF          (26)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_WID          ( 6)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MSK          (0xFC000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MIN          (0)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_MAX          (63) // 0x0000003F
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_DEF          (0x00000000)
  #define DDRDATA5CH0_CR_DCCDATATRAINERRSTATUSRANK3_Spare_HSH          (0x061A0FFC)
#pragma pack(pop)
#endif
