/** @file
  Register names for VTD block
  <b>Conventions</b>:
  - Prefixes:
    - Definitions beginning with "R_" are registers
    - Definitions beginning with "B_" are bits within registers
    - Definitions beginning with "V_" are meaningful values of bits within the registers
    - Definitions beginning with "S_" are register sizes
    - Definitions beginning with "N_" are the bit position
@copyright
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  This file contains an 'Intel Peripheral Driver' and is uniquely identified as
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@par Specification Reference:
**/
#ifndef _VTD_REGS_H_
#define _VTD_REGS_H_

#define VTD_ENGINE_NUMBER                       3
#define R_MCHBAR_VTDTRKLCK                      0x73FC
#define R_VTD_ECAP_OFFSET                       0x10
#define B_VTD_ECAP_REG_IR                       BIT3

///
/// Vt-d Engine base address.
///
#define R_MCHBAR_VTD1_OFFSET                 0x5400  ///< HW UNIT1 for IGD
#define R_MCHBAR_VTD2_LOW_OFFSET             0x7880  ///< HW UNIT2 for IPU
#define R_MCHBAR_VTD2_HIGH_OFFSET            0x7884  ///< HW UNIT2 for IPU
#define R_MCHBAR_ITBT_PCIE_0_VTD_LOW_OFFSET  0x7888  ///< HW UNIT4 for iTBT PCIE0
#define R_MCHBAR_ITBT_PCIE_0_VTD_HIGH_OFFSET 0x788C  ///< HW UNIT4 for iTBT PCIE0
#define R_MCHBAR_ITBT_PCIE_1_VTD_LOW_OFFSET  0x7890  ///< HW UNIT5 for iTBT PCIE1
#define R_MCHBAR_ITBT_PCIE_1_VTD_HIGH_OFFSET 0x7894  ///< HW UNIT5 for iTBT PCIE1
#define R_MCHBAR_ITBT_PCIE_2_VTD_LOW_OFFSET  0x7898  ///< HW UNIT6 for iTBT PCIE2
#define R_MCHBAR_ITBT_PCIE_2_VTD_HIGH_OFFSET 0x789C  ///< HW UNIT6 for iTBT PCIE2
#define R_MCHBAR_ITBT_PCIE_3_VTD_LOW_OFFSET  0x78A0  ///< HW UNIT7 for iTBT PCIE3
#define R_MCHBAR_ITBT_PCIE_3_VTD_HIGH_OFFSET 0x78A4  ///< HW UNIT7 for iTBT PCIE3
#define R_MCHBAR_ITBT_PCIE_4_VTD_LOW_OFFSET  0x78A8  ///< HW UNIT8 for iTBT PCIE4
#define R_MCHBAR_ITBT_PCIE_4_VTD_HIGH_OFFSET 0x78AC  ///< HW UNIT8 for iTBT PCIE4
#define R_MCHBAR_ITBT_PCIE_5_VTD_LOW_OFFSET  0x78B0  ///< HW UNIT9 for iTBT PCIE5
#define R_MCHBAR_ITBT_PCIE_5_VTD_HIGH_OFFSET 0x78B4  ///< HW UNIT9 for iTBT PCIE5
#define R_MCHBAR_VTD3_OFFSET                 0x5410  ///< HW UNIT3 for all other - PEG, USB, SATA etc

///
/// Protected memory registers w.r.t. VTD3 bar
///
#define R_VTD_PMEN_OFFSET                    0x64
#define R_VTD_PLMBASE_OFFSET                 0x68
#define R_VTD_PLMLIMIT_OFFSET                0x6C
#define R_VTD_PHMBASE_OFFSET                 0x70
#define R_VTD_PHM_LIMIT_OFFSET               0x78

#endif
