#ifndef __MrcMcRegisterTgl1Cxxx_h__
#define __MrcMcRegisterTgl1Cxxx_h__
/** @file
  This file was automatically generated. Modify at your own risk.
  Note that no error checking is done in these functions so ensure that the correct values are passed.

@copyright
  Copyright (c) 2010 - 2019 Intel Corporation. All rights reserved
  This software and associated documentation (if any) is furnished
  under a license and may only be used or copied in accordance
  with the terms of the license. Except as permitted by the
  license, no part of this software or documentation may be
  reproduced, stored in a retrieval system, or transmitted in any
  form or by any means without the express written consent of
  Intel Corporation.
  This file contains an 'Intel Peripheral Driver' and is uniquely
  identified as "Intel Reference Module" and is licensed for Intel
  CPUs and chipsets under the terms of your license agreement with
  Intel or your vendor. This file may be modified by the user, subject
  to additional terms of the license agreement.

@par Specification Reference:
**/

#pragma pack(push, 1)


#define MC1_CR_CPGC2_ACCESS_CONTROL_POLICY_REG                         (0x0001C000)
//Duplicate of MC0_CR_CPGC2_ACCESS_CONTROL_POLICY_REG

#define MC1_CR_CPGC2_ACCESS_READ_POLICY_REG                            (0x0001C008)
//Duplicate of MC0_CR_CPGC2_ACCESS_READ_POLICY_REG

#define MC1_CR_CPGC2_ACCESS_WRITE_POLICY_REG                           (0x0001C010)
//Duplicate of MC0_CR_CPGC2_ACCESS_WRITE_POLICY_REG

#define MC1_CR_CPGC2_VISA_MUX_SEL_REG                                  (0x0001C018)
//Duplicate of MC0_CR_CPGC2_VISA_MUX_SEL_REG

#define MC1_CR_CPGC2_STG_CHICKEN_REG                                   (0x0001C020)
//Duplicate of MC0_CR_CPGC2_STG_CHICKEN_REG

#define MC1_CR_CPGC2_CREDIT_CFG_REG                                    (0x0001C028)
//Duplicate of MC0_CR_CPGC2_CREDIT_CFG_REG

#define MC1_CR_CPGC2_V_CHICKEN_REG                                     (0x0001C02C)
//Duplicate of MC0_CR_CPGC2_V_CHICKEN_REG

#define MC1_REQ0_CR_CPGC2_ADDRESS_CONTROL_REG                          (0x0001C030)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_CONTROL_REG

#define MC1_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG                    (0x0001C034)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_1_REG                    (0x0001C035)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_2_REG                    (0x0001C036)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_3_REG                    (0x0001C037)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_DATA_CONTROL_REG                             (0x0001C038)
//Duplicate of MC0_REQ0_CR_CPGC2_DATA_CONTROL_REG

#define MC1_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG                       (0x0001C03C)
//Duplicate of MC0_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_DATA_INSTRUCTION_1_REG                       (0x0001C03D)
//Duplicate of MC0_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_DATA_INSTRUCTION_2_REG                       (0x0001C03E)
//Duplicate of MC0_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_DATA_INSTRUCTION_3_REG                       (0x0001C03F)
//Duplicate of MC0_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_ADDRESS_DATA_STATUS_REG                      (0x0001C040)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_DATA_STATUS_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG                  (0x0001C044)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_1_REG                  (0x0001C045)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_2_REG                  (0x0001C046)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_3_REG                  (0x0001C047)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_4_REG                  (0x0001C048)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_5_REG                  (0x0001C049)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_6_REG                  (0x0001C04A)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_7_REG                  (0x0001C04B)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG             (0x0001C04C)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_1_REG             (0x0001C04D)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_2_REG             (0x0001C04E)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_3_REG             (0x0001C04F)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_4_REG             (0x0001C050)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_5_REG             (0x0001C051)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_6_REG             (0x0001C052)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_7_REG             (0x0001C053)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_WAIT_COUNT_CURRENT_REG             (0x0001C054)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_WAIT_COUNT_CURRENT_REG

#define MC1_REQ0_CR_CPGC2_ALGORITHM_WAIT_EVENT_CONTROL_REG             (0x0001C058)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_WAIT_EVENT_CONTROL_REG

#define MC1_REQ0_CR_CPGC2_BASE_REPEATS_REG                             (0x0001C05C)
//Duplicate of MC0_REQ0_CR_CPGC2_BASE_REPEATS_REG

#define MC1_REQ0_CR_CPGC2_BASE_REPEATS_CURRENT_REG                     (0x0001C060)
//Duplicate of MC0_REQ0_CR_CPGC2_BASE_REPEATS_CURRENT_REG

#define MC1_REQ0_CR_CPGC2_BASE_COL_REPEATS_REG                         (0x0001C064)
//Duplicate of MC0_REQ0_CR_CPGC2_BASE_COL_REPEATS_REG

#define MC1_REQ0_CR_CPGC2_BLOCK_REPEATS_REG                            (0x0001C068)
//Duplicate of MC0_REQ0_CR_CPGC2_BLOCK_REPEATS_REG

#define MC1_REQ0_CR_CPGC2_BLOCK_REPEATS_CURRENT_REG                    (0x0001C06C)
//Duplicate of MC0_REQ0_CR_CPGC2_BLOCK_REPEATS_CURRENT_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG                    (0x0001C070)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_1_REG                    (0x0001C071)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_2_REG                    (0x0001C072)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_3_REG                    (0x0001C073)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_4_REG                    (0x0001C074)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_5_REG                    (0x0001C075)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_6_REG                    (0x0001C076)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_7_REG                    (0x0001C077)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_8_REG                    (0x0001C078)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_9_REG                    (0x0001C079)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_10_REG                   (0x0001C07A)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_11_REG                   (0x0001C07B)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_12_REG                   (0x0001C07C)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_13_REG                   (0x0001C07D)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_14_REG                   (0x0001C07E)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_15_REG                   (0x0001C07F)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_16_REG                   (0x0001C080)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_17_REG                   (0x0001C081)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_18_REG                   (0x0001C082)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_19_REG                   (0x0001C083)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_20_REG                   (0x0001C084)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_21_REG                   (0x0001C085)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_22_REG                   (0x0001C086)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_23_REG                   (0x0001C087)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_HAMMER_REPEATS_REG                           (0x0001C088)
//Duplicate of MC0_REQ0_CR_CPGC2_HAMMER_REPEATS_REG

#define MC1_REQ0_CR_CPGC2_HAMMER_REPEATS_CURRENT_REG                   (0x0001C08C)
//Duplicate of MC0_REQ0_CR_CPGC2_HAMMER_REPEATS_CURRENT_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG             (0x0001C090)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_1_REG             (0x0001C091)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_2_REG             (0x0001C092)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_3_REG             (0x0001C093)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_4_REG             (0x0001C094)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_5_REG             (0x0001C095)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_6_REG             (0x0001C096)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_7_REG             (0x0001C097)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_8_REG             (0x0001C098)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_9_REG             (0x0001C099)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_10_REG            (0x0001C09A)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_11_REG            (0x0001C09B)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_12_REG            (0x0001C09C)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_13_REG            (0x0001C09D)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_14_REG            (0x0001C09E)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_15_REG            (0x0001C09F)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG             (0x0001C0A0)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_1_REG             (0x0001C0A1)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_2_REG             (0x0001C0A2)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_3_REG             (0x0001C0A3)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_4_REG             (0x0001C0A4)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_5_REG             (0x0001C0A5)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_6_REG             (0x0001C0A6)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_7_REG             (0x0001C0A7)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_8_REG             (0x0001C0A8)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_9_REG             (0x0001C0A9)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_10_REG            (0x0001C0AA)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_11_REG            (0x0001C0AB)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_REPEATS_CURRENT_REG                   (0x0001C0AC)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_REPEATS_CURRENT_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_REPEATS_0_REG                         (0x0001C0B0)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_REPEATS_0_REG

#define MC1_REQ0_CR_CPGC2_OFFSET_REPEATS_1_REG                         (0x0001C0B4)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_REPEATS_0_REG

#define MC1_REQ0_CR_CPGC2_REGION_LOW_REG                               (0x0001C0B8)
//Duplicate of MC0_REQ0_CR_CPGC2_REGION_LOW_REG

#define MC1_REQ0_CR_CPGC2_ADDRESS_SIZE_REG                             (0x0001C0D8)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_SIZE_REG

#define MC1_REQ0_CR_CPGC2_BASE_ADDRESS_CONTROL_REG                     (0x0001C0E0)
//Duplicate of MC0_REQ0_CR_CPGC2_BASE_ADDRESS_CONTROL_REG

#define MC1_REQ0_CR_CPGC2_ADDRESS_PRBS_SEED_REG                        (0x0001C0E8)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_PRBS_SEED_REG

#define MC1_REQ0_CR_CPGC2_ADDRESS_PRBS_CURRENT_REG                     (0x0001C0F0)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_PRBS_CURRENT_REG

#define MC1_REQ0_CR_CPGC2_ADDRESS_PRBS_SAVE_REG                        (0x0001C0F8)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_PRBS_SAVE_REG

#define MC1_REQ0_CR_CPGC2_ADDRESS_PRBS_POLY_REG                        (0x0001C100)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_PRBS_POLY_REG

#define MC1_REQ0_CR_CPGC2_BASE_CLOCK_CONFIG_REG                        (0x0001C108)
//Duplicate of MC0_REQ0_CR_CPGC2_BASE_CLOCK_CONFIG_REG

#define MC1_REQ0_CR_CPGC2_CMD_FSM_CURRENT_REG                          (0x0001C10C)
//Duplicate of MC0_REQ0_CR_CPGC2_CMD_FSM_CURRENT_REG

#define MC1_REQ0_CR_CPGC_SEQ_CFG_A_REG                                 (0x0001C110)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_CFG_A_REG

#define MC1_REQ0_CR_CPGC_SEQ_CFG_B_REG                                 (0x0001C114)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_CFG_B_REG

#define MC1_REQ0_CR_CPGC_SEQ_CTL_REG                                   (0x0001C118)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_CTL_REG

#define MC1_REQ0_CR_CPGC_SEQ_STATUS_REG                                (0x0001C11C)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_STATUS_REG

#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG                     (0x0001C120)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_1_REG                     (0x0001C128)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_2_REG                     (0x0001C130)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_3_REG                     (0x0001C138)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_4_REG                     (0x0001C140)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_5_REG                     (0x0001C148)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_6_REG                     (0x0001C150)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_7_REG                     (0x0001C158)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_ECC_0_REG                 (0x0001C160)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_ECC_1_REG                 (0x0001C168)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH0_CR_CPGC2_READ_COMMAND_COUNT_CURRENT_REG                (0x0001C170)
//Duplicate of MC0_CH0_CR_CPGC2_READ_COMMAND_COUNT_CURRENT_REG

#define MC1_CH0_CR_CPGC2_MASK_ERRS_FIRST_N_READS_REG                   (0x0001C174)
//Duplicate of MC0_CH0_CR_CPGC2_MASK_ERRS_FIRST_N_READS_REG

#define MC1_CH0_CR_CPGC2_ERR_SUMMARY_A_REG                             (0x0001C178)
//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_A_REG

#define MC1_CH0_CR_CPGC2_ERR_SUMMARY_B_REG                             (0x0001C17C)
//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_A_REG

#define MC1_CH0_CR_CPGC2_ERR_SUMMARY_C_REG                             (0x0001C180)
//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_C_REG

#define MC1_CH0_CR_CPGC2_RASTER_MODE3_MAX_REG                          (0x0001C184)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_MODE3_MAX_REG

#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONFIG_REG                        (0x0001C188)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONFIG_REG

#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONFIG_P0_REG                     (0x0001C188)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONFIG_P0_REG

#define MC1_CH0_CR_CPGC2_RASTER_REPO_STATUS_REG                        (0x0001C18C)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_STATUS_REG

#define MC1_CH0_CR_CPGC_DPAT_CFG_REG                                   (0x0001C190)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_CFG_REG

#define MC1_CH0_CR_CPGC_DPAT_INVDC_CFG_REG                             (0x0001C194)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_INVDC_CFG_REG

#define MC1_CH0_CR_CPGC_DPAT_BUF_CFG_REG                               (0x0001C198)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_BUF_CFG_REG

#define MC1_CH0_CR_CPGC_DPAT_ALT_BUF_CFG_REG                           (0x0001C19C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_ALT_BUF_CFG_REG

#define MC1_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG                             (0x0001C1A0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG

#define MC1_CH0_CR_CPGC_DPAT_USQ_CFG_1_REG                             (0x0001C1A1)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG

#define MC1_CH0_CR_CPGC_DPAT_USQ_CFG_2_REG                             (0x0001C1A2)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_0_REG                              (0x0001C1A8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_1_REG                              (0x0001C1AC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_2_REG                              (0x0001C1B0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG                         (0x0001C1B8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_POLY_1_REG                         (0x0001C1BC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_POLY_2_REG                         (0x0001C1C0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG                        (0x0001C1C8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_1_REG                        (0x0001C1CC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_2_REG                        (0x0001C1D0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG                          (0x0001C1D8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_LMN_1_REG                          (0x0001C1DC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_LMN_2_REG                          (0x0001C1E0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG

#define MC1_CH0_CR_CPGC_DPAT_INV_DC_MASK_LO_REG                        (0x0001C1E8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_INV_DC_MASK_LO_REG

#define MC1_CH0_CR_CPGC_DPAT_INV_DC_MASK_HI_REG                        (0x0001C1EC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_INV_DC_MASK_HI_REG

#define MC1_CH0_CR_CPGC_DPAT_DRAMDM_REG                                (0x0001C1F0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_DRAMDM_REG

#define MC1_CH0_CR_CPGC_DPAT_XDRAMDM_REG                               (0x0001C1F4)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_XDRAMDM_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG                       (0x0001C1F8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_1_REG                       (0x0001C1FC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_2_REG                       (0x0001C200)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG                       (0x0001C208)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_1_REG                       (0x0001C20C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_2_REG                       (0x0001C210)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG

#define MC1_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG                          (0x0001C218)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG

#define MC1_CH0_CR_CPGC_DPAT_LMN_WRSTAT_1_REG                          (0x0001C21C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG

#define MC1_CH0_CR_CPGC_DPAT_LMN_WRSTAT_2_REG                          (0x0001C220)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG

#define MC1_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG                          (0x0001C228)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG

#define MC1_CH0_CR_CPGC_DPAT_LMN_RDSTAT_1_REG                          (0x0001C22C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG

#define MC1_CH0_CR_CPGC_DPAT_LMN_RDSTAT_2_REG                          (0x0001C230)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG                       (0x0001C238)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_1_REG                       (0x0001C23C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_2_REG                       (0x0001C240)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_RDSAVE_0_REG                       (0x0001C248)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_RDSAVE_1_REG                       (0x0001C24C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_RDSAVE_2_REG                       (0x0001C250)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH0_CR_CPGC_ERR_LNEN_LO_REG                                (0x0001C258)
//Duplicate of MC0_CH0_CR_CPGC_ERR_LNEN_LO_REG

#define MC1_CH0_CR_CPGC_ERR_LNEN_HI_REG                                (0x0001C25C)
//Duplicate of MC0_CH0_CR_CPGC_ERR_LNEN_HI_REG

#define MC1_CH0_CR_CPGC_ERR_XLNEN_REG                                  (0x0001C260)
//Duplicate of MC0_CH0_CR_CPGC_ERR_XLNEN_REG

#define MC1_CH0_CR_CPGC_ERR_CTL_REG                                    (0x0001C264)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CTL_REG

#define MC1_CH0_CR_CPGC_ERR_STAT03_REG                                 (0x0001C268)
//Duplicate of MC0_CH0_CR_CPGC_ERR_STAT03_REG

#define MC1_CH0_CR_CPGC_ERR_STAT47_REG                                 (0x0001C26C)
//Duplicate of MC0_CH0_CR_CPGC_ERR_STAT47_REG

#define MC1_CH0_CR_CPGC_ERR_ECC_CHNK_RANK_STAT_REG                     (0x0001C270)
//Duplicate of MC0_CH0_CR_CPGC_ERR_ECC_CHNK_RANK_STAT_REG

#define MC1_CH0_CR_CPGC_ERR_BYTE_NTH_PAR_STAT_REG                      (0x0001C274)
//Duplicate of MC0_CH0_CR_CPGC_ERR_BYTE_NTH_PAR_STAT_REG

#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_0_REG                              (0x0001C278)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_1_REG                              (0x0001C27C)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_2_REG                              (0x0001C280)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_3_REG                              (0x0001C284)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_4_REG                              (0x0001C288)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_5_REG                              (0x0001C28C)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_6_REG                              (0x0001C290)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_7_REG                              (0x0001C294)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_8_REG                              (0x0001C298)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTR_0_REG                                 (0x0001C2A0)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTR_1_REG                                 (0x0001C2A4)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTR_2_REG                                 (0x0001C2A8)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTR_3_REG                                 (0x0001C2AC)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTR_4_REG                                 (0x0001C2B0)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTR_5_REG                                 (0x0001C2B4)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTR_6_REG                                 (0x0001C2B8)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTR_7_REG                                 (0x0001C2BC)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTR_8_REG                                 (0x0001C2C0)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH0_CR_CPGC_ERR_CNTR_OV_REG                                (0x0001C2C8)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_OV_REG

#define MC1_CH0_CR_CPGC_ERR_TEST_ERR_STAT_REG                          (0x0001C2CC)
//Duplicate of MC0_CH0_CR_CPGC_ERR_TEST_ERR_STAT_REG

#define MC1_BUF0_CPGC_DPAT_EXTBUF_0_REG                                (0x0001C2D0)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF0_CPGC_DPAT_EXTBUF_1_REG                                (0x0001C2D4)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF0_CPGC_DPAT_EXTBUF_2_REG                                (0x0001C2D8)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF0_CPGC_DPAT_EXTBUF_3_REG                                (0x0001C2DC)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF0_CPGC_DPAT_EXTBUF_4_REG                                (0x0001C2E0)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF0_CPGC_DPAT_EXTBUF_5_REG                                (0x0001C2E4)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF0_CPGC_DPAT_EXTBUF_6_REG                                (0x0001C2E8)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF0_CPGC_DPAT_EXTBUF_7_REG                                (0x0001C2EC)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF0_CPGC_DPAT_EXTBUF_8_REG                                (0x0001C2F0)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF0_CPGC_DPAT_EXTBUF_9_REG                                (0x0001C2F4)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF0_CPGC_DPAT_EXTBUF_10_REG                               (0x0001C2F8)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF0_CPGC_DPAT_EXTBUF_11_REG                               (0x0001C2FC)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF0_CPGC_DPAT_EXTBUF_12_REG                               (0x0001C300)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF0_CPGC_DPAT_EXTBUF_13_REG                               (0x0001C304)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF0_CPGC_DPAT_EXTBUF_14_REG                               (0x0001C308)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF0_CPGC_DPAT_EXTBUF_15_REG                               (0x0001C30C)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF0_CPGC_B_DUMMY_REG                                      (0x0001C310)
//Duplicate of MC0_BUF0_CPGC_B_DUMMY_REG

#define MC1_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_A_REG                    (0x0001C320)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_A_REG

#define MC1_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_B_REG                    (0x0001C324)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_B_REG

#define MC1_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_C_REG                    (0x0001C328)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_C_REG

#define MC1_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_D_REG                    (0x0001C32C)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_D_REG

#define MC1_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_E_REG                    (0x0001C330)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_E_REG

#define MC1_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_F_REG                    (0x0001C334)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_F_REG

#define MC1_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_A_REG                    (0x0001C338)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_A_REG

#define MC1_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_B_REG                    (0x0001C33C)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_B_REG

#define MC1_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_C_REG                    (0x0001C340)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_C_REG

#define MC1_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_D_REG                    (0x0001C344)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_D_REG

#define MC1_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_E_REG                    (0x0001C348)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_E_REG

#define MC1_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_F_REG                    (0x0001C34C)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_F_REG

#define MC1_REQ0_CR_CPGC_SEQ_RANK_ADDR_SWIZZLE_REG                     (0x0001C350)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_ADDR_SWIZZLE_REG

#define MC1_REQ0_CR_CPGC_SEQ_BANK_ADDR_SWIZZLE_REG                     (0x0001C354)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_ADDR_SWIZZLE_REG

#define MC1_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_A_REG                    (0x0001C358)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_A_REG

#define MC1_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_B_REG                    (0x0001C35C)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_B_REG

#define MC1_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_C_REG                    (0x0001C360)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_C_REG

#define MC1_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_X_REG                    (0x0001C364)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_X_REG

#define MC1_REQ0_CR_CPGC_SEQ_COL_ADDR_SWIZZLE_A_REG                    (0x0001C368)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_COL_ADDR_SWIZZLE_A_REG

#define MC1_REQ0_CR_CPGC_SEQ_COL_ADDR_SWIZZLE_B_REG                    (0x0001C36C)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_COL_ADDR_SWIZZLE_B_REG

#define MC1_REQ0_CR_CPGC_SEQ_ROW_ADDR_DQ_MAP0_REG                      (0x0001C370)
//Duplicate of CAMARILLO_MAILBOX_DATA0_PCU_REG

#define MC1_REQ0_CR_CPGC_SEQ_ROW_ADDR_DQ_MAP1_REG                      (0x0001C374)
//Duplicate of CAMARILLO_MAILBOX_DATA0_PCU_REG

#define MC1_REQ0_CR_CPGC_A_DUMMY_REG                                   (0x0001C378)
//Duplicate of MC0_BUF0_CPGC_B_DUMMY_REG

#define MC1_REQ1_CR_CPGC2_ADDRESS_CONTROL_REG                          (0x0001C430)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_CONTROL_REG

#define MC1_REQ1_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG                    (0x0001C434)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_ADDRESS_INSTRUCTION_1_REG                    (0x0001C435)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_ADDRESS_INSTRUCTION_2_REG                    (0x0001C436)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_ADDRESS_INSTRUCTION_3_REG                    (0x0001C437)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_DATA_CONTROL_REG                             (0x0001C438)
//Duplicate of MC0_REQ0_CR_CPGC2_DATA_CONTROL_REG

#define MC1_REQ1_CR_CPGC2_DATA_INSTRUCTION_0_REG                       (0x0001C43C)
//Duplicate of MC0_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_DATA_INSTRUCTION_1_REG                       (0x0001C43D)
//Duplicate of MC0_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_DATA_INSTRUCTION_2_REG                       (0x0001C43E)
//Duplicate of MC0_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_DATA_INSTRUCTION_3_REG                       (0x0001C43F)
//Duplicate of MC0_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_ADDRESS_DATA_STATUS_REG                      (0x0001C440)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_DATA_STATUS_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG                  (0x0001C444)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_1_REG                  (0x0001C445)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_2_REG                  (0x0001C446)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_3_REG                  (0x0001C447)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_4_REG                  (0x0001C448)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_5_REG                  (0x0001C449)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_6_REG                  (0x0001C44A)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_7_REG                  (0x0001C44B)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG             (0x0001C44C)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_1_REG             (0x0001C44D)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_2_REG             (0x0001C44E)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_3_REG             (0x0001C44F)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_4_REG             (0x0001C450)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_5_REG             (0x0001C451)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_6_REG             (0x0001C452)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_7_REG             (0x0001C453)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_WAIT_COUNT_CURRENT_REG             (0x0001C454)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_WAIT_COUNT_CURRENT_REG

#define MC1_REQ1_CR_CPGC2_ALGORITHM_WAIT_EVENT_CONTROL_REG             (0x0001C458)
//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_WAIT_EVENT_CONTROL_REG

#define MC1_REQ1_CR_CPGC2_BASE_REPEATS_REG                             (0x0001C45C)
//Duplicate of MC0_REQ0_CR_CPGC2_BASE_REPEATS_REG

#define MC1_REQ1_CR_CPGC2_BASE_REPEATS_CURRENT_REG                     (0x0001C460)
//Duplicate of MC0_REQ0_CR_CPGC2_BASE_REPEATS_CURRENT_REG

#define MC1_REQ1_CR_CPGC2_BASE_COL_REPEATS_REG                         (0x0001C464)
//Duplicate of MC0_REQ0_CR_CPGC2_BASE_COL_REPEATS_REG

#define MC1_REQ1_CR_CPGC2_BLOCK_REPEATS_REG                            (0x0001C468)
//Duplicate of MC0_REQ0_CR_CPGC2_BLOCK_REPEATS_REG

#define MC1_REQ1_CR_CPGC2_BLOCK_REPEATS_CURRENT_REG                    (0x0001C46C)
//Duplicate of MC0_REQ0_CR_CPGC2_BLOCK_REPEATS_CURRENT_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_0_REG                    (0x0001C470)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_1_REG                    (0x0001C471)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_2_REG                    (0x0001C472)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_3_REG                    (0x0001C473)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_4_REG                    (0x0001C474)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_5_REG                    (0x0001C475)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_6_REG                    (0x0001C476)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_7_REG                    (0x0001C477)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_8_REG                    (0x0001C478)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_9_REG                    (0x0001C479)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_10_REG                   (0x0001C47A)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_11_REG                   (0x0001C47B)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_12_REG                   (0x0001C47C)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_13_REG                   (0x0001C47D)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_14_REG                   (0x0001C47E)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_15_REG                   (0x0001C47F)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_16_REG                   (0x0001C480)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_17_REG                   (0x0001C481)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_18_REG                   (0x0001C482)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_19_REG                   (0x0001C483)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_20_REG                   (0x0001C484)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_21_REG                   (0x0001C485)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_22_REG                   (0x0001C486)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_23_REG                   (0x0001C487)
//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_HAMMER_REPEATS_REG                           (0x0001C488)
//Duplicate of MC0_REQ0_CR_CPGC2_HAMMER_REPEATS_REG

#define MC1_REQ1_CR_CPGC2_HAMMER_REPEATS_CURRENT_REG                   (0x0001C48C)
//Duplicate of MC0_REQ0_CR_CPGC2_HAMMER_REPEATS_CURRENT_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG             (0x0001C490)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_1_REG             (0x0001C491)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_2_REG             (0x0001C492)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_3_REG             (0x0001C493)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_4_REG             (0x0001C494)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_5_REG             (0x0001C495)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_6_REG             (0x0001C496)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_7_REG             (0x0001C497)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_8_REG             (0x0001C498)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_9_REG             (0x0001C499)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_10_REG            (0x0001C49A)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_11_REG            (0x0001C49B)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_12_REG            (0x0001C49C)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_13_REG            (0x0001C49D)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_14_REG            (0x0001C49E)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_15_REG            (0x0001C49F)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG             (0x0001C4A0)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_1_REG             (0x0001C4A1)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_2_REG             (0x0001C4A2)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_3_REG             (0x0001C4A3)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_4_REG             (0x0001C4A4)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_5_REG             (0x0001C4A5)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_6_REG             (0x0001C4A6)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_7_REG             (0x0001C4A7)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_8_REG             (0x0001C4A8)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_9_REG             (0x0001C4A9)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_10_REG            (0x0001C4AA)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_11_REG            (0x0001C4AB)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_REPEATS_CURRENT_REG                   (0x0001C4AC)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_REPEATS_CURRENT_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_REPEATS_0_REG                         (0x0001C4B0)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_REPEATS_0_REG

#define MC1_REQ1_CR_CPGC2_OFFSET_REPEATS_1_REG                         (0x0001C4B4)
//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_REPEATS_0_REG

#define MC1_REQ1_CR_CPGC2_REGION_LOW_REG                               (0x0001C4B8)
//Duplicate of MC0_REQ0_CR_CPGC2_REGION_LOW_REG

#define MC1_REQ1_CR_CPGC2_ADDRESS_SIZE_REG                             (0x0001C4D8)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_SIZE_REG

#define MC1_REQ1_CR_CPGC2_BASE_ADDRESS_CONTROL_REG                     (0x0001C4E0)
//Duplicate of MC0_REQ0_CR_CPGC2_BASE_ADDRESS_CONTROL_REG

#define MC1_REQ1_CR_CPGC2_ADDRESS_PRBS_SEED_REG                        (0x0001C4E8)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_PRBS_SEED_REG

#define MC1_REQ1_CR_CPGC2_ADDRESS_PRBS_CURRENT_REG                     (0x0001C4F0)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_PRBS_CURRENT_REG

#define MC1_REQ1_CR_CPGC2_ADDRESS_PRBS_SAVE_REG                        (0x0001C4F8)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_PRBS_SAVE_REG

#define MC1_REQ1_CR_CPGC2_ADDRESS_PRBS_POLY_REG                        (0x0001C500)
//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_PRBS_POLY_REG

#define MC1_REQ1_CR_CPGC2_BASE_CLOCK_CONFIG_REG                        (0x0001C508)
//Duplicate of MC0_REQ0_CR_CPGC2_BASE_CLOCK_CONFIG_REG

#define MC1_REQ1_CR_CPGC2_CMD_FSM_CURRENT_REG                          (0x0001C50C)
//Duplicate of MC0_REQ0_CR_CPGC2_CMD_FSM_CURRENT_REG

#define MC1_REQ1_CR_CPGC_SEQ_CFG_A_REG                                 (0x0001C510)
//Duplicate of MC0_REQ1_CR_CPGC_SEQ_CFG_A_REG

#define MC1_REQ1_CR_CPGC_SEQ_CFG_B_REG                                 (0x0001C514)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_CFG_B_REG

#define MC1_REQ1_CR_CPGC_SEQ_CTL_REG                                   (0x0001C518)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_CTL_REG

#define MC1_REQ1_CR_CPGC_SEQ_STATUS_REG                                (0x0001C51C)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_STATUS_REG

#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_0_REG                     (0x0001C520)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_1_REG                     (0x0001C528)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_2_REG                     (0x0001C530)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_3_REG                     (0x0001C538)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_4_REG                     (0x0001C540)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_5_REG                     (0x0001C548)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_6_REG                     (0x0001C550)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_7_REG                     (0x0001C558)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_ECC_0_REG                 (0x0001C560)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_ECC_1_REG                 (0x0001C568)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH1_CR_CPGC2_READ_COMMAND_COUNT_CURRENT_REG                (0x0001C570)
//Duplicate of MC0_CH0_CR_CPGC2_READ_COMMAND_COUNT_CURRENT_REG

#define MC1_CH1_CR_CPGC2_MASK_ERRS_FIRST_N_READS_REG                   (0x0001C574)
//Duplicate of MC0_CH0_CR_CPGC2_MASK_ERRS_FIRST_N_READS_REG

#define MC1_CH1_CR_CPGC2_ERR_SUMMARY_A_REG                             (0x0001C578)
//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_A_REG

#define MC1_CH1_CR_CPGC2_ERR_SUMMARY_B_REG                             (0x0001C57C)
//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_A_REG

#define MC1_CH1_CR_CPGC2_ERR_SUMMARY_C_REG                             (0x0001C580)
//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_C_REG

#define MC1_CH1_CR_CPGC2_RASTER_MODE3_MAX_REG                          (0x0001C584)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_MODE3_MAX_REG

#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONFIG_REG                        (0x0001C588)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONFIG_REG

#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONFIG_P0_REG                     (0x0001C588)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONFIG_P0_REG

#define MC1_CH1_CR_CPGC2_RASTER_REPO_STATUS_REG                        (0x0001C58C)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_STATUS_REG

#define MC1_CH1_CR_CPGC_DPAT_CFG_REG                                   (0x0001C590)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_CFG_REG

#define MC1_CH1_CR_CPGC_DPAT_INVDC_CFG_REG                             (0x0001C594)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_INVDC_CFG_REG

#define MC1_CH1_CR_CPGC_DPAT_BUF_CFG_REG                               (0x0001C598)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_BUF_CFG_REG

#define MC1_CH1_CR_CPGC_DPAT_ALT_BUF_CFG_REG                           (0x0001C59C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_ALT_BUF_CFG_REG

#define MC1_CH1_CR_CPGC_DPAT_USQ_CFG_0_REG                             (0x0001C5A0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG

#define MC1_CH1_CR_CPGC_DPAT_USQ_CFG_1_REG                             (0x0001C5A1)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG

#define MC1_CH1_CR_CPGC_DPAT_USQ_CFG_2_REG                             (0x0001C5A2)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_0_REG                              (0x0001C5A8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_1_REG                              (0x0001C5AC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_2_REG                              (0x0001C5B0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_POLY_0_REG                         (0x0001C5B8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_POLY_1_REG                         (0x0001C5BC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_POLY_2_REG                         (0x0001C5C0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG                        (0x0001C5C8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_STAGR_1_REG                        (0x0001C5CC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_STAGR_2_REG                        (0x0001C5D0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_LMN_0_REG                          (0x0001C5D8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_LMN_1_REG                          (0x0001C5DC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_LMN_2_REG                          (0x0001C5E0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG

#define MC1_CH1_CR_CPGC_DPAT_INV_DC_MASK_LO_REG                        (0x0001C5E8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_INV_DC_MASK_LO_REG

#define MC1_CH1_CR_CPGC_DPAT_INV_DC_MASK_HI_REG                        (0x0001C5EC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_INV_DC_MASK_HI_REG

#define MC1_CH1_CR_CPGC_DPAT_DRAMDM_REG                                (0x0001C5F0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_DRAMDM_REG

#define MC1_CH1_CR_CPGC_DPAT_XDRAMDM_REG                               (0x0001C5F4)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_XDRAMDM_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG                       (0x0001C5F8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_WRSTAT_1_REG                       (0x0001C5FC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_WRSTAT_2_REG                       (0x0001C600)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG                       (0x0001C608)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_RDSTAT_1_REG                       (0x0001C60C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_RDSTAT_2_REG                       (0x0001C610)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG

#define MC1_CH1_CR_CPGC_DPAT_LMN_WRSTAT_0_REG                          (0x0001C618)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG

#define MC1_CH1_CR_CPGC_DPAT_LMN_WRSTAT_1_REG                          (0x0001C61C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG

#define MC1_CH1_CR_CPGC_DPAT_LMN_WRSTAT_2_REG                          (0x0001C620)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG

#define MC1_CH1_CR_CPGC_DPAT_LMN_RDSTAT_0_REG                          (0x0001C628)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG

#define MC1_CH1_CR_CPGC_DPAT_LMN_RDSTAT_1_REG                          (0x0001C62C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG

#define MC1_CH1_CR_CPGC_DPAT_LMN_RDSTAT_2_REG                          (0x0001C630)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG                       (0x0001C638)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_WRSAVE_1_REG                       (0x0001C63C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_WRSAVE_2_REG                       (0x0001C640)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_RDSAVE_0_REG                       (0x0001C648)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_RDSAVE_1_REG                       (0x0001C64C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_RDSAVE_2_REG                       (0x0001C650)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH1_CR_CPGC_ERR_LNEN_LO_REG                                (0x0001C658)
//Duplicate of MC0_CH0_CR_CPGC_ERR_LNEN_LO_REG

#define MC1_CH1_CR_CPGC_ERR_LNEN_HI_REG                                (0x0001C65C)
//Duplicate of MC0_CH0_CR_CPGC_ERR_LNEN_HI_REG

#define MC1_CH1_CR_CPGC_ERR_XLNEN_REG                                  (0x0001C660)
//Duplicate of MC0_CH0_CR_CPGC_ERR_XLNEN_REG

#define MC1_CH1_CR_CPGC_ERR_CTL_REG                                    (0x0001C664)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CTL_REG

#define MC1_CH1_CR_CPGC_ERR_STAT03_REG                                 (0x0001C668)
//Duplicate of MC0_CH0_CR_CPGC_ERR_STAT03_REG

#define MC1_CH1_CR_CPGC_ERR_STAT47_REG                                 (0x0001C66C)
//Duplicate of MC0_CH0_CR_CPGC_ERR_STAT47_REG

#define MC1_CH1_CR_CPGC_ERR_ECC_CHNK_RANK_STAT_REG                     (0x0001C670)
//Duplicate of MC0_CH0_CR_CPGC_ERR_ECC_CHNK_RANK_STAT_REG

#define MC1_CH1_CR_CPGC_ERR_BYTE_NTH_PAR_STAT_REG                      (0x0001C674)
//Duplicate of MC0_CH0_CR_CPGC_ERR_BYTE_NTH_PAR_STAT_REG

#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_0_REG                              (0x0001C678)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_1_REG                              (0x0001C67C)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_2_REG                              (0x0001C680)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_3_REG                              (0x0001C684)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_4_REG                              (0x0001C688)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_5_REG                              (0x0001C68C)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_6_REG                              (0x0001C690)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_7_REG                              (0x0001C694)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_8_REG                              (0x0001C698)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTR_0_REG                                 (0x0001C6A0)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTR_1_REG                                 (0x0001C6A4)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTR_2_REG                                 (0x0001C6A8)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTR_3_REG                                 (0x0001C6AC)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTR_4_REG                                 (0x0001C6B0)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTR_5_REG                                 (0x0001C6B4)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTR_6_REG                                 (0x0001C6B8)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTR_7_REG                                 (0x0001C6BC)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTR_8_REG                                 (0x0001C6C0)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH1_CR_CPGC_ERR_CNTR_OV_REG                                (0x0001C6C8)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_OV_REG

#define MC1_CH1_CR_CPGC_ERR_TEST_ERR_STAT_REG                          (0x0001C6CC)
//Duplicate of MC0_CH0_CR_CPGC_ERR_TEST_ERR_STAT_REG

#define MC1_BUF1_CPGC_DPAT_EXTBUF_0_REG                                (0x0001C6D0)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF1_CPGC_DPAT_EXTBUF_1_REG                                (0x0001C6D4)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF1_CPGC_DPAT_EXTBUF_2_REG                                (0x0001C6D8)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF1_CPGC_DPAT_EXTBUF_3_REG                                (0x0001C6DC)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF1_CPGC_DPAT_EXTBUF_4_REG                                (0x0001C6E0)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF1_CPGC_DPAT_EXTBUF_5_REG                                (0x0001C6E4)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF1_CPGC_DPAT_EXTBUF_6_REG                                (0x0001C6E8)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF1_CPGC_DPAT_EXTBUF_7_REG                                (0x0001C6EC)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF1_CPGC_DPAT_EXTBUF_8_REG                                (0x0001C6F0)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF1_CPGC_DPAT_EXTBUF_9_REG                                (0x0001C6F4)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF1_CPGC_DPAT_EXTBUF_10_REG                               (0x0001C6F8)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF1_CPGC_DPAT_EXTBUF_11_REG                               (0x0001C6FC)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF1_CPGC_DPAT_EXTBUF_12_REG                               (0x0001C700)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF1_CPGC_DPAT_EXTBUF_13_REG                               (0x0001C704)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF1_CPGC_DPAT_EXTBUF_14_REG                               (0x0001C708)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF1_CPGC_DPAT_EXTBUF_15_REG                               (0x0001C70C)
//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG

#define MC1_BUF1_CPGC_B_DUMMY_REG                                      (0x0001C710)
//Duplicate of MC0_BUF0_CPGC_B_DUMMY_REG

#define MC1_REQ1_CR_CPGC_SEQ_RANK_L2P_MAPPING_A_REG                    (0x0001C720)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_A_REG

#define MC1_REQ1_CR_CPGC_SEQ_RANK_L2P_MAPPING_B_REG                    (0x0001C724)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_B_REG

#define MC1_REQ1_CR_CPGC_SEQ_RANK_L2P_MAPPING_C_REG                    (0x0001C728)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_C_REG

#define MC1_REQ1_CR_CPGC_SEQ_RANK_L2P_MAPPING_D_REG                    (0x0001C72C)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_D_REG

#define MC1_REQ1_CR_CPGC_SEQ_RANK_L2P_MAPPING_E_REG                    (0x0001C730)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_E_REG

#define MC1_REQ1_CR_CPGC_SEQ_RANK_L2P_MAPPING_F_REG                    (0x0001C734)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_F_REG

#define MC1_REQ1_CR_CPGC_SEQ_BANK_L2P_MAPPING_A_REG                    (0x0001C738)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_A_REG

#define MC1_REQ1_CR_CPGC_SEQ_BANK_L2P_MAPPING_B_REG                    (0x0001C73C)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_B_REG

#define MC1_REQ1_CR_CPGC_SEQ_BANK_L2P_MAPPING_C_REG                    (0x0001C740)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_C_REG

#define MC1_REQ1_CR_CPGC_SEQ_BANK_L2P_MAPPING_D_REG                    (0x0001C744)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_D_REG

#define MC1_REQ1_CR_CPGC_SEQ_BANK_L2P_MAPPING_E_REG                    (0x0001C748)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_E_REG

#define MC1_REQ1_CR_CPGC_SEQ_BANK_L2P_MAPPING_F_REG                    (0x0001C74C)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_F_REG

#define MC1_REQ1_CR_CPGC_SEQ_RANK_ADDR_SWIZZLE_REG                     (0x0001C750)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_ADDR_SWIZZLE_REG

#define MC1_REQ1_CR_CPGC_SEQ_BANK_ADDR_SWIZZLE_REG                     (0x0001C754)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_ADDR_SWIZZLE_REG

#define MC1_REQ1_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_A_REG                    (0x0001C758)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_A_REG

#define MC1_REQ1_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_B_REG                    (0x0001C75C)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_B_REG

#define MC1_REQ1_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_C_REG                    (0x0001C760)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_C_REG

#define MC1_REQ1_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_X_REG                    (0x0001C764)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_X_REG

#define MC1_REQ1_CR_CPGC_SEQ_COL_ADDR_SWIZZLE_A_REG                    (0x0001C768)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_COL_ADDR_SWIZZLE_A_REG

#define MC1_REQ1_CR_CPGC_SEQ_COL_ADDR_SWIZZLE_B_REG                    (0x0001C76C)
//Duplicate of MC0_REQ0_CR_CPGC_SEQ_COL_ADDR_SWIZZLE_B_REG

#define MC1_REQ1_CR_CPGC_SEQ_ROW_ADDR_DQ_MAP0_REG                      (0x0001C770)
//Duplicate of CAMARILLO_MAILBOX_DATA0_PCU_REG

#define MC1_REQ1_CR_CPGC_SEQ_ROW_ADDR_DQ_MAP1_REG                      (0x0001C774)
//Duplicate of CAMARILLO_MAILBOX_DATA0_PCU_REG

#define MC1_REQ1_CR_CPGC_A_DUMMY_REG                                   (0x0001C778)
//Duplicate of MC0_BUF0_CPGC_B_DUMMY_REG

#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_0_REG                     (0x0001C920)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_1_REG                     (0x0001C928)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_2_REG                     (0x0001C930)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_3_REG                     (0x0001C938)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_4_REG                     (0x0001C940)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_5_REG                     (0x0001C948)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_6_REG                     (0x0001C950)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_7_REG                     (0x0001C958)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_ECC_0_REG                 (0x0001C960)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_ECC_1_REG                 (0x0001C968)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH2_CR_CPGC2_READ_COMMAND_COUNT_CURRENT_REG                (0x0001C970)
//Duplicate of MC0_CH0_CR_CPGC2_READ_COMMAND_COUNT_CURRENT_REG

#define MC1_CH2_CR_CPGC2_MASK_ERRS_FIRST_N_READS_REG                   (0x0001C974)
//Duplicate of MC0_CH0_CR_CPGC2_MASK_ERRS_FIRST_N_READS_REG

#define MC1_CH2_CR_CPGC2_ERR_SUMMARY_A_REG                             (0x0001C978)
//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_A_REG

#define MC1_CH2_CR_CPGC2_ERR_SUMMARY_B_REG                             (0x0001C97C)
//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_A_REG

#define MC1_CH2_CR_CPGC2_ERR_SUMMARY_C_REG                             (0x0001C980)
//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_C_REG

#define MC1_CH2_CR_CPGC2_RASTER_MODE3_MAX_REG                          (0x0001C984)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_MODE3_MAX_REG

#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONFIG_REG                        (0x0001C988)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONFIG_REG

#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONFIG_P0_REG                     (0x0001C988)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONFIG_P0_REG

#define MC1_CH2_CR_CPGC2_RASTER_REPO_STATUS_REG                        (0x0001C98C)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_STATUS_REG

#define MC1_CH2_CR_CPGC_DPAT_CFG_REG                                   (0x0001C990)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_CFG_REG

#define MC1_CH2_CR_CPGC_DPAT_INVDC_CFG_REG                             (0x0001C994)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_INVDC_CFG_REG

#define MC1_CH2_CR_CPGC_DPAT_BUF_CFG_REG                               (0x0001C998)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_BUF_CFG_REG

#define MC1_CH2_CR_CPGC_DPAT_ALT_BUF_CFG_REG                           (0x0001C99C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_ALT_BUF_CFG_REG

#define MC1_CH2_CR_CPGC_DPAT_USQ_CFG_0_REG                             (0x0001C9A0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG

#define MC1_CH2_CR_CPGC_DPAT_USQ_CFG_1_REG                             (0x0001C9A1)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG

#define MC1_CH2_CR_CPGC_DPAT_USQ_CFG_2_REG                             (0x0001C9A2)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_0_REG                              (0x0001C9A8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_1_REG                              (0x0001C9AC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_2_REG                              (0x0001C9B0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_POLY_0_REG                         (0x0001C9B8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_POLY_1_REG                         (0x0001C9BC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_POLY_2_REG                         (0x0001C9C0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG                        (0x0001C9C8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_STAGR_1_REG                        (0x0001C9CC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_STAGR_2_REG                        (0x0001C9D0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_LMN_0_REG                          (0x0001C9D8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_LMN_1_REG                          (0x0001C9DC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_LMN_2_REG                          (0x0001C9E0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG

#define MC1_CH2_CR_CPGC_DPAT_INV_DC_MASK_LO_REG                        (0x0001C9E8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_INV_DC_MASK_LO_REG

#define MC1_CH2_CR_CPGC_DPAT_INV_DC_MASK_HI_REG                        (0x0001C9EC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_INV_DC_MASK_HI_REG

#define MC1_CH2_CR_CPGC_DPAT_DRAMDM_REG                                (0x0001C9F0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_DRAMDM_REG

#define MC1_CH2_CR_CPGC_DPAT_XDRAMDM_REG                               (0x0001C9F4)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_XDRAMDM_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG                       (0x0001C9F8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_WRSTAT_1_REG                       (0x0001C9FC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_WRSTAT_2_REG                       (0x0001CA00)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG                       (0x0001CA08)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_RDSTAT_1_REG                       (0x0001CA0C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_RDSTAT_2_REG                       (0x0001CA10)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG

#define MC1_CH2_CR_CPGC_DPAT_LMN_WRSTAT_0_REG                          (0x0001CA18)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG

#define MC1_CH2_CR_CPGC_DPAT_LMN_WRSTAT_1_REG                          (0x0001CA1C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG

#define MC1_CH2_CR_CPGC_DPAT_LMN_WRSTAT_2_REG                          (0x0001CA20)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG

#define MC1_CH2_CR_CPGC_DPAT_LMN_RDSTAT_0_REG                          (0x0001CA28)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG

#define MC1_CH2_CR_CPGC_DPAT_LMN_RDSTAT_1_REG                          (0x0001CA2C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG

#define MC1_CH2_CR_CPGC_DPAT_LMN_RDSTAT_2_REG                          (0x0001CA30)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG                       (0x0001CA38)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_WRSAVE_1_REG                       (0x0001CA3C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_WRSAVE_2_REG                       (0x0001CA40)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_RDSAVE_0_REG                       (0x0001CA48)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_RDSAVE_1_REG                       (0x0001CA4C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_RDSAVE_2_REG                       (0x0001CA50)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH2_CR_CPGC_ERR_LNEN_LO_REG                                (0x0001CA58)
//Duplicate of MC0_CH0_CR_CPGC_ERR_LNEN_LO_REG

#define MC1_CH2_CR_CPGC_ERR_LNEN_HI_REG                                (0x0001CA5C)
//Duplicate of MC0_CH0_CR_CPGC_ERR_LNEN_HI_REG

#define MC1_CH2_CR_CPGC_ERR_XLNEN_REG                                  (0x0001CA60)
//Duplicate of MC0_CH0_CR_CPGC_ERR_XLNEN_REG

#define MC1_CH2_CR_CPGC_ERR_CTL_REG                                    (0x0001CA64)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CTL_REG

#define MC1_CH2_CR_CPGC_ERR_STAT03_REG                                 (0x0001CA68)
//Duplicate of MC0_CH0_CR_CPGC_ERR_STAT03_REG

#define MC1_CH2_CR_CPGC_ERR_STAT47_REG                                 (0x0001CA6C)
//Duplicate of MC0_CH0_CR_CPGC_ERR_STAT47_REG

#define MC1_CH2_CR_CPGC_ERR_ECC_CHNK_RANK_STAT_REG                     (0x0001CA70)
//Duplicate of MC0_CH0_CR_CPGC_ERR_ECC_CHNK_RANK_STAT_REG

#define MC1_CH2_CR_CPGC_ERR_BYTE_NTH_PAR_STAT_REG                      (0x0001CA74)
//Duplicate of MC0_CH0_CR_CPGC_ERR_BYTE_NTH_PAR_STAT_REG

#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_0_REG                              (0x0001CA78)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_1_REG                              (0x0001CA7C)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_2_REG                              (0x0001CA80)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_3_REG                              (0x0001CA84)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_4_REG                              (0x0001CA88)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_5_REG                              (0x0001CA8C)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_6_REG                              (0x0001CA90)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_7_REG                              (0x0001CA94)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_8_REG                              (0x0001CA98)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTR_0_REG                                 (0x0001CAA0)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTR_1_REG                                 (0x0001CAA4)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTR_2_REG                                 (0x0001CAA8)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTR_3_REG                                 (0x0001CAAC)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTR_4_REG                                 (0x0001CAB0)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTR_5_REG                                 (0x0001CAB4)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTR_6_REG                                 (0x0001CAB8)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTR_7_REG                                 (0x0001CABC)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTR_8_REG                                 (0x0001CAC0)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH2_CR_CPGC_ERR_CNTR_OV_REG                                (0x0001CAC8)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_OV_REG

#define MC1_CH2_CR_CPGC_ERR_TEST_ERR_STAT_REG                          (0x0001CACC)
//Duplicate of MC0_CH0_CR_CPGC_ERR_TEST_ERR_STAT_REG

#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_0_REG                     (0x0001CD20)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_1_REG                     (0x0001CD28)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_2_REG                     (0x0001CD30)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_3_REG                     (0x0001CD38)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_4_REG                     (0x0001CD40)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_5_REG                     (0x0001CD48)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_6_REG                     (0x0001CD50)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_7_REG                     (0x0001CD58)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_ECC_0_REG                 (0x0001CD60)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_ECC_1_REG                 (0x0001CD68)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG

#define MC1_CH3_CR_CPGC2_READ_COMMAND_COUNT_CURRENT_REG                (0x0001CD70)
//Duplicate of MC0_CH0_CR_CPGC2_READ_COMMAND_COUNT_CURRENT_REG

#define MC1_CH3_CR_CPGC2_MASK_ERRS_FIRST_N_READS_REG                   (0x0001CD74)
//Duplicate of MC0_CH0_CR_CPGC2_MASK_ERRS_FIRST_N_READS_REG

#define MC1_CH3_CR_CPGC2_ERR_SUMMARY_A_REG                             (0x0001CD78)
//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_A_REG

#define MC1_CH3_CR_CPGC2_ERR_SUMMARY_B_REG                             (0x0001CD7C)
//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_A_REG

#define MC1_CH3_CR_CPGC2_ERR_SUMMARY_C_REG                             (0x0001CD80)
//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_C_REG

#define MC1_CH3_CR_CPGC2_RASTER_MODE3_MAX_REG                          (0x0001CD84)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_MODE3_MAX_REG

#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONFIG_REG                        (0x0001CD88)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONFIG_REG

#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONFIG_P0_REG                     (0x0001CD88)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONFIG_P0_REG

#define MC1_CH3_CR_CPGC2_RASTER_REPO_STATUS_REG                        (0x0001CD8C)
//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_STATUS_REG

#define MC1_CH3_CR_CPGC_DPAT_CFG_REG                                   (0x0001CD90)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_CFG_REG

#define MC1_CH3_CR_CPGC_DPAT_INVDC_CFG_REG                             (0x0001CD94)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_INVDC_CFG_REG

#define MC1_CH3_CR_CPGC_DPAT_BUF_CFG_REG                               (0x0001CD98)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_BUF_CFG_REG

#define MC1_CH3_CR_CPGC_DPAT_ALT_BUF_CFG_REG                           (0x0001CD9C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_ALT_BUF_CFG_REG

#define MC1_CH3_CR_CPGC_DPAT_USQ_CFG_0_REG                             (0x0001CDA0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG

#define MC1_CH3_CR_CPGC_DPAT_USQ_CFG_1_REG                             (0x0001CDA1)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG

#define MC1_CH3_CR_CPGC_DPAT_USQ_CFG_2_REG                             (0x0001CDA2)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_0_REG                              (0x0001CDA8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_1_REG                              (0x0001CDAC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_2_REG                              (0x0001CDB0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_POLY_0_REG                         (0x0001CDB8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_POLY_1_REG                         (0x0001CDBC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_POLY_2_REG                         (0x0001CDC0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG                        (0x0001CDC8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_STAGR_1_REG                        (0x0001CDCC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_STAGR_2_REG                        (0x0001CDD0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_LMN_0_REG                          (0x0001CDD8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_LMN_1_REG                          (0x0001CDDC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_LMN_2_REG                          (0x0001CDE0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG

#define MC1_CH3_CR_CPGC_DPAT_INV_DC_MASK_LO_REG                        (0x0001CDE8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_INV_DC_MASK_LO_REG

#define MC1_CH3_CR_CPGC_DPAT_INV_DC_MASK_HI_REG                        (0x0001CDEC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_INV_DC_MASK_HI_REG

#define MC1_CH3_CR_CPGC_DPAT_DRAMDM_REG                                (0x0001CDF0)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_DRAMDM_REG

#define MC1_CH3_CR_CPGC_DPAT_XDRAMDM_REG                               (0x0001CDF4)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_XDRAMDM_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG                       (0x0001CDF8)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_WRSTAT_1_REG                       (0x0001CDFC)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_WRSTAT_2_REG                       (0x0001CE00)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG                       (0x0001CE08)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_RDSTAT_1_REG                       (0x0001CE0C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_RDSTAT_2_REG                       (0x0001CE10)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG

#define MC1_CH3_CR_CPGC_DPAT_LMN_WRSTAT_0_REG                          (0x0001CE18)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG

#define MC1_CH3_CR_CPGC_DPAT_LMN_WRSTAT_1_REG                          (0x0001CE1C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG

#define MC1_CH3_CR_CPGC_DPAT_LMN_WRSTAT_2_REG                          (0x0001CE20)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG

#define MC1_CH3_CR_CPGC_DPAT_LMN_RDSTAT_0_REG                          (0x0001CE28)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG

#define MC1_CH3_CR_CPGC_DPAT_LMN_RDSTAT_1_REG                          (0x0001CE2C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG

#define MC1_CH3_CR_CPGC_DPAT_LMN_RDSTAT_2_REG                          (0x0001CE30)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG                       (0x0001CE38)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_WRSAVE_1_REG                       (0x0001CE3C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_WRSAVE_2_REG                       (0x0001CE40)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_RDSAVE_0_REG                       (0x0001CE48)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_RDSAVE_1_REG                       (0x0001CE4C)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_RDSAVE_2_REG                       (0x0001CE50)
//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG

#define MC1_CH3_CR_CPGC_ERR_LNEN_LO_REG                                (0x0001CE58)
//Duplicate of MC0_CH0_CR_CPGC_ERR_LNEN_LO_REG

#define MC1_CH3_CR_CPGC_ERR_LNEN_HI_REG                                (0x0001CE5C)
//Duplicate of MC0_CH0_CR_CPGC_ERR_LNEN_HI_REG

#define MC1_CH3_CR_CPGC_ERR_XLNEN_REG                                  (0x0001CE60)
//Duplicate of MC0_CH0_CR_CPGC_ERR_XLNEN_REG

#define MC1_CH3_CR_CPGC_ERR_CTL_REG                                    (0x0001CE64)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CTL_REG

#define MC1_CH3_CR_CPGC_ERR_STAT03_REG                                 (0x0001CE68)
//Duplicate of MC0_CH0_CR_CPGC_ERR_STAT03_REG

#define MC1_CH3_CR_CPGC_ERR_STAT47_REG                                 (0x0001CE6C)
//Duplicate of MC0_CH0_CR_CPGC_ERR_STAT47_REG

#define MC1_CH3_CR_CPGC_ERR_ECC_CHNK_RANK_STAT_REG                     (0x0001CE70)
//Duplicate of MC0_CH0_CR_CPGC_ERR_ECC_CHNK_RANK_STAT_REG

#define MC1_CH3_CR_CPGC_ERR_BYTE_NTH_PAR_STAT_REG                      (0x0001CE74)
//Duplicate of MC0_CH0_CR_CPGC_ERR_BYTE_NTH_PAR_STAT_REG

#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_0_REG                              (0x0001CE78)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_1_REG                              (0x0001CE7C)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_2_REG                              (0x0001CE80)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_3_REG                              (0x0001CE84)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_4_REG                              (0x0001CE88)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_5_REG                              (0x0001CE8C)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_6_REG                              (0x0001CE90)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_7_REG                              (0x0001CE94)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_8_REG                              (0x0001CE98)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTR_0_REG                                 (0x0001CEA0)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTR_1_REG                                 (0x0001CEA4)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTR_2_REG                                 (0x0001CEA8)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTR_3_REG                                 (0x0001CEAC)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTR_4_REG                                 (0x0001CEB0)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTR_5_REG                                 (0x0001CEB4)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTR_6_REG                                 (0x0001CEB8)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTR_7_REG                                 (0x0001CEBC)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTR_8_REG                                 (0x0001CEC0)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG

#define MC1_CH3_CR_CPGC_ERR_CNTR_OV_REG                                (0x0001CEC8)
//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_OV_REG

#define MC1_CH3_CR_CPGC_ERR_TEST_ERR_STAT_REG                          (0x0001CECC)
//Duplicate of MC0_CH0_CR_CPGC_ERR_TEST_ERR_STAT_REG
#pragma pack(pop)
#endif
