#ifndef __MrcMcRegisterTgl1Dxxx_h__
#define __MrcMcRegisterTgl1Dxxx_h__
/** @file
  This file was automatically generated. Modify at your own risk.
  Note that no error checking is done in these functions so ensure that the correct values are passed.

@copyright
  Copyright (c) 2010 - 2019 Intel Corporation. All rights reserved
  This software and associated documentation (if any) is furnished
  under a license and may only be used or copied in accordance
  with the terms of the license. Except as permitted by the
  license, no part of this software or documentation may be
  reproduced, stored in a retrieval system, or transmitted in any
  form or by any means without the express written consent of
  Intel Corporation.
  This file contains an 'Intel Peripheral Driver' and is uniquely
  identified as "Intel Reference Module" and is licensed for Intel
  CPUs and chipsets under the terms of your license agreement with
  Intel or your vendor. This file may be modified by the user, subject
  to additional terms of the license agreement.

@par Specification Reference:
**/

#pragma pack(push, 1)


#define MC1_CH0_CR_CADB_ACCESS_CONTROL_POLICY_REG                      (0x0001D000)
//Duplicate of MC0_CR_CPGC2_ACCESS_CONTROL_POLICY_REG

#define MC1_CH0_CR_CADB_ACCESS_READ_POLICY_REG                         (0x0001D008)
//Duplicate of MC0_CR_CPGC2_ACCESS_READ_POLICY_REG

#define MC1_CH0_CR_CADB_ACCESS_WRITE_POLICY_REG                        (0x0001D010)
//Duplicate of MC0_CR_CPGC2_ACCESS_WRITE_POLICY_REG

#define MC1_CH0_CR_CADB_CTL_REG                                        (0x0001D020)
//Duplicate of MC0_CH0_CR_CADB_CTL_REG

#define MC1_CH0_CR_CADB_CFG_REG                                        (0x0001D024)
//Duplicate of MC0_CH0_CR_CADB_CFG_REG

#define MC1_CH0_CR_CADB_DLY_REG                                        (0x0001D028)
//Duplicate of MC0_CH0_CR_CADB_DLY_REG

#define MC1_CH0_CR_CADB_STATUS_REG                                     (0x0001D02C)
//Duplicate of MC0_CH0_CR_CADB_STATUS_REG

#define MC1_CH0_CR_CADB_DSEL_UNISEQ_CFG_0_REG                          (0x0001D030)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_CFG_0_REG

#define MC1_CH0_CR_CADB_DSEL_UNISEQ_CFG_1_REG                          (0x0001D031)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_CFG_0_REG

#define MC1_CH0_CR_CADB_DSEL_UNISEQ_CFG_2_REG                          (0x0001D032)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_CFG_0_REG

#define MC1_CH0_CR_CADB_DSEL_UNISEQ_PBUF_0_REG                         (0x0001D034)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_PBUF_0_REG

#define MC1_CH0_CR_CADB_DSEL_UNISEQ_PBUF_1_REG                         (0x0001D038)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_PBUF_0_REG

#define MC1_CH0_CR_CADB_DSEL_UNISEQ_PBUF_2_REG                         (0x0001D03C)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_PBUF_0_REG

#define MC1_CH0_CR_CADB_DSEL_UNISEQ_LMN_REG                            (0x0001D040)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_LMN_REG

#define MC1_CH0_CR_CADB_BUF_0_REG                                      (0x0001D048)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH0_CR_CADB_BUF_1_REG                                      (0x0001D050)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH0_CR_CADB_BUF_2_REG                                      (0x0001D058)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH0_CR_CADB_BUF_3_REG                                      (0x0001D060)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH0_CR_CADB_BUF_4_REG                                      (0x0001D068)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH0_CR_CADB_BUF_5_REG                                      (0x0001D070)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH0_CR_CADB_BUF_6_REG                                      (0x0001D078)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH0_CR_CADB_BUF_7_REG                                      (0x0001D080)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH0_CR_CADB_AO_MRSCFG_REG                                  (0x0001D088)
//Duplicate of MC0_CH0_CR_CADB_AO_MRSCFG_REG

#define MC1_CH0_CR_CADB_SELCFG_REG                                     (0x0001D090)
//Duplicate of MC0_CH0_CR_CADB_SELCFG_REG

#define MC1_CH0_CR_CADB_MRSCFG_REG                                     (0x0001D098)
//Duplicate of MC0_CH0_CR_CADB_MRSCFG_REG

#define MC1_CH1_CR_CADB_ACCESS_CONTROL_POLICY_REG                      (0x0001D100)
//Duplicate of MC0_CR_CPGC2_ACCESS_CONTROL_POLICY_REG

#define MC1_CH1_CR_CADB_ACCESS_READ_POLICY_REG                         (0x0001D108)
//Duplicate of MC0_CR_CPGC2_ACCESS_READ_POLICY_REG

#define MC1_CH1_CR_CADB_ACCESS_WRITE_POLICY_REG                        (0x0001D110)
//Duplicate of MC0_CR_CPGC2_ACCESS_WRITE_POLICY_REG

#define MC1_CH1_CR_CADB_CTL_REG                                        (0x0001D120)
//Duplicate of MC0_CH0_CR_CADB_CTL_REG

#define MC1_CH1_CR_CADB_CFG_REG                                        (0x0001D124)
//Duplicate of MC0_CH0_CR_CADB_CFG_REG

#define MC1_CH1_CR_CADB_DLY_REG                                        (0x0001D128)
//Duplicate of MC0_CH0_CR_CADB_DLY_REG

#define MC1_CH1_CR_CADB_STATUS_REG                                     (0x0001D12C)
//Duplicate of MC0_CH0_CR_CADB_STATUS_REG

#define MC1_CH1_CR_CADB_DSEL_UNISEQ_CFG_0_REG                          (0x0001D130)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_CFG_0_REG

#define MC1_CH1_CR_CADB_DSEL_UNISEQ_CFG_1_REG                          (0x0001D131)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_CFG_0_REG

#define MC1_CH1_CR_CADB_DSEL_UNISEQ_CFG_2_REG                          (0x0001D132)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_CFG_0_REG

#define MC1_CH1_CR_CADB_DSEL_UNISEQ_PBUF_0_REG                         (0x0001D134)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_PBUF_0_REG

#define MC1_CH1_CR_CADB_DSEL_UNISEQ_PBUF_1_REG                         (0x0001D138)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_PBUF_0_REG

#define MC1_CH1_CR_CADB_DSEL_UNISEQ_PBUF_2_REG                         (0x0001D13C)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_PBUF_0_REG

#define MC1_CH1_CR_CADB_DSEL_UNISEQ_LMN_REG                            (0x0001D140)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_LMN_REG

#define MC1_CH1_CR_CADB_BUF_0_REG                                      (0x0001D148)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH1_CR_CADB_BUF_1_REG                                      (0x0001D150)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH1_CR_CADB_BUF_2_REG                                      (0x0001D158)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH1_CR_CADB_BUF_3_REG                                      (0x0001D160)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH1_CR_CADB_BUF_4_REG                                      (0x0001D168)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH1_CR_CADB_BUF_5_REG                                      (0x0001D170)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH1_CR_CADB_BUF_6_REG                                      (0x0001D178)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH1_CR_CADB_BUF_7_REG                                      (0x0001D180)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH1_CR_CADB_AO_MRSCFG_REG                                  (0x0001D188)
//Duplicate of MC0_CH0_CR_CADB_AO_MRSCFG_REG

#define MC1_CH1_CR_CADB_SELCFG_REG                                     (0x0001D190)
//Duplicate of MC0_CH0_CR_CADB_SELCFG_REG

#define MC1_CH1_CR_CADB_MRSCFG_REG                                     (0x0001D198)
//Duplicate of MC0_CH0_CR_CADB_MRSCFG_REG

#define MC1_CH2_CR_CADB_ACCESS_CONTROL_POLICY_REG                      (0x0001D200)
//Duplicate of MC0_CR_CPGC2_ACCESS_CONTROL_POLICY_REG

#define MC1_CH2_CR_CADB_ACCESS_READ_POLICY_REG                         (0x0001D208)
//Duplicate of MC0_CR_CPGC2_ACCESS_READ_POLICY_REG

#define MC1_CH2_CR_CADB_ACCESS_WRITE_POLICY_REG                        (0x0001D210)
//Duplicate of MC0_CR_CPGC2_ACCESS_WRITE_POLICY_REG

#define MC1_CH2_CR_CADB_CTL_REG                                        (0x0001D220)
//Duplicate of MC0_CH0_CR_CADB_CTL_REG

#define MC1_CH2_CR_CADB_CFG_REG                                        (0x0001D224)
//Duplicate of MC0_CH0_CR_CADB_CFG_REG

#define MC1_CH2_CR_CADB_DLY_REG                                        (0x0001D228)
//Duplicate of MC0_CH0_CR_CADB_DLY_REG

#define MC1_CH2_CR_CADB_STATUS_REG                                     (0x0001D22C)
//Duplicate of MC0_CH0_CR_CADB_STATUS_REG

#define MC1_CH2_CR_CADB_DSEL_UNISEQ_CFG_0_REG                          (0x0001D230)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_CFG_0_REG

#define MC1_CH2_CR_CADB_DSEL_UNISEQ_CFG_1_REG                          (0x0001D231)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_CFG_0_REG

#define MC1_CH2_CR_CADB_DSEL_UNISEQ_CFG_2_REG                          (0x0001D232)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_CFG_0_REG

#define MC1_CH2_CR_CADB_DSEL_UNISEQ_PBUF_0_REG                         (0x0001D234)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_PBUF_0_REG

#define MC1_CH2_CR_CADB_DSEL_UNISEQ_PBUF_1_REG                         (0x0001D238)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_PBUF_0_REG

#define MC1_CH2_CR_CADB_DSEL_UNISEQ_PBUF_2_REG                         (0x0001D23C)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_PBUF_0_REG

#define MC1_CH2_CR_CADB_DSEL_UNISEQ_LMN_REG                            (0x0001D240)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_LMN_REG

#define MC1_CH2_CR_CADB_BUF_0_REG                                      (0x0001D248)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH2_CR_CADB_BUF_1_REG                                      (0x0001D250)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH2_CR_CADB_BUF_2_REG                                      (0x0001D258)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH2_CR_CADB_BUF_3_REG                                      (0x0001D260)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH2_CR_CADB_BUF_4_REG                                      (0x0001D268)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH2_CR_CADB_BUF_5_REG                                      (0x0001D270)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH2_CR_CADB_BUF_6_REG                                      (0x0001D278)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH2_CR_CADB_BUF_7_REG                                      (0x0001D280)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH2_CR_CADB_AO_MRSCFG_REG                                  (0x0001D288)
//Duplicate of MC0_CH0_CR_CADB_AO_MRSCFG_REG

#define MC1_CH2_CR_CADB_SELCFG_REG                                     (0x0001D290)
//Duplicate of MC0_CH0_CR_CADB_SELCFG_REG

#define MC1_CH2_CR_CADB_MRSCFG_REG                                     (0x0001D298)
//Duplicate of MC0_CH0_CR_CADB_MRSCFG_REG

#define MC1_CH3_CR_CADB_ACCESS_CONTROL_POLICY_REG                      (0x0001D300)
//Duplicate of MC0_CR_CPGC2_ACCESS_CONTROL_POLICY_REG

#define MC1_CH3_CR_CADB_ACCESS_READ_POLICY_REG                         (0x0001D308)
//Duplicate of MC0_CR_CPGC2_ACCESS_READ_POLICY_REG

#define MC1_CH3_CR_CADB_ACCESS_WRITE_POLICY_REG                        (0x0001D310)
//Duplicate of MC0_CR_CPGC2_ACCESS_WRITE_POLICY_REG

#define MC1_CH3_CR_CADB_CTL_REG                                        (0x0001D320)
//Duplicate of MC0_CH0_CR_CADB_CTL_REG

#define MC1_CH3_CR_CADB_CFG_REG                                        (0x0001D324)
//Duplicate of MC0_CH0_CR_CADB_CFG_REG

#define MC1_CH3_CR_CADB_DLY_REG                                        (0x0001D328)
//Duplicate of MC0_CH0_CR_CADB_DLY_REG

#define MC1_CH3_CR_CADB_STATUS_REG                                     (0x0001D32C)
//Duplicate of MC0_CH0_CR_CADB_STATUS_REG

#define MC1_CH3_CR_CADB_DSEL_UNISEQ_CFG_0_REG                          (0x0001D330)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_CFG_0_REG

#define MC1_CH3_CR_CADB_DSEL_UNISEQ_CFG_1_REG                          (0x0001D331)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_CFG_0_REG

#define MC1_CH3_CR_CADB_DSEL_UNISEQ_CFG_2_REG                          (0x0001D332)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_CFG_0_REG

#define MC1_CH3_CR_CADB_DSEL_UNISEQ_PBUF_0_REG                         (0x0001D334)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_PBUF_0_REG

#define MC1_CH3_CR_CADB_DSEL_UNISEQ_PBUF_1_REG                         (0x0001D338)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_PBUF_0_REG

#define MC1_CH3_CR_CADB_DSEL_UNISEQ_PBUF_2_REG                         (0x0001D33C)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_PBUF_0_REG

#define MC1_CH3_CR_CADB_DSEL_UNISEQ_LMN_REG                            (0x0001D340)
//Duplicate of MC0_CH0_CR_CADB_DSEL_UNISEQ_LMN_REG

#define MC1_CH3_CR_CADB_BUF_0_REG                                      (0x0001D348)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH3_CR_CADB_BUF_1_REG                                      (0x0001D350)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH3_CR_CADB_BUF_2_REG                                      (0x0001D358)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH3_CR_CADB_BUF_3_REG                                      (0x0001D360)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH3_CR_CADB_BUF_4_REG                                      (0x0001D368)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH3_CR_CADB_BUF_5_REG                                      (0x0001D370)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH3_CR_CADB_BUF_6_REG                                      (0x0001D378)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH3_CR_CADB_BUF_7_REG                                      (0x0001D380)
//Duplicate of MC0_CH0_CR_CADB_BUF_0_REG

#define MC1_CH3_CR_CADB_AO_MRSCFG_REG                                  (0x0001D388)
//Duplicate of MC0_CH0_CR_CADB_AO_MRSCFG_REG

#define MC1_CH3_CR_CADB_SELCFG_REG                                     (0x0001D390)
//Duplicate of MC0_CH0_CR_CADB_SELCFG_REG

#define MC1_CH3_CR_CADB_MRSCFG_REG                                     (0x0001D398)
//Duplicate of MC0_CH0_CR_CADB_MRSCFG_REG

#define MC1_MAD_INTER_CHANNEL_P0_REG                                   (0x0001D800)
//Duplicate of MC0_MAD_INTER_CHANNEL_P0_REG

#define MC1_MAD_INTRA_CH0_P0_REG                                       (0x0001D804)
//Duplicate of MC0_MAD_INTRA_CH0_P0_REG

#define MC1_MAD_INTRA_CH1_P0_REG                                       (0x0001D808)
//Duplicate of MC0_MAD_INTRA_CH0_P0_REG

#define MC1_MAD_DIMM_CH0_P0_REG                                        (0x0001D80C)
//Duplicate of MC0_MAD_DIMM_CH0_P0_REG

#define MC1_MAD_DIMM_CH1_P0_REG                                        (0x0001D810)
//Duplicate of MC0_MAD_DIMM_CH0_P0_REG

#define MC1_MCDECS_MISC_P0_REG                                         (0x0001D818)
//Duplicate of MC0_MCDECS_MISC_P0_REG

#define MC1_MCDECS_CBIT_P0_REG                                         (0x0001D81C)
//Duplicate of MC0_MCDECS_CBIT_P0_REG

#define MC1_CHANNEL_HASH_P0_REG                                        (0x0001D824)
//Duplicate of MC0_CHANNEL_HASH_P0_REG

#define MC1_CHANNEL_EHASH_P0_REG                                       (0x0001D828)
//Duplicate of MC0_CHANNEL_EHASH_P0_REG

#define MC1_MC_INIT_STATE_G_P0_REG                                     (0x0001D830)
//Duplicate of MC0_MC_INIT_STATE_G_P0_REG

#define MC1_MRC_REVISION_P0_REG                                        (0x0001D834)
//Duplicate of MC0_MRC_REVISION_P0_REG

#define MC1_PWM_PROGRAMMABLE_REQCOUNT_CONFIG_P0_REG                    (0x0001D83C)
//Duplicate of MC0_PWM_PROGRAMMABLE_REQCOUNT_CONFIG_P0_REG

#define MC1_PWM_TOTAL_REQCOUNT_P0_REG                                  (0x0001D840)
//Duplicate of MC0_PWM_TOTAL_REQCOUNT_P0_REG

#define MC1_PWM_PROGRAMMABLE_REQCOUNT_0_P0_REG                         (0x0001D848)
//Duplicate of MC0_PWM_TOTAL_REQCOUNT_P0_REG

#define MC1_PWM_PROGRAMMABLE_REQCOUNT_1_P0_REG                         (0x0001D850)
//Duplicate of MC0_PWM_TOTAL_REQCOUNT_P0_REG

#define MC1_PWM_RDCAS_COUNT_P0_REG                                     (0x0001D858)
//Duplicate of MC0_PWM_TOTAL_REQCOUNT_P0_REG

#define MC1_PM_SREF_CONFIG_P0_REG                                      (0x0001D860)
//Duplicate of MC0_PM_SREF_CONFIG_P0_REG

#define MC1_ATMC_STS_P0_REG                                            (0x0001D864)
//Duplicate of MC0_ATMC_STS_P0_REG

#define MC1_READ_OCCUPANCY_COUNT_P0_REG                                (0x0001D868)
//Duplicate of MC0_PWM_TOTAL_REQCOUNT_P0_REG

#define MC1_STALL_DRAIN_P0_REG                                         (0x0001D874)
//Duplicate of MC0_STALL_DRAIN_P0_REG

#define MC1_IPC_MC_ARB_P0_REG                                          (0x0001D878)
//Duplicate of MC0_IPC_MC_ARB_P0_REG

#define MC1_IPC_MC_DEC_ARB_P0_REG                                      (0x0001D87C)
//Duplicate of MC0_IPC_MC_ARB_P0_REG

#define MC1_QUEUE_CREDIT_C_P0_REG                                      (0x0001D880)
//Duplicate of MC0_QUEUE_CREDIT_C_P0_REG

#define MC1_ECC_INJ_ADDR_COMPARE_P0_REG                                (0x0001D888)
//Duplicate of MC0_ECC_INJ_ADDR_COMPARE_P0_REG

#define MC1_REMAPBASE_P0_REG                                           (0x0001D890)
//Duplicate of MC0_REMAPBASE_P0_REG

#define MC1_REMAPLIMIT_P0_REG                                          (0x0001D898)
//Duplicate of MC0_REMAPLIMIT_P0_REG

#define MC1_PWM_WRCAS_COUNT_P0_REG                                     (0x0001D8A0)
//Duplicate of MC0_PWM_TOTAL_REQCOUNT_P0_REG

#define MC1_PWM_COMMAND_COUNT_P0_REG                                   (0x0001D8A8)
//Duplicate of MC0_PWM_TOTAL_REQCOUNT_P0_REG

#define MC1_PWM_NON_SR_COUNT_P0_REG                                    (0x0001D8B0)
//Duplicate of MC0_PWM_TOTAL_REQCOUNT_P0_REG

#define MC1_TOLUD_P0_REG                                               (0x0001D8BC)
//Duplicate of MC0_TOLUD_P0_REG

#define MC1_GDXC_DDR_SYS_ADD_FILTER_MASK_0_P0_REG                      (0x0001D900)
//Duplicate of MC0_GDXC_DDR_SYS_ADD_FILTER_MASK_0_P0_REG

#define MC1_GDXC_DDR_SYS_ADD_FILTER_MASK_1_P0_REG                      (0x0001D908)
//Duplicate of MC0_GDXC_DDR_SYS_ADD_FILTER_MASK_0_P0_REG

#define MC1_GDXC_DDR_SYS_ADD_FILTER_MATCH_0_P0_REG                     (0x0001D910)
//Duplicate of MC0_GDXC_DDR_SYS_ADD_FILTER_MASK_0_P0_REG

#define MC1_GDXC_DDR_SYS_ADD_FILTER_MATCH_1_P0_REG                     (0x0001D918)
//Duplicate of MC0_GDXC_DDR_SYS_ADD_FILTER_MASK_0_P0_REG

#define MC1_GDXC_DDR_SYS_ADD_TRIGGER_MASK_P0_REG                       (0x0001D920)
//Duplicate of MC0_GDXC_DDR_SYS_ADD_FILTER_MASK_0_P0_REG

#define MC1_GDXC_DDR_SYS_ADD_TRIGGER_MATCH_P0_REG                      (0x0001D928)
//Duplicate of MC0_GDXC_DDR_SYS_ADD_FILTER_MASK_0_P0_REG

#define MC1_SC_QOS_P0_REG                                              (0x0001D930)
//Duplicate of MC0_SC_QOS_P0_REG

#define MC1_MCMAINS_GLOBAL_DRIVER_GATE_CFG_P0_REG                      (0x0001D938)
//Duplicate of MC0_MCMAINS_GLOBAL_DRIVER_GATE_CFG_P0_REG

#define MC1_PWM_COUNTERS_DURATION_P0_REG                               (0x0001D948)
//Duplicate of MC0_PWM_COUNTERS_DURATION_P0_REG

#define MC1_MCDECS_SECOND_CBIT_P0_REG                                  (0x0001D954)
//Duplicate of MC0_MCDECS_SECOND_CBIT_P0_REG

#define MC1_ECC_INJ_ADDR_MASK_P0_REG                                   (0x0001D958)
//Duplicate of MC0_ECC_INJ_ADDR_MASK_P0_REG

#define MC1_SC_QOS2_P0_REG                                             (0x0001D960)
//Duplicate of MC0_SC_QOS2_P0_REG

#define MC1_SC_QOS3_P0_REG                                             (0x0001D968)
//Duplicate of MC0_SC_QOS3_P0_REG

#define MC1_NORMALMODE_CFG_P0_REG                                      (0x0001D96C)
//Duplicate of MC0_NORMALMODE_CFG_P0_REG

#define MC1_MC_CPGC_CMI_P0_REG                                         (0x0001D970)
//Duplicate of MC0_MC_CPGC_CMI_P0_REG

#define MC1_MC_CPGC_MISC_DFT_P0_REG                                    (0x0001D974)
//Duplicate of MC0_MC_CPGC_MISC_DFT_P0_REG

#define MC1_PWM_GLB_DRV_OFF_COUNT_P0_REG                               (0x0001D978)
//Duplicate of MC0_PWM_TOTAL_REQCOUNT_P0_REG

#define MC1_PARITYERRLOG_P0_REG                                        (0x0001D9A0)
//Duplicate of MC0_PARITYERRLOG_P0_REG

#define MC1_PARITY_ERR_INJ_P0_REG                                      (0x0001D9A8)
//Duplicate of MC0_PARITY_ERR_INJ_P0_REG

#define MC1_PARITY_CONTROL_P0_REG                                      (0x0001D9B4)
//Duplicate of MC0_PARITY_CONTROL_P0_REG

#define MC1_MC_JEDEC_INIT_TIMING_P0_REG                                (0x0001D9B8)
//Duplicate of MC0_MC_JEDEC_INIT_TIMING_P0_REG

#define MC1_DDRPL_CFG_DTF_P0_REG                                       (0x0001DF00)
//Duplicate of MC0_DDRPL_CFG_DTF_P0_REG

#define MC1_DDRPL_FILTER_DTF_P0_REG                                    (0x0001DF04)
//Duplicate of MC0_DDRPL_FILTER_DTF_P0_REG

#define MC1_DDRPL_DEBUG_DTF_P0_REG                                     (0x0001DF08)
//Duplicate of MC0_DDRPL_DEBUG_DTF_P0_REG

#define MC1_DDRPL_VISA_LANES_P0_REG                                    (0x0001DF0C)
//Duplicate of MC0_DDRPL_VISA_LANES_P0_REG

#define MC1_DDRPL_VISA_CFG_DTF_P0_REG                                  (0x0001DF10)
//Duplicate of MC0_DDRPL_VISA_CFG_DTF_P0_REG
#pragma pack(pop)
#endif
